APPLICATION BULLETIN ® Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952-111 • Telex: 066-6491 • FAX (602) 889-1510 • Immediate Product Info: (800) 548-6132 THE CURRENT-FEEDBACK OP AMP A HIGH-SPEED BUILDING BLOCK 1 By Anthony D. Wang, Burr-Brown Corp. Although current-feedback amplifiers (CFAs) have been in use for quite some time, there is a reluctance to view them in the same light as voltage-feedback amplifiers (VFAs). For instance, the gain-bandwidth curve of VFAs has a parallel in a transimpedance-bandwidth curve for CFAs. This parameter can be used to determine the closed-loop behavior of the CFA in the same way that GBW can for the VFA. Not all the fault is with the users—the amplifier manufacturers have not standardized the CFA characterization as they have done with VFAs. This paper describes the CFA and its behavior in an intuitive manner. 2 The three transistor amplifier of Figure 1 is arranged in a series-shunt configuration. However, in order to analyze the amplifier, the circuit is rearranged as shown in Figure 2. 3 The feedback network shows up in two places—a series network at the output and a parallel network at the emitter of the input transistor. This allows for open-loop analysis while keeping the effects of loading intact. 4 The loading of the output by the feedback network is generally not a problem. However, the gain of the first transistor stage is dependent on the values of the resistors in the feedback network. Thus the open-loop response will change with closed-loop gain (as the feedback network changes), which could make frequency compensation an iterative chore. HISTORICAL PERSPECTIVE The term “operational amplifier,” or “op amp” in typical engineering shorthand, has generally been associated with the transistorized voltage-feedback amplifier. It is becoming more acceptable now to include the current-feedback amplifier in the same category. The discrete transistor circuit of Figure 3 circumvents this difficulty. Adding another transistor, Q4, to buffer the input stage transistor, Q1, from the feedback network illustrates this modification. This is the first step to a voltage feedback amplifier topology. Interestingly enough, the basic architecture for the CFA might have predated the VFA although it was not until the 1980s that the CFA was itself repopularized. To appreciate R1 the evolution of the beast, it helps to look back to some early discrete transistor circuits. R2 R1 R2 Q2 Q2 CT VIN CT Q1 VIN Q3 Q1 Q3 RF VOUT RG VOUT R3 RE = FIGURE 1. Three Transistor Amplifier. RF • RG RF + R G R3 RL = R F + R G FIGURE 2. Amplifier Redrawn for Analysis. AB-193 5 6 R1 R2 Q2 CT Q3 RF VIN Q1 +In –In VOUT Q4 RG VOUT R3 FIGURE 3. Adding a Buffer Transistor. The added transistor presents a high impedance input to the feedback network. It also features the benefits of a balanced input, such as low offset voltage and equal input bias currents. FIGURE 4. Basic CFA Topology. The NPN current mirror of Figure 5a, which provides double-ended to single-ended conversion, still maintains balance in the circuit because the second stage output voltage is determined by the current that flows into the high impedance presented by the collectors. Of greater significance is the fact that the dynamic emitter resistance(1) of the added transistor is substituted for the parallel resistance of the feedback network in Figure 2. The first stage gain, and consequently the open-loop gain, no longer depends on the feedback network. The process of frequency compensation has one less degree of variation to be concerned with. Inspection of Figure 4 shows that the axis of symmetry for the CFA is centered horizontally. Therefore, the half-circuit used for analysis is the same circuit as presented in Figure 1, ignoring the input emitter follower. However, as pointed out previously, the feedback network is closely intertwined with the analysis. Therefore, the circuit of Figure 2 can be used for the analysis. The compensation capacitor, CT, can be the intrinsic base-collector capacitor of Q2 or an extrinsic capacitor deliberately added for compensation. These two circuits illustrate the basic distinctions between current-feedback and voltage-feedback amplifiers. In both cases, the feedback network is connected to an (inverting) input node. In Figure 1, the emitter presents a low impedance input, while in Figure 3 the base presents a high impedance input. The only real difference between Figure 5b and Figure 2 is the presence of the parallel combination of the feedback network resistors in the emitter of the CFA’s input transistor. Needless to say, the three transistor amplifier of Figure 1 can be considered the forebear for the CFA as it is known today, while Figure 3 is the template for the VFA. Figure 4 shows the same amplifier connected to a mirror-image of itself, whose transistors have been converted to the opposite polarity type. The input transistors are buffered by emitter followers for level shifting to ensure low offset voltage. This is the basis of the modern current-feedback architecture. The CFA analysis is straightforward and the DC gain can be determined by inspection of Figure 2. A VDC = R1 R 3 • RE R2 The open-loop pole can be approximated quite accurately as the interaction of the resistor, R1, with the Miller multiplied capacitor, CT. ANALYZING THE CFA The study of the differential input, voltage-feedback amplifier is simplified with a technique known as “half-circuit analysis.” This technique, illustrated in Figure 5, recognizes that the symmetry of the circuit presents an opportunity for simplification whereby only half the signal path needs to be considered. ωP ≅ 1 R R1 3 • C T R2 This analysis presumes that re1, the dynamic emitter resistance of Q1, can be neglected (RE>>re1) and that R2 includes re2. NOTE: (1) The dynamic emitter resistance is tangent to the slope of the I-V curve for the base-emitter diode 2 –In +In VOUT FIGURE 5a. Basic VFA Topology. Removing RE, the feedback network term, from the equation for open-loop voltage gain yields a more general expression that describes the amplifier’s open-loop performance in terms of its intrinsic characteristics. This equation would have units of ohms and would be better identified as a complex impedance, or transimpedance, ZT: +1 ZT = VOUT RT 1 + jωR T C T This is the true measure of performance for CFAs. It is now obvious why the amplifier is known as “current-feedback.” The output voltage is responsive to a current at the low impedance inverting input node (the emitter of Q1) that interacts with the open-loop transimpedance, ZT. +In FIGURE 5b. VFA Half-Circuit. Furthermore, the open-loop response of the amplifier is completely described by the DC transresistance, RT, and the compensation capacitor, C T , which is called the transcapacitance. RT interacts with CT to form the open-loop pole. This is graphically depicted in Figure 6. It would be convenient at this point to define the transresistance as: RT = R1 • R 3 R2 ZT Note that the transresistance has the dimensions of ohms and is determined solely by elements internal to the amplifier. The previous equations can be rewritten more simply. A VDC = RT RE and ω P = RT 1 R T • CT Now the open-loop gain can be completely described by: AV = RT R 1 1 • = T• RE 1 + j ω R E 1 + jωR T C T ωP In order to arrive at this equation, it was assumed that the feedback network was known. This is the crux of the issue— the open-loop voltage gain of a CFA depends on the value of the feedback network. (RTCT)–1 FIGURE 6. Open-Loop Transimpedance. 3 log ω The DC value of closed-loop gain is set by the feedback network, while the closed-loop pole is determined by the interaction of the transcapacitance with the feedback resistor. This latter term is what gives the CFA its much touted characteristic of gain-independent bandwidth. The ordinate axis has the dimension of ohms and is scaled logarithmically. Having described the CFA with just two components suggests a simplified version of the half-circuit used for analysis. Figure 7 shows a convenient model that has all the essentials necessary for quick hand calculations. The inverting buffer preserves the sense of the signal as it is amplified by the Q2 stage in Figure 2. RT Figure 8 illustrates graphically that the open-loop gain curve slides vertically to keep the closed-loop intercept frequency constant. Since RF is kept constant, the area of the curve above the closed-loop gain stays constant. CT –1 +In A closer look at the unsimplified equation for the closedloop gain helps to clarify this property. The DC portion of open-loop gain in the numerator is modified by the parallel combination of the feedback network, which changes with desired closed-loop gain. As long as RF is kept constant, the loop gain expression in the denominator does not vary, nor do any of the frequency dependent terms. VOUT Q1 RL = RF + RG –In AV RF • RG RE = RF + RG RT RE´ RT RE FIGURE 7. CFA Model for AC Analysis. When determining which op amp to use for an application, comparisons with voltage-feedback amplifiers will inevitably be made. Presumably the closed-loop gain is known, which means that a feedback network can be established. Therefore, the open-loop voltage gain can be calculated for the CFA and a fair comparison with VFA can be established. RF RE´ RF RE Note that the analysis described here is based on a fairly simple current-feedback topology. Although the design of integrated circuit CFAs has become more sophisticated, the open-loop transimpedance approach (ZT) is still valid. (RTCT)–1 AV 1 + AV • β where β = The closed-loop gain expressions have been expressed as a ratio of the feedback resistor to the equivalent feedback network. This can be verified algebraically as: R + RG RF RF = = F RE RF • RG RG RF + RG RG RF + RG Substituting for AV yields the following expression: Thus, the open-loop gain varies directly with the closed-loop gain for changes in RE as long as RF is kept constant. RT 1 • R E 1 + jωR T C T Open–Loop Gain A CL = = RF Loop Gain 1+ + jωR F C T RT RT • RF 1 + jωR T C T The loop gain, of course, limits the accuracy of the closedloop gain. Note that RT>>RF (typically RT>100k and RF<5k), therefore the equation can be easily simplified to: A CL = log ω FIGURE 8. Variation of Open-Loop Gain. CLOSED-LOOP PERFORMANCE The closed-loop response of the CFA can be described by using classical analysis: A CL = (RFCT)–1 RF + RG 1 • RG 1 + jωR F C T 4 NONIDEAL CONSIDERATIONS The assumption that the re of Q1 can be neglected has limits. For ease of analysis, Figure 6 has been redrawn to include it as a finite input resistance, RIN (Figure 9). Note that RIN is internal to the CFA terminals. The second generalization is that the closed-loop bandwidth will become gain-bandwidth limited when R IN ≥ R F ⇔ R IN ≥ R E β The latter expression makes use of the fact that the feedback factor, β, is a function of the feedback network resistors. Once this limit has been reached, the CFA can be associated with a gain-bandwidth product, GBW. RT CT GBW = 1 R IN C T VOUT –1 The graph in Figure 10 shows an asymptotic approach to estimating a CFA’s closed-loop response. +In RL = RF + RG RIN –In RE = AV RF • RG RF + RG RT RIN FIGURE 9. CFA Model Modified for Finite RIN. The open-loop gain equation can be modified by inspection, while a new closed-loop gain equation can again be derived using the classical approach. RF RIN RT 1 AV = • R E + R IN 1 + jωR T C T A CL = RF + RG • RG 1 R 1 + jω R F + IN C T β (RTCT)–1 RIN decreases the open-loop gain but not its corner frequency. On the other hand, RIN does not affect the DC closed-loop gain but does modify the intercept frequency. In practice, RIN includes more than just the dynamic emitter resistance—it also includes bulk resistances that are in series with the inverting input, as well as parasitic resistances external to the amplifier. Obviously, RIN should be as low as possible to get the maximum benefit from a CFA. (RINCT)–1 log ω FIGURE 10. CFA Closed-Loop Performance. To be technically accurate, it should be pointed out that the inverting input is characterized by an impedance, ZIN, which does vary with frequency. Fortunately, the resistive portion, RIN, dominates over most of the CFA’s useful bandwidth. At high frequency, the inverting input impedance increases, which only further degrades the closed-loop performance, although the extent of the increase is generally well under an order of magnitude. The modified equations lead to some practical generalizations when using CFAs. The first is that the open-loop gain has a theoretical maximum and this can be conveniently estimated as: A V(max) ≅ (RFCT)–1 FREQUENCY COMPENSATION The analysis so far has centered on the gain versus frequency performance without taking into account any phase shift considerations. Excess phase plagues the CFA just as it does the VFA. The open-loop transimpedance curve of Figure 6 depicts a single-pole response which would have only 90° of phase shift. Parasitic poles introduce additional phase shift to the open-loop phase response. Figure 11 displays the more complete open-loop transfer curves—both magnitude and phase. RT 1 • R IN 1 + jωR T C T This is an ideal value that can never be realized since any feedback network will automatically reduce the open-loop gain. However, it is useful for estimating a CFA’s merits against a particular VFA. 5 ZT UNITY GAIN FREQUENCY RESPONSE vs PHASE MARGIN 5 RT 45° 0 Gain (dB) –5 60° 90° –10 75° –15 –20 ZT(f1) –25 fi/100 fi 10fi Relative Frequency log ω (RTCT)–1 fi/10 fi FIGURE 12. Phase Margin’s Effect on Frequency Response. 0° A more general way of looking at this is to make the observation that the closed-loop response can be extended if the open-loop phase has fallen 120° at fi, the frequency where the asymptote for closed-loop gain intersects the open-loop gain curve. –45° –90° In VFAs, the phase margin is set by design and the user does not change it. There are a few amplifiers which allow access to the high impedance node to tailor compensation, but these are in the minority. In general, VFAs break out into two categories—compensated and decompensated. –135° ØM –180° Ø The compensated amplifiers allow operation at unity gain but at the expense of bandwidth in higher gains. Decompensated, or undercompensated, amplifiers must be operated in gains greater than unity but have a higher gain-bandwidth product. In either case, the phase margin is predetermined. FIGURE 11. CFA Open-Loop Transfer Curves. Since the feedback network sets the open-loop gain for the CFA, it also sets the phase margin, ΦM. This is the crucial factor that actually determines the selection of the feedback network resistors. For the CFA, phase margin is set by the user via the feedback network. However, rather than use phase margin as the design criterion, higher performance can be attained by making use of the general observations regarding phase shift and bandwidth. In other words, guarantee that the open-loop phase has fallen 120° at fi. The significance of phase margin would benefit from a brief review of its properties. Phase margin for operational amplifiers is measured at that frequency, fU, where an amplifier’s open-loop voltage gain has fallen to unity. It is the difference between the open-loop phase shift and –180°, where the amplifier would lose negative feedback and become unstable. The mechanics are rather straightforward because, as illustrated in Figure 8, varying the feedback network causes a simple vertical translation of the open-loop gain curve. The open-loop pole does not move and so the attendant openloop phase shift is unaffected. The excess phase shift is also insensitive to the feedback network change. Thus, selection of a desired phase shift automatically sets the intercept frequency. Φ M = Φ(f U ) − (−180° ) The concept of phase margin is best illustrated by plotting unity gain frequency response curves as phase margin is varied (Figure 12). Once the intercept frequency, fi, is determined, so is the magnitude of transimpedance, ZT(fi). This is depicted graphically in Figure 11 by following the dashed lines up from the open-loop phase curve to the intersection with the open-loop transimpedance curve. As the plot shows, the optimum value for phase margin is 60°. This gives the desirable combination of broad bandwidth with flat frequency response. Note that an amplifier with 90° of phase margin, which implies a lack of excess phase, has a –3dB bandwidth less than half of the optimum response. 6 To realize the benefit of the –120° phase shift, the feedback network has to be selected so that the open-loop gain equals the closed-loop gain at fi. A convenient way to visualize this problem is to concentrate on the essentials of the model in Figure 9. MODEL REPRESENTATION The single transistor model of Figure 9 is a satisfactory vehicle to provide intuitive insight. It is by no means an accurate representation of the CFA but offers a good visual aid for the user. The CFA model can be simplified further by ignoring the inverting buffer and focusing on that portion of the circuit which provides gain. In Figure 13 the CFA model has been reduced to an elementary transistor amplifier. The gain for this circuit is A more generally accepted model for the CFA is depicted in Figure 14. This model is a very faithful rendition of the CFA from a block diagram standpoint. It can accurately account for the bipolar input and output swings that are possible with the CFA’s complementary symmetry. AV = Comparing it to Figure 4, it is readily apparent that the unity gain buffer at the input is an accurate portrayal of the input stage between the input pins. The finite input resistance, RIN, is included for completeness. Z T (f i ) R E + R IN ZT(fi) VOUT +In Q1 +In RIN +1 –In RE = +1 RF • RG RF + RG RIN IIN RT VOUT CT –In IIN FIGURE 13. Elementary Amplifier. The goal, therefore, is to select the necessary feedback network so that AV equals the desired closed-loop gain. Since ZT has previously been defined as a complex impedance, direct substitution yields a closed form solution. RF + RT RG FIGURE 14. Block Diagram CFA Model. RT 1 + j2πf i R T C T Z T (f i ) = = R E + R IN R E + R IN The current-controlled current source, IIN, translates the current from the inverting input to the open-loop transimpedance, again composed of RT and CT. The unitygain buffer provides a low impedance source to the external load. which can be reduced to a less bulky equation: RF ≅ R 1 − IN β 2πf i C T Either of the models is sufficient to appreciate the CFA and its performance features. Figure 9 bears a strong resemblance to the ancestral antecedent of the CFA while the latter is more readily adaptable to generating a SPICE macromodel. Not surprisingly, this expression conforms to the plot of CFA closed-loop performance (Figure 10). For low gains, the RIN term is negligible and RF is set by fi. As closed-loop gain increases and RIN/β can no longer be neglected, RF should be adjusted according to the equation to maintain optimum performance. When RF approaches zero, the CFA is becoming gain-bandwidth limited and the intercept frequency must be lowered. Other properties of the CFA are apparent when studying these models. The slew rate is limited by the current available to charge the transcapacitance. Decreasing (RIN + RE) will certainly benefit slew performance. Minimizing CT will increase slew rate as well as the small-signal performance. 7 Potential for trouble exists when parasitic capacitance is present at the inverting input. This parasitic capacitance can be the result of poor layout techniques, inappropriate use of a socket or even the wrong package. If CP is the lumped parasitic capacitor, the open-loop gain will become: AV = RT • R E + R IN It is not very common practice to specify power supply rejection for each supply separately but, for the CFA, it is essential. The complementary devices, NPN and PNP, should not be expected to match each other closely and usually the PNPs are the weaker. PSR measured with tracking supplies typically tend to partially cancel the errors. Real world applications usually rely on independent positive and negative voltage regulators. 1 + jωR E C P R •R (1 + jωR T C T )1 + jω R E + RIN C P E IN The table below is for a medium performance CFA and exemplifies the amount of detail that should be provided. This expression has added a zero and a pole to the transfer function. The zero will always occur before the pole and can be the source of trouble in some cases. If instability arises because of CP, move the closed-loop pole to a lower frequency by adjusting the feedback network. PARAMETER To model excess phase, the addition of a delay line can be more expedient than trying to add multiple poles and zeroes to the open-loop transimpedance. The modified transfer function is still quite compact. RT ZT = • e − jωTD 1 + jωR T C T The exponential adds phase shift without affecting magnitude. A reasonable technique is to use the phase shift at the highest intercept frequency the circuit is expected to encounter. 1 TD = Φ(f i ) − 90° 2πf i • 360° Here, subtracting 90° from the open-loop phase, Φ(fi), removes the phase shift due to the open-loop pole. TYP UNIT INPUT OFFSET VOLTAGE Initial vs Temperature vs Common-mode vs Supply (Tracking) vs Supply (Non-tracking) 5 8 60 85 60 mV µV/°C dB dB dB +INPUT BIAS CURRENT Initial vs Temperature vs Common-mode vs Supply (Tracking) vs Supply (Non-tracking) 5 30 200 50 150 µA nA/°C nA/V nA/V nA/V –INPUT BIAS CURRENT Initial vs Temperature vs Common-mode vs Supply (Tracking) vs Supply (Non-tracking) 25 300 200 300 1500 µA nA/°C nA/V nA/V nA/V 5M || 2 30 || 2 Ω || pF Ω || pF OPEN-LOOP TRANSIMPEDANCE Transresistance Transcapacitance 440 1.8 kΩ pF OUTPUT CHARACTERISTICS Voltage Current Output resistance, Open-loop 12 150 70 V mA Ω INPUT IMPEDANCE +Input –Input DATA SHEET SPECIFICATIONS The open-loop transimpedance terms, RT and CT, and the input resistance, RIN, have already been identified as necessary features to describe a CFA. Additionally, the open-loop transimpedance and phase versus frequency curves should be provided as well. TABLE I. Source: BB OPA603 Data Sheet. The block diagram presentation of Figure 14 suggests the other specifications that should not be overlooked. The presence of a buffer between the noninverting and inverting inputs of the CFA guarantees that the input characteristics will not match. This is the main difference between the VFA and the CFA data sheets. SPICE SIMULATION The combination of declining hardware costs with increasing computing horsepower has made circuit simulation a required part of the design cycle. This has forced the op amp vendors to supply the macromodels for their product offerings. The VFA data sheet typically specifies the power supply and common-mode rejection for the offset voltage only. The input bias currents are also subject to disturbances from these sources but good VFA design encourages matching impedances at the inputs to mask the effects. These simulation tools have been offered in varying degrees of complexity, from the simple Boyle model to simplified circuit models, which utilize full transistor models in the signal path. There has been a growing consensus that this latter approach is necessary for the high bandwidth amplifiers. The CFA does not have the privilege of bias current match, so the same effects that are specified for the offset voltage need to be measured for the two input currents. In particular, the inverting input, which is the true signal input is often the biggest source of error. It is not uncommon to see a CFA constrained to operate in an inverting gain configuration to circumvent common-mode effects. 8 The circuit of Figure 15a was simulated with the following listing: There can be no doubt that having these models available helps to fill in the gaps from incomplete data sheets. Although the models may not necessarily be configured for worst case process extremes, there may be some performance peculiarities that can be discovered through their use. The pitfall to be aware of is that even the simplified circuit models generally idealize the biasing circuitry, which may mask some second order PSR and CMR effects. * CURRENT-FEEDBACK OPEN-LOOP SIMULATION * * file: CFA-OL.CIR ***** Simulation Commands ***** .options noecho nomod numdgt=8 .op .ac dec 20 10 200meg .probe ***** Library Files ***** .lib burr_brn.lib ***** Circuit Listing ***** vp 7 0 15 vm 4 0 -15 *ginv 2 0 6 0 -1 inv 2 0 dc -38.3pa ac 1 x603 0 2 7 4 6 opa603 rl 6 0 100k .end Figure 15 shows two alternative simulation schemes. In Figure 15a, the CFA is driven open-loop to measure the open-loop transimpedance and input resistance. This requires two separate simulations. The first uses a voltagecontrolled current source to find the dc value of inverting input current to servo the output to zero. The second pass is the ac simulation to actually measure the transimpedance. VDIF Figure 16a is the plot of input resistance as measured by dividing the ac voltage by the ac current. Note that for the useful frequency range of the amplifier (roughly 100MHz), RIN varies less than 10Ω. The open-loop transimpedance is displayed in Figure 16b. Here the magnitude has fallen from a DC value of 790kΩ to 1.5kΩ at 51.6MHz, which is where the open-loop phase has fallen to –120°. VOUT RL CL IIN FIGURE 15a. Open-Loop Simulation. Figure 15b uses a zero volt battery to measure the inverting input current while the op amp is in a closed-loop configuration. This measures an effective transimpedance that includes the common-mode effect. VDIF VOUT RL FIGURE 16a. Measuring the Inverting Input Impedance. CL VINV RF RG FIGURE 15b. In Circuit Measurement. FIGURE 16b. Measuring Open-Loop Transimpedance. 9 MEASUREMENT CIRCUITS If companies could ship only simulation files to their customers, life would be so easy. Sooner or later, a reality check has to be made. The following circuits have been proven to be quite reliable for measuring the CFA performance parameters. The circuit of Figure 15b was simulated with the following listing: * CURRENT-FEEDBACK CLOSED-LOOP SIMULATION * * file: CFA-CL.CIR ***** Simulation Commands ***** .options noecho nomod .ac dec 20 1000 200meg .probe ***** Library Files ***** .lib burr_brn.lib ***** Circuit Listing ***** vp 7 0 15 vm 4 0 -15 vin 3 0 dc 0 ac 1 x603 3 inv 7 4 6 opa603 vinv inv 2 dc 0 rf 6 2 1450 rg 2 0 1450 .end The low impedance of the inverting input node presents a special problem for the test engineer. Conventional op amp test circuits cannot easily separate the individual parameter variations. The most logical solution is to test the CFA with a current mode test circuit. Figure 18 shows the basic current pump topology used in the DC test circuit. It consists of a JFET input op amp, a Pchannel MOSFET and a unique current reference circuit which includes two very accurate current sources and a high precision current mirror. The plot in Figure 17 shows the intersection of the open-loop gain curve with the closed-loop gain asymptote which occurs at 45.7MHz. The open-loop phase has the value of –120° at this frequency and the broadbanding of the closedloop gain is quite evident. Note the technique used to generate the open-loop gain curve. IS1 100µA The equation relies on the calculation of open-loop transimpedance (via the current in the battery) which is divided by the sum of the equivalent feedback network plus the input resistance. IS2 100µA RIN VIN RL 1/2 OPA2111 vm(output) Z T (f i ) im(battery) AV = = R E + R IN R E + R IN REF200 FIGURE 18. Current Pump Topology. The high gain of the JFET input op amp (VFA) constrains its inverting input to stay at null ground by controlling the current flowing through the MOSFET. If VIN is positive, a current equal to VIN/RIN is shunted to the current mirror input. If VIN is negative, a matching VIN/RIN is provided by the 100µA current source, IS1, and the input to the current mirror decreases. This is an inverting current pump, a positive voltage causes the output to sink current and a negative input causes the output to source current. FIGURE 17. Slope Intercept Curves for CFA Circuit. 10 The full test circuit is shown in Figure 20. The input offset voltage of the DUT is measured directly by the instrumentation amplifier, A1. The RC filters minimize noise and protect the inputs of A1 from overload transients. integrator servos the output to zero by sensing the DUT output and feeding a small current back to the input. A2 buffers the DUT output and drives the 50Ω input of the network analyzer. Amplifier A2 maintains the common-mode bias by forcing the current pump (A3, M1, IC1) to keep the noninverting input of the DUT equal to the input, VCM. The output of A2 driving the 100kΩ input resistor to the current pump is a measure of +Ib. The only caveat is to take into account the gain and phase rolloff of A2. Automated network analyzers allow for compensation by storing an “offset” sweep which is subtracted from the actual signal sweep. Although the network analyzer will scale the output in dB, the transimpedance can be determined by using the following equation: Amplifier A4 constrains the DUT output to be the negative of the input voltage, Vf, by forcing the current pump (A5, M2, IC2) to drive the low impedance inverting input. The amount of inverting current drive is reflected by the output of A4. Z T = 500 • log −1 All DC parameters, including RT and RIN, can be measured independently and directly. When adapted to a measurement card for the HP Semiconductor Analyzer, the test parameters can be displayed as slopes to determine the limits of linearity. dB magnitude 20 The transcapacitance can be found by extrapolating the open-loop pole. CONCLUSION Figure 19 details an open-loop transimpedance test circuit which, when mated with a network analyzer, will provide the open-loop frequency response curves. CFAs are not difficult to comprehend and work with if the basic relationships between RT, CT, RIN and open-loop phase are kept in mind. The lack of balanced input nodes require extra care be taken with applications requiring DC accuracy. Simulation is a wonderful tool for the early design stages but only actual measurements will grant peace of mind. The input ladder network divides the input by 20,000 to provide a low current level signal to the inverting input of the DUT. The 500Ω value for the input resistor dominates the small but finite input resistance of the CFA. The A1 0.2µF 500kΩ 0.4µF A1 A1: OPA177 A2: OPA621 NOTE: (1) Short these points to compensate test circuit. 500kΩ 100kΩ 100Ω 9750Ω DUT 500Ω 50Ω VIN A2 CL 50Ω 500Ω RL (1) 250Ω 250Ω (1) FIGURE 19. Open-Loop Frequency Response Test Circuit. 11 VOUT 100kΩ A2 A3 +IB IC1 M1 1000pF 100kΩ VCM 10kΩ +VS 1000pF 100kΩ VOS A1 x200 VOUT DUT 100kΩ 1000pF –VS A1: INA110 A1–A5: 1/2 OPA2111 IC1–IC2: REF200 M1–M2: VPO300 200kΩ 1000pF 200kΩ Vf A5 M2 IC2 A4 100kΩ –IB FIGURE 20. Current Mode CFA Test Circuit. 12

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