® NEW SOFTWARE FOR THE DDC112 EVALUATION FIXTURE By Jim Todsen This application bulletin describes the operation of a new version, Ver 2.0, of the evaluation software. Available for download from Burr-Brown’s web site, this new software keeps the same look and feel as the original version while adding additional features. This application bulletin assumes you are familiar with the basic operation of the DDC112 and have used the earlier version of the software. Only the new features are discussed. When running the DDC112 Evaluation Fixture for the first time, get a copy of the data sheet for the DDC112’s Evaluation Fixture DEM-DDC112U-C which explains how to use the original version of the software and read it first. The explanations will still be helpful as the basic operation of the software has not changed with Ver 2.0. Setup Data Analysis [ [ As with the earlier version, Ver 2.0 runs under DOS using a mouse-based windows environment. Figure 1 shows the main window at startup. It can be run under Windows 95 or 98 using a DOS program shortcut. Ver 2.0 uses the same name, “DDC112.CFG”, for the ASCII file that stores the software configuration and, as with the earlier version, if the software finds this file when loading, it uses it to set the various parameters such as the DDC112’s range, integration time, etc. When this file can’t be found, the software uses the default values. Any changes made to the settings in the course of running the software are saved upon exiting. Ver 2.0 does add two additional parameters to the configuration file: SCLK Speed and Osc Freq. Table I shows the complete Calibration Misc Info DDC112 Ver 2.0 This software is designed for use with the DDC112 Evaluation Fixture DEM-DDC112U-C which consists of the PC Interface Board and the DUT Board. Ok Alt-X Exit Burr-Brown Corporation DDC112 FIGURE 1. Software Startup Screen. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. © 1999 Burr-Brown Corporation AB-144 Printed in U.S.A. February, 1999 PARAMETER DEFAULT VALUE DDC112 Range COMMENTS 250pC In units of µs 500 TINT CONV Source 0 Number of DDC112s on DUT Board 1 0 → demo board DCLK Setting 3 3 → DCLK= osc freq / 2 (this is NOT the value of Xilinx register 0). DXMIT Delay 0 Delay in µs between DVALID falling and DXMIT falling. Test Status 0 0→ OFF, 1→ ON Number of Test Pulses 1 Retrieval Option Separate Number of Points to Retrieve Retrieve A and B separately. 1024 FFT Window Hamming PC Interface Board Parallel Port 0 0→ LPT1 Printer Parallel Port 1 1→ LPT2 Ctrl 2 0 Xilinx register 7, see Table II. SCLK Speed 0 Xilinx register 1, see Table II. Osc Frequency 20.0 Frequency of oscillator U7 on PC Interface Board. TABLE I. Parameters Stored in the Configuration File DDC112.CFG. and then is afterwards reset. When CONV toggles, the sides switch and the ADC measures the side that had been integrating while the previously-measured side integrates. Therefore, the input current is always being integrated by one of the two sides. This implies continuous mode operation. To allow for very short integration times, noncontinuous operation is possible. See Application Bulletin AB-131 “Understanding the DDC112’s Continuous and Non-Continuous Modes.” One consequence of the DDC112’s technique for providing continuous integration is that two integrators supply data for one input. That is, the data alternates between coming from sides A and B. This needs to be considered when designing the system calibration. Due to process variations, the two integrators will have slightly different offsets and gains. When using external capacitors, the gain mismatch will depend on the mismatch of the capacitors. To remove these mismatches between the sides, offset and gain calibration must be used on both sides. This calibration is not needed if data from only one side is used. For example, collect only side A data and ignore data from side B. Of course, this is not acceptable in many applications as the input signal is no longer continuously integrated and the data rate is cut in half. set of parameters stored in the configuration file. Ver 2.0 is backwards-compatible in that it can read the old configuration files and then uses default values for the two new parameters. The three main pop-down menus, Setup, Data and Analysis, remain mostly the same with Ver 2.0. A new feature, Restore Defaults, was added to return the software to its default state. Minor cleanup was also made to the appearance of the menus and their text. Two additional menus, Calibration and Misc, were added and these are explained in the Calibration section. Finally, a bug in Ver 1.2 was fixed so the program can now run on faster computers (>200MHz). CALIBRATION Before explaining how the calibration works in the software, a brief review of the DDC112 may help. The DDC112 uses two integrators per input to provide continuous integration of the input signal. Figure 2 shows a simplified diagram of the two-integrator structure for one of the DDC112’s inputs. While one integrator or side is integrating the input current, the other is being measured by the DDC112’s internal ADC The software calibration routines in Ver 2.0 allow for both offset and gain calibration of the DDC112’s data. The offset is first subtracted from the raw DDC112 data with the result then multiplied by the gain coefficient. In equation form, the calibrated data is: Side A Input Datacalibrated = ( Dataraw – Offset) • Gain Output to Voltage ADC (1) The calibration is applied on an individual side basis. That is, separate coefficients are used for each side: 1A, 1B, 2A and 2B. The default values are 0 for the offset coefficients and 1 for the gain coefficients. There are two ways to access the software calibration routines, either by using the calibration menu or by using specially defined keys in the time plot window. Side B FIGURE 2. Simplified Diagram of One DDC112 Input. 2 Calibration Menu 1A (still set at the default value of 0). Figure 4 shows the offset for side 1A being set to 0.0001. The Calibration pop-down menu has three functions: Offset Cal, Gain Cal, and Status of Cal. Gain Cal Offset Cal This function is identical to Offset Cal except that the gain calibration coefficients can be displayed and set. This function allows you to display and to set the offset calibration coefficients. Figure 3 shows the offset for side Setup Data Analysis Calibration Misc Info Offset Calibration (*) ( ) Display Current Cal Manually Set Cal Ok Cancel [ [ #1A Current Offset: 0.0000000 Next Alt-X Exit Burr-Brown Corporation DDC112 FIGURE 3. Menu for Displaying Offset Calibration Coefficients. Setup Data Analysis Calibration Misc Info Offset Calibration ( ) (*) Display Current Cal Manually Set Cal Ok Cancel [ [ #1A Offset Value 0.0001_ Ok Alt-X Exit Cancel Burr-Brown Corporation FIGURE 4. Menu for Setting Offset Calibration Coefficients. 3 DDC112 Status of Cal Alt-O : Autofind Offset Calibration This function, shown in Figure 5, turns the software calibration on or off. When on, the data retrieved from the DDC112 automatically has both the offset and gain calibration applied before being displayed. Once the calibration has been applied to the data, there is no easy way to undo it. The calibration must be turned off and new data retrieved. Turning the software calibration off does not reset the values of the calibration coefficients. Alt-G : Autofind Gain Calibration Time Plot Calibration Control 3) Hit Alt-O. The offset coefficients are now set to the data’s average values. Alt-T : Toggle Calibration Status (On/Off) Autofind Offset Calibration This function automatically sets the offset coefficients. To use this feature: 1) Apply a zero-level signal to the DDC112’s inputs. 2) Retrieve data with the “Separate” option selected. In addition to the Calibration pop-down menu, the calibration routines can also be controlled in the Time Plot window. Three special keys are defined for calibration in the time plots: Setup Data Analysis After running the autofind offset calibration, the calibration will be turned on and the data’s average value will be equal to zero as shown in Figure 6. Calibration [ [ Misc Calibration (*) ( ) Ok Alt-X Exit Info Off On Cancel Burr-Brown Corporation FIGURE 5. Menu for Turning Calibration On or Off. FIGURE 6. Time Plot Display After Autofind Offset Calibration. 4 DDC112 Autofind Gain Calibration Toggle Calibration Status (On/Off) This function automatically sets the gain coefficients. The offset calibration should be set before running this function. To use this feature: Alt-T toggles the calibration status. When the calibration is turned off, the coefficients are not reset. Afterwards, the calibration can be turned back on with the coefficients still set. 1) Make sure the offset calibration is set. 2) Apply a full-scale level to the DDC112’s inputs. CUSTOMIZATION Ver 2.0 allows you to customize the evaluation fixture by overriding some of the settings in the Xilinx registers on the PC Interface Board. The customization is controlled under the Misc menu. The first menu item, Xilinx Regs, is shown in Figure 7 and displays the current status of the registers on the PC Interface Board. These registers control the operation of the evaluation fixture. They set the clock speeds, integration time, test mode status, etc. The registers with a “Y” in 3) Retrieve data with “Separate” option selected. 4) Hit Alt-G. Now the gain coefficients for B sides are automatically set so that the A and B side data are the same. Once the gain calibration is set, data can be retrieved with both offset and gain calibrations applied. Data can also be retrieved either separately or as is more likely with “Together” selected. Setup Data Analysis Calibration Misc [ [ Info Xilinx Registers Reg Function Value Edit 0 1 2-5 6 7 8-9 10 11 DCLK Speed SCLK Speed CONV Timing Ctr1 1 Ctr1 2 DXMIT Delay # of DDC112s Test Mode 0 0 4999 39 0 0 1 127 Y Y N Y Y N N N Reg # = Reg Value = Ok Alt-X Exit 0 0 Cancel Burr-Brown Corporation FIGURE 7. Menu for Displaying and Setting Xilinx Registers on PC Interface Board. 5 DDC112 the Edit column can be changed in this window. To do so, enter the register number and desired value in the appropriate fields at the bottom of the window. After clicking “OK”, the selected register will be updated. Some registers are not editable because they can be directly changed using the existing software controls. For example, registers 2-5 (CONV Timing) can be changed in the Setup/Timing window. Table II lists a brief definition of each register. For a more complete explanation of the registers and their functions see “Customizing the DDC112’s Evaluation Fixture”, AB-125. One of the nice features of the DDC112’s virtual ground input is that signals from multiple voltage sources sum together inherently at the input. Caddock’s MK632 series of high-valued resistors with low voltage-coefficients were used. The DDC112’s integration time and range were set to 500µs and 350pC, respectively. 10MΩ The second Misc menu item, Oscillator Freq, allows you to have the software recognize when you have changed the oscillator frequency on the PC Interface Board. IN2 VAC DDC112 IN1 10MΩ EXAMPLE OF CALIBRATION This final section presents some measurement results to help illustrate the operation of the software calibration routines. The measurements were taken using the setup shown in Figure 8. A low-distortion sine wave generator and a lownoise DC source were adjusted to produce a 21Hz sine wave with a full-scale peak-to-peak amplitude. REGISTER NAME + VDC FIGURE 8. Sine Wave Input Measurement Circuit. DESCRIPTION 0 DCLK Speed Sets the speed of DCLK by dividing down the oscillator on the PC Interface Board (U7). DCLK = (Osc Freq) / (2N + 2) for N < 8, where N is the register value. Example: if N = 0, then DCLK = Osc Freq / 2. For N = 127, DCLK = Osc Freq 1 SCLK Speed Sets the speed of SCLK by dividing down the oscillator on the PC Interface Board (U7). SCLK = (Osc Freq) /(2N + 2) for N < 8, where N is the register value. Example: if N = 0, then SCLK = Osc Freq / 2. For N = 127, SCLK = Osc Freq 2-5 CONV Timing 6 7 Ctrl 1 Ctrl 2 Sets the CONV period which in turns sets the integration time, TINT. Bit Name Description 0 1 2 3 4 5 6 G0 G1 G2 TEST_EN Unused W/RB DCLK_SOURCE Gain 0, connected to DDC112 G0 input Gain 1, " " " G1 " Gain 2, " " " G2 " Enable test mode "0"→ read RAM to PC, "1"→ write DDC112 data to RAM "0"→ PCIB generated DCLK, "1"→ external DCLK using BNC Bit Name Description 0 1 2 3 4 5 6 CONV_HOLD CONV_LO Unused Unused CONV_X CONV_XSYNC CONV_NEGSYNC Freezes the CONV signal, used when changing TINT Toggle sign of CONV "0"→ PCIB generated CONV, "1"→ external CONV using BNC "0"→ external CONV as is, "1"→ sync'd to SCLK "0"→ CONV sync'd to pos edge of SCLK, "1"→ neg edge 8-9 DXMIT Delay Sets the readback delay; the delay between DVALID and DXMIT. 10 Number of DDC112s Sets the number of DDC112s on the DUT board. 11 Test Mode Sets the number of test charge packets dumped. TABLE II. Description of the Registers. 6 Figure 9 shows a 4096 point FFT of side 1A’s data. That is, the data was retrieved from just side 1A using the software’s separate option—no calibration was applied. Figure 9 illustrates the performance that can be achieved by a single integrator. ponents at the high end of the frequency spectrum. These were not present in Figure 9 and are due to the offset and gain mismatch between the two sides. The offset mismatch produces a tone at fS/2: 1kHz for a 500µs integration time. The gain mismatch causes the input signal to mix with fS/2, producing a tone at (fS/2 – fINPUT). The gain mismatch also produces an fS/2 tone from the DC component of the sine wave. The plot in Figure 10 shows the FFT for input 1 data. This data was from both side A and B and was retrieved using the “Together” option without calibration. Notice the two com- FIGURE 9. FFT for Side 1A Data Retrieved “Separate”. FIGURE 10. FFT Sides 1A and 1B Data Retrieved “Together”—No Calibration. 7 Finally, Figure 12 shows the FFT for input 1 with offset and gain calibration. The offset was calibrated as previously described. Afterwards the gain was then calibrated by setting the AC source to zero and applying a full-scale DC signal. The tones present in Figures 10 and 11 are now drastically reduced. This is reflected in the AC parameters SNR, SNDR and SFDR. These measurements for the FFT using data from both sides 1A and 1B are nearly identical with those from a single side as shown in Figure 9. That is, the offset and gain calibration allow the combination of the two sides into a single data channel with minimal performance loss. Figure 11 again shows the FFT for input 1 data retrieved using the “Together” option but this time with offset calibration applied. The offset was first calibrated by setting both signal sources to zero and autofinding the offset cal on data retrieved separately. It’s better to set the signal sources to zero rather than disconnect them as the offset is dependent on the loading at the input. As can be seen, the fS/2 component is lower but the (fS/2 – fINPUT) tone is basically unchanged. Though not obvious from these plots, offsetonly calibration may be acceptable in many applications, in particular those with stringent requirements at low-level signals that ease as the signal levels increase. FIGURE 11. FFT for Sides 1A and 1B Data Retrieved “Together”—Offset Calibration. FIGURE 12. FFT for Sides 1A and 1B Data Retrieved “Together”—Offset and Gain Calibration. 8