3 MSPS, 14-Bit SAR ADC AD7484 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND CBIAS 2.5V REFERENCE DVDD VDRIVE DGND BUF REFSEL VIN REFOUT REFIN 14-BIT ALGORITHMIC SAR T/H AD7484 CONTROL LOGIC AND I/O REGISTERS D14 D13 D12 D11 D10 D9 D8 D7 02642-001 MODE1 MODE2 CLIP NAP STBY RESET CONVST CS RD WRITE BUSY D0 D1 D2 D3 D4 D5 D6 Fast throughput rate: 3 MSPS Wide input bandwidth: 40 MHz No pipeline delays with SAR ADC Excellent dc accuracy performance 2 parallel interface modes Low power: 90 mW (full power) and 2.5 mW (nap mode) Standby mode: 2 μA maximum Single 5 V supply operation Internal 2.5 V reference Full-scale overrange mode (using 15th bit) System offset removal via user access offset register Nominal 0 V to 2.5 V input with shifted range capability Pin compatible upgrade of 12-bit AD7482 Figure 1. GENERAL DESCRIPTION The AD7484 is a 14-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz. The conversion process is a proprietary algorithmic successive approximation technique that results in no pipeline delays. The input signal is sampled, and a conversion is initiated on the falling edge of the CONVST signal. The conversion process is controlled by an internally trimmed oscillator. Interfacing is via standard parallel signal lines, making the part directly compatible with microcontrollers and DSPs. The AD7484 provides excellent ac and dc performance specifications. Factory trimming ensures high dc accuracy, resulting in very low INL, offset, and gain errors. The part uses advanced design techniques to achieve very low power dissipation at high throughput rates. Power consumption in the normal mode of operation is 90 mW. There are two power saving modes: a nap mode, which keeps the reference circuitry alive for a quick power-up while consuming 2.5 mW, and a standby mode that reduces power consumption to a mere 10 μW. The AD7484 features an on-board 2.5 V reference but can also accommodate an externally provided 2.5 V reference source. The nominal analog input range is 0 V to 2.5 V, but an offset shift capability allows this nominal range to be offset by ±200 mV. This allows the user considerable flexibility in setting the bottom end reference point of the signal range, a useful feature when using single-supply op amps. The AD7484 also provides an 8% overrange capability via a 15th bit. Therefore, if the analog input range strays outside the nominal range by up to 8%, the user can still accurately resolve the signal by using the 15th bit. The AD7484 is powered by a 4.75 V to 5.25 V supply. The part also provides a VDRIVE pin that allows the user to set the voltage levels for the digital interface lines. The range for this VDRIVE pin is 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package and is specified over a −40°C to +85°C temperature range. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. AD7484 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description......................................................................... 12 Functional Block Diagram .............................................................. 1 Converter Operation.................................................................. 12 General Description ......................................................................... 1 Analog Input ............................................................................... 12 Revision History ............................................................................... 2 ADC Transfer Function ............................................................. 13 Specifications..................................................................................... 3 Power Saving ............................................................................... 13 Timing Characteristics ................................................................ 5 Offset/Overrange........................................................................ 14 Absolute Maximum Ratings............................................................ 6 Parallel Interface ......................................................................... 15 ESD Caution .................................................................................. 6 Board Layout and Grounding................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 19 Terminology .................................................................................... 11 REVISION HISTORY 12/09—Rev. B to Rev. C Changes to Table 1, Power Requirements Section ....................... 4 Changes to Ordering Guide .......................................................... 19 8/08—Rev. A. to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Table 3 ............................................................................ 6 Changes to Typical Performance Characteristics Section ........... 9 Changes to Figure 9 ........................................................................ 10 Changes to Circuit Description Section ...................................... 11 Changes to Terminology Section.................................................. 11 Changes to Analog Input Section ................................................. 12 Changes to Offset/Overrange Section ......................................... 14 Changes to Table 5, Table 6, Table 7, and Table 8 ....................... 15 Changes to Parallel Interface Section........................................... 15 Changes to Table 9 .......................................................................... 16 Changes to Board Layout and Grounding Section .................... 17 Changes to Ordering Guide .......................................................... 19 2/04—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Timing Characteristics Section ..................................5 Changes to Pin Function Descriptions Section .............................8 Changes to Figure 9 ........................................................................ 11 Changes to the Converter Operation Section............................. 13 Changes to the Offset/Overrange Section................................... 15 8/02—Revision 0: Initial Version Rev. C | Page 2 of 20 AD7484 SPECIFICATIONS AVDD/DVDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = external, fSAMPLE = 3 MSPS; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 1. Parameter DYNAMIC PERFORMANCE 1, 2 Signal-to-Noise + Distortion (SINAD) 3 Min Typ Max 76.5 78 79 77 Total Harmonic Distortion (THD)3 −90 −95 −92 −90 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second Order Terms Third Order Terms Aperture Delay Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 −96 −94 10 40 3.5 14 ±0.5 ±0.3 Gain Error3 ANALOG INPUT Input Voltage −200 +2.7 ±1 DC Leakage Current Input Capacitance 4 REFERENCE INPUT/OUTPUT Input Voltage, VREFIN Input DC Leakage Current, VREFIN Input Capacitance, VREFIN4 Input Current, VREFIN Output Voltage, VREFOUT Error @ 25°C, VREFOUT Error TMIN to TMAX, VREFOUT Output Impedance, VREFOUT ±1 ±0.75 ±6 0.036 ±6 0.036 ±2 35 +2.5 ±1 25 220 +2.5 ±50 ±100 1 Rev. C | Page 3 of 20 Unit Test Conditions/Comments dB dB dB dB dB dB dB dB fIN = 1 MHz fIN = 1 MHz fIN = 1 MHz, extended input fIN = 1 MHz, internal reference dB dB ns MHz MHz fIN1 = 95.053 kHz, fIN2 = 105.329 kHz Bits LSB LSB LSB %FSR LSB %FSR mV V µA µA pF V µA pF µA V mV mV Ω Internal reference @ 3 dB @ 0.1 dB Guaranteed no missed codes to 14 bits VIN from 0 V to 2.7 V VIN = −200 mV ± 1% for specified performance External reference AD7484 Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time (tACQ) Min Typ Unit 0.4 ±1 10 V V µA pF 0.4 ±10 10 V V µA pF 300 70 70 2.5 3 ns ns ns MSPS MSPS V V ± 5% 5.25 13 20 0.5 2 mA mA mA µA CS and RD = Logic 1 100 2.5 10 mW mW µW VDRIVE −1 0.7 × VDRIVE Test Conditions/Comments Straight (Natural) Binary Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) Nap Mode Standby Mode Power Dissipation Normal Mode (Operational) Nap Mode Standby Mode 5 Max 5 2.7 0.5 SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB. See the Typical Performance Characteristics section for analog input circuits used. 3 See the Terminology section. 4 Sample tested @ 25°C to ensure compliance. 5 Digital input levels at DGND or VDRIVE. 1 2 Rev. C | Page 4 of 20 Sine wave input Full-scale step input Parallel Mode 1 Parallel Mode 2 AD7484 TIMING CHARACTERISTICS AVDD/DVDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = external; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted. Table 2. Parameter1 DATA READ Conversion Time Quiet Time Before Conversion Start CONVST Pulse Width CONVST Falling Edge to BUSY Falling Edge CS Falling Edge to RD Falling Edge Data Access Time CONVST Falling Edge to New Data Valid BUSY Rising Edge to New Data Valid Bus Relinquish Time RD Rising Edge to CS Rising Edge CS Pulse Width RD Pulse Width DATA WRITE WRITE Pulse Width Data Setup Time Data Hold Time CS Falling Edge to WRITE Falling Edge WRITE Falling Edge to CS Rising Edge Symbol Min Typ Max Unit 300 tCONV tQUIET t1 t2 t3 t4 t5 t6 t7 t8 t14 t15 0 30 30 ns ns ns ns ns ns ns ns ns ns ns ns t9 t10 t11 t12 t13 5 2 6 5 0 ns ns ns ns ns 100 5 100 20 0 25 30 5 10 All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 1 Rev. C | Page 5 of 20 AD7484 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND VDRIVE to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND REFIN to AGND Input Current to Any Pin Except Supply Pins Operating Temperature Range Commercial Storage Temperature Range Junction Temperature θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 50°C/W 10°C/W 215°C 220°C 1 kV Rev. C | Page 6 of 20 AD7484 D11 D12 D13 CONVST D14 RESET MODE2 MODE1 CLIP AGND AVDD AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 CBIAS 2 AGND 3 AGND 4 AVDD 5 AGND 6 35 D9 34 D8 33 D7 32 VDRIVE 31 DGND AD7484 TOP VIEW (Not to Scale) VIN 7 REFOUT 36 D10 PIN 1 IDENTIFIER 30 DGND 8 29 DVDD 28 D6 REFIN 9 REFSEL 10 27 D5 AGND 11 26 D4 AGND 12 25 D3 02642-002 D2 D1 BUSY D0 RD WRITE CS NAP STBY AGND AVDD AGND 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 5, 13, 46 2 3, 4, 6, 11, 12, 14, 15, 47, 48 7 8 Mnemonic AVDD CBIAS AGND Description Positive Power Supply for Analog Circuitry. Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND. Power Supply Ground for Analog Circuitry. VIN REFOUT 9 REFIN 10 REFSEL 16 STBY 17 NAP 18 CS 19 20 RD WRITE 21 BUSY 22 to 28, 33 to 39 29 30, 31 32 D0 to D13 Analog Input. Single ended analog input channel. Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor must be placed between this pin and AGND. Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin. Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND. Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving section for further details. Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power Saving section for further details. Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus is brought out of three-state and the current contents of the output register driven onto the data lines following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to the offset register. CS can be hardwired permanently low. Read Logic Input. Used in conjunction with CS to access the conversion result. Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this pulse that latches the word into the offset register. Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY signal returns high when the conversion result has been latched into the output register. In Parallel Mode 2, the BUSY signal returns high as soon as the conversion has been completed, but the conversion result does not get latched into the output register until the falling edge of the next CONVST pulse. Data I/O Bits. D13 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating voltage level for these pins is determined by the VDRIVE input. Positive Power Supply for Digital Circuitry. Ground Reference for Digital Circuitry. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of the device operates. DVDD DGND VDRIVE Rev. C | Page 7 of 20 AD7484 Pin No. 40 Mnemonic D14 41 CONVST 42 RESET 43 44 45 MODE2 MODE1 CLIP Description Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to DGND via a 100 kΩ resistor. Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The input trackand-hold amplifier goes from track mode to hold mode, and the conversion process commences. Reset Logic Input. An active low reset pulse must be applied to this pin after power-up to ensure correct operation. A falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. The contents of the offset register will also be cleared on this edge. Holding this pin low keeps the part in a reset state. Operating Mode Logic Input. See Table 8 for details. Operating Mode Logic Input. See Table 8 for details. Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that is greater than positive full scale or less than negative full scale will be clipped to all 1s or all 0s, respectively. Further details are given in the Offset/Overrange section. Rev. C | Page 8 of 20 AD7484 TYPICAL PERFORMANCE CHARACTERISTICS 0 1.0 fIN = 10.7kHz SNR = 78.9dB SNR + D = 78.8dB THD = –93.9dB –20 0.8 0.6 0.4 –60 0.2 INL (LSB) (dB) –40 –80 0 –0.2 –0.4 –100 –0.6 –120 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) –1.0 02642-003 0 0 4096 Figure 3. 64 k FFT Plot with 10 kHz Input Tone 0 16384 Figure 6. Typical INL 80 fIN = 1.013MHz SNR = 77.7dB SNR + D = 77.6dB THD = –95.5dB –20 12288 8192 ADC (Code) 02642-006 –0.8 –140 –40 SINAD (dB) (dB) 75 –60 –80 70 –100 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz) 65 02642-004 –140 10 1000 100 10000 INPUT FREQUENCY (kHz) 02642-007 –120 Figure 7. SINAD vs. Input Tone (AD8021 Input Circuit) Figure 4. 64 k FFT Plot with 1 MHz Input Tone 1.0 –40 0.8 200Ω 100Ω 0.6 –50 –60 THD (dB) 0.2 0 51Ω –70 10Ω –0.2 –80 –0.4 0Ω –0.6 –90 –1.0 0 4096 8192 ADC (Code) 12288 16384 Figure 5. Typical DNL –100 100 1000 10000 INPUT FREQUENCY (kHz) Figure 8. THD vs. Input Tone for Different Input Resistances Rev. C | Page 9 of 20 02642-008 –0.8 02642-005 DNL (LSB) 0.4 AD7484 0 0.0004 100mV p-p SINE WAVE ON SUPPLY PINS –10 0 –0.0004 REFOUT (V) –30 –40 –50 –0.0008 –0.0012 –60 –80 10 100 FREQUENCY (kHz) 1000 –0.0020 –55 –25 5 35 65 TEMPERATURE (°C) Figure 10. Reference Error Figure 9. PSRR Without Decoupling Rev. C | Page 10 of 20 95 125 02642-010 –0.0016 –70 02642-009 PSRR (dB) –20 AD7484 TERMINOLOGY Integral Nonlinearity The integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Total Harmonic Distortion (THD) The THD is the ratio of the rms sum of the harmonics to the fundamental. It is defined as Differential Nonlinearity The differential nonlinearity is the difference between the measured and ideal 1 LSB change between any two adjacent codes in the ADC. where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error The offset error is the deviation of the first code transition (00…000) to (00…001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The gain error is the deviation of the last code transition (111…110) to (111…111) from the ideal, that is, VREF − 1.5 LSB, after the offset error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track-and-hold returns to track mode). Signal-to-Noise + Distortion (SINAD) Ratio The SINAD ratio is the measured ratio of signal-to-noise + distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise + Distortion = (6.02N + 1.76)dB Therefore, this is 86.04 dB for a 14-bit converter. THD (dB ) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. The value of this specification is usually determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa − fb), whereas the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7484 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, whereas the third order terms are usually at a frequency close to the input frequencies. As a result, the second order and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Rev. C | Page 11 of 20 AD7484 CIRCUIT DESCRIPTION CONVERTER OPERATION At the end of conversion, the track-and-hold returns to track mode and the acquisition time begins. The track-and-hold acquisition time is 70 ns. Figure 13 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. The AD7484 is a 14-bit algorithmic successive approximation ADC based around a capacitive DAC. It provides the user with track-and-hold, reference, an ADC, and versatile interface logic functions on a single chip. The normal analog input signal range that the AD7484 can convert is 0 V to 2.5 V. By using the offset and overrange features on the ADC, the AD7484 can convert analog input signals from −200 mV to +2.7 V while operating from a single 5 V supply. The part requires a 2.5 V reference, which can be provided from the internal reference or an external reference source. Figure 11 shows a simplified schematic of the ADC. The control logic, SAR, and capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. CAPACITIVE DAC A VIN + SW1 CONTROL LOGIC B – SW2 AGND COMPARATOR Figure 13. ADC Acquisition Phase CAPACITIVE DAC ANALOG INPUT +VS VIN SWITCHES SAR AC SIGNAL 1kΩ BIAS VOLTAGE 1kΩ 8 100Ω 3 + 2 – 7 6 AD829 5 1 OUTPUT DATA 14-BIT PARALLEL 02642-011 CONTROL LOGIC –VS 220pF 02642-013 CONTROL INPUTS VIN 4 150Ω Figure 14. Analog Input Circuit Used for 10 kHz Input Tone Figure 11. Simplified Block Diagram of the AD7484 +VS Conversion is initiated on the AD7484 by pulsing the CONVST input. On the falling edge of CONVST, the track-and-hold goes from track mode to hold mode and the conversion sequence is started. Conversion time for the part is 300 ns. Figure 12 shows the ADC during conversion. When conversion starts, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The ADC then runs through its successiveapproximation routine and brings the comparator back into a balanced condition. When the comparator is rebalanced, the conversion result is available in the SAR register. AC SIGNAL 50Ω BIAS VOLTAGE 220Ω 8 2 + 3 – 7 6 AD8021 VIN 4 5 1 10pF 220Ω 10pF –VS 02642-012 VREF 02642-015 COMPARATOR Figure 15. Analog Input Circuit Used for 1 MHz Input Tone CAPACITIVE DAC A VIN + SW1 CONTROL LOGIC B SW2 – 02642-014 COMPARATOR AGND Figure 12. ADC Conversion Phase Figure 14 shows the analog input circuit used to obtain the data for the fast fourier transfer (FFT) plot shown in Figure 3. The circuit uses the AD829 op amp as the input buffer. A bipolar analog signal is applied and biased up with a stable, low noise dc voltage connected to the labeled terminal, as shown in Figure 11. A 220 pF compensation capacitor is connected between Pin 5 of the AD829 and the analog ground plane. The AD829 is supplied with +12 V and −12 V supplies. The supply pins are decoupled as close to the device as possible with both a 0.1 µF and a 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two caps to the device. More information on the AD829 is available at www.analog.com. Rev. C | Page 12 of 20 AD7484 The output coding of the AD7484 is straight binary. The designed code transitions occur midway between the successive integer LSB values, that is, 1/2 LSB, 3/2 LSB, and so on. The LSB size is VREF/16,384. The nominal transfer characteristic for the AD7484 is shown in Figure 16. This transfer characteristic may be shifted as detailed in the Offset/Overrange section. Therefore, the power dissipated during each cycle is 27 mW + 42 mW = 69 mW Figure 17 shows the AD7484 conversion sequence operating in normal mode. 1µs CONVST BUSY 300ns 700ns 111...000 1LSB = VREF /16384 000...010 000...001 000...000 0.5LSB +VREF – 1.5LSB ANALOG INPUT In nap mode, almost all of the internal circuitry is powered down. In this mode, the power dissipation is reduced to 2.5 mW. When using an external reference, there must be a minimum of 300 ns from exiting nap mode to initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track-and-hold to properly acquire the analog input signal. The internal reference cannot be used in conjunction with the nap mode. If the AD7484 is put into nap mode after each conversion, the average power dissipation is reduced, but the throughput rate is limited by the power-up time. Using the AD7484 with a throughput rate of 500 kSPS while placing the part in nap mode after each conversion results in average power dissipation as follows: The power-up phase contributes 02642-016 ADC CODE 111...111 111...110 0V (700 ns/1 μs) × (5 V × 12 mA) = 42 mW Figure 17. Normal Mode Power Dissipation ADC TRANSFER FUNCTION 011...111 For the remaining 700 ns of the cycle, the AD7484 dissipates 42 mW of power. 02642-017 For higher input bandwidth applications, the AD8021 op amp (also available as a dual AD8022 op amp) is the recommended choice to drive the AD7484. Figure 15 shows the analog input circuit used to obtain the data for the FFT plot shown in Figure 4. A bipolar analog signal is applied to the terminal and biased up with a stable, low noise dc voltage connected, as shown in Figure 12. A 10 pF compensation capacitor is connected between Pin 5 of the AD8021 and the negative supply. The AD8021 is supplied with +12 V and −12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and a 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two caps to the device. The AD8021 logic reference pin is tied to analog ground, and the DISABLE pin is tied to the positive supply. Detailed information on the AD8021 is available at www.analog.com. (300 ns/2 μs) × (5 V × 12 mA) = 9 mW The conversion phase contributes Figure 16. AD7484 Transfer Characteristic (300 ns/2 μs) × (5 V × 18 mA) = 13.5 mW POWER SAVING The AD7484 uses advanced design techniques to achieve very low power dissipation at high throughput rates. In addition, the AD7484 features two power saving modes, nap and standby. These modes are selected by bringing either the NAP pin or the STBY pin to a logic high, respectively. While in nap mode for the rest of the cycle, the AD7484 dissipates only 1.75 mW of power. (1400 ns/2 μs) × (5 V × 0.5 mA) = 1.75 mW Therefore, the power dissipated during each cycle is When operating the AD7484 in normal fully powered mode, the current consumption is 18 mA during conversion and the quiescent current is 12 mA. Operating at a throughput rate of 1 MSPS, the conversion time of 300 ns contributes 27 mW to the overall power dissipation. (300 ns/1 μs) × (5 V × 18 mA) = 27 mW Rev. C | Page 13 of 20 9 mW + 13.5 mW + 1.75 mW = 24.25 mW AD7484 reference source is used and kept powered up while the AD7484 is in standby mode, the power-up time required is reduced to 80 µs. Figure 18 shows the AD7484 conversion sequence when the part is put into nap mode after each conversion. 600ns OFFSET/OVERRANGE 1400ns NAP 300ns CONVST 02642-018 BUSY 2µs Figure 18. Nap Mode Power Dissipation Figure 19 and Figure 20 show a typical graphical representation of power vs. throughput for the AD7484 when in normal mode and nap mode, respectively. 90 85 POWER (mW) 80 75 The AD7484 provides a ±8% overrange capability as well as a programmable offset register. The overrange capability is achieved by the use of a 15th bit (D14) and the CLIP input. If the CLIP input is at logic high and the contents of the offset register are 0, then the AD7484 operates as a normal 14-bit ADC. If the input voltage is greater than the full-scale voltage, the data output from the ADC is all 1s. Similarly, if the input voltage is lower than the zero-scale voltage, the data output from the ADC is all 0s. In this case, D14 acts as an overrange indicator. It is set to 1 if the analog input voltage is outside the nominal 0 V to 2.5 V range. The default contents of the offset register are 0. If the offset register contains any value other than 0, the contents of the register are added to the SAR result at the end of conversion. This has the effect of shifting the transfer function of the ADC as shown in Figure 21 and Figure 22. However, it should be noted that with the CLIP input set to logic high, the maximum and minimum codes that the AD7484 can output are 0x3FFF and 0x0000, respectively. Further details are given in Table 5 and Table 6. Figure 21 shows the effect of writing a positive value to the offset register. For example, if the contents of the offset register contained the value 1024, then the value of the analog input voltage for which the ADC transitions from reading all 0s to 000…001 (the bottom reference point) is 70 60 0 2000 1000 1500 THROUGHPUT (kSPS) 500 2500 3000 02642-019 65 Figure 19. Normal Mode, Power vs. Throughput 90 0.5 LSB − (1024 LSB) = −156.326 mV The analog input voltage for which the ADC reads full-scale (0x3FFF) in this example is 2.5 – 1.5 LSB – (1024 LSB) = 2.34352 V 80 111...111 111...110 50 40 111...000 1LSB = VREF /16384 011...111 30 20 ANALOG INPUT 0V 10 Figure 21. Transfer Characteristic with Positive Offset 0 250 500 750 1000 1250 THROUGHPUT (kSPS) 1500 1750 2000 02642-020 0 +VREF – 1.5LSB –OFFSET 000...010 000...001 000...000 02642-021 ADC CODE POWER (mW) 60 0.5LSB –OFFSET 70 Figure 20. Nap Mode, Power vs. Throughput In standby mode, all internal circuitry is powered down and the power consumption of the AD7484 is reduced to 10 µW. The power-up time necessary before a conversion can be initiated is longer because more of the internal circuitry has been powered down. In using the internal reference of the AD7484, the ADC must be brought out of standby mode 500 ms before a conversion is initiated. Initiating a conversion before the required power-up time has elapsed results in incorrect conversion data. If an external The effect of writing a negative value to the offset register is shown in Figure 22. If a value of −512 is written to the offset register, the bottom end reference point occurs at 0.5 LSB – (−512 LSB) = 78.20 mW Following this, the analog input voltage needed to produce a full-scale (0x3FFF) result from the ADC is Rev. C | Page 14 of 20 2.5 V – 1.5 LSB – (−512 LSB) = 2.5779 V AD7484 range on the positive side and the output code is a 15-bit straight binary code (see Table 7). ADC CODE 111...111 111...110 Table 7. DB14, DB13 Decoding, CLIP = 0 1LSB = VREF /16384 111...000 DB14 0 0 1 1 011...111 0V +VREF – 1.5LSB 0.5LSB –OFFSET –OFFSET ANALOG INPUT 02642-022 000...010 000...001 000...000 Figure 22. Transfer Characteristic with Negative Offset Table 5 shows the expected ADC result for a given analog input voltage with different offset values and with CLIP tied to logic high. The combined advantages of the offset and overrange features of the AD7484 are shown in Table 6. Table 6 shows the same range of analog input and offset values as Table 5 but with the clipping feature disabled. ADC DATA, D[0:13] −512 0 +1024 0 0 0 0 0 0 0 0 1024 0 512 1536 14,846 15,358 16,383 15,871 16,383 16,383 16,383 16,383 16,383 16,383 16,383 16,383 D14 111 110 100 000 000 001 011 111 Table 6. Clipping Disabled (CLIP = 0) Offset VIN −200 mV −156.3 mV 0V +78.2 mV +2.3434 V +2.5 V +2.5782 V +2.7 V −512 −1823 −1536 −512 0 14,846 15,872 16,384 17,183 Output Coding Straight binary–inside nominal range Straight binary–inside nominal range Straight binary–outside nominal range Twos complement–outside nominal range Values from −1310 to +1310 can be written to the offset register. These values correspond to an offset of ±200 mV. A write to the offset register is performed by writing a 13-bit word to the part, as detailed in the Parallel Interface section. The 12 LSBs of the 15-bit word contain the offset value, whereas the 3 MSBs must be set to 0. Failure to write 0s to the 3 MSBs may result in the incorrect operation of the device. PARALLEL INTERFACE The AD7484 features two parallel interfacing modes. These modes are selected by the mode pins (see Table 8). Table 5. Clipping Enabled (CLIP = 1) Offset VIN −200 mV −156.3 mV 0V +78.2 mV +2.3434 V +2.5 V +2.5782 V +2.7 V DB13 0 1 0 1 ADC DATA, D[0:14] 0 +1024 −1311 −287 −1024 0 0 1024 512 1536 15,358 16,382 16,384 17,408 16,896 17,920 17,695 18,719 If the CLIP input is at logic low, the overrange indicator is disabled and the AD7484 can achieve output codes outside the nominal 14-bit range of 0 to 16,383 (see Table 6). D14 acts as an indicator that the ADC is outside this nominal range. If the ADC is outside this nominal range on the negative side, the ADC outputs a twos complement code and if the ADC is outside the range on the positive side, the ADC outputs a straight binary code as normal. If D14 is Logic 1, D13 indicates if the ADC is out of range on the positive or negative side. If DB13 is Logic 1, the ADC is outside the nominal range on the negative side and the output code is a 15-bit twos complement number (a negative number). If D13 is Logic 0, the ADC is outside the nominal Table 8. Operating Modes Operating Mode Do Not Use Parallel Mode 1 Parallel Mode 2 Do Not Use Mode 2 0 0 1 1 Mode 1 0 1 0 1 In Parallel Mode 1, the data in the output register is updated on the rising edge of BUSY at the end of a conversion and is available for reading almost immediately afterwards. Using this mode, throughput rates of up to 2.5 MSPS can be achieved. This mode is to be used if the conversion data is required immediately after the conversion is completed. An example where this may be of use is if the AD7484 is operating at much lower throughput rates in conjunction with the nap mode (for power saving reasons), and the input signal is being compared with set limits within the DSP or other controller. If the limits are exceeded, the ADC is brought immediately into full power operation and commences sampling at full speed. Figure 31 shows a timing diagram for the AD7484 operating in Parallel Mode 1 with both CS and RD tied low. In Parallel Mode 2, the data in the output register is not updated until the next falling edge of CONVST. This mode can be used where a single sample delay is not vital to the system operation, and conversion speeds of greater than 2.5 MSPS are desired. For example, this may occur in a system where a large amount of samples are taken at high speed before an FFT is performed for frequency analysis of the input signal. Figure 32 shows a timing diagram for the AD7484 operating in Parallel Mode 2 with both CS and RD tied low. Rev. C | Page 15 of 20 AD7484 Data must not be read from the AD7484 while a conversion is taking place. For this reason, if operating the AD7484 at throughput speeds greater than 2.5 MSPS, it is necessary to tie both the CS pin and RD pin on the AD7484 low and use a buffer on the data lines. This situation may also arise in the case where a read operation cannot be completed in the time after the end of one conversion and the start of the quiet period before the next conversion. The maximum slew rate at the input of the ADC must be limited to 500 V/µs while BUSY is low to avoid corrupting the ongoing conversion. In any multiplexed application where the channel is switched during conversion, this is to happen as soon as possible after the BUSY falling edge. Reading Data from the AD7484 Data is read from the part via a 15-bit parallel data bus with the standard CS and RD signals. The CS and RD signals are internally gated to enable the conversion result onto the data bus. The data lines D0 to D14 leave their high impedance state when both CS and RD are logic low. Therefore, CS can be permanently tied logic low if required, and the RD signal used to access the conversion result. Figure 29 shows a timing specification called tQUIET. This is the amount of time that must be left after any data bus activity before the next conversion is initiated. Writing to the AD7484 The AD7484 features a user accessible offset register. This allows the bottom of the transfer function to be shifted by ±200 mV. This feature is explained in more detail in the Offset/Overrange section. To write to the offset register, a 15-bit word is written to the AD7484 with the 12 LSBs containing the offset value in twos complement format. The 3 MSBs must be set to 0. The offset value must be within the range −1310 to +1310, corresponding to an offset from −200 mV to +200 mV. The value written to the offset register is stored and used until power is removed from the device, or the device is reset. The value stored may be updated at any time between conversions by another write to the device. Table 9 shows some examples of offset register values and their effective offset voltage. Figure 30 shows a timing diagram for writing to the AD7484. Driving the CONVST Pin To achieve the specified performance from the AD7484, the CONVST pin must be driven from a low jitter source. Because the falling edge on the CONVST pin determines the sampling instant, any jitter that may exist on this edge appears as noise when the analog input signal contains high frequency components. The relationship between the analog input frequency (fIN), timing jitter (tj), and resulting SNR is given by SNR JITTER (dB ) = 10 log ) 2 Typical Connection Figure 23 shows a typical connection diagram for the AD7484 operating in Parallel Mode 1. Conversion is initiated by a falling edge on CONVST. When CONVST goes low, the BUSY signal goes low, and at the end of conversion, the rising edge of BUSY is used to activate an interrupt service routine. The CS and RD lines are then activated to read the 14 data bits (15 bits if using the overrange feature). In Figure 23, the VDRIVE pin is tied to DVDD, which results in logic output levels being either 0 V or DVDD. The voltage applied to VDRIVE controls the voltage value of the output logic signals. For example, if DVDD is supplied by a 5 V supply and VDRIVE is supplied by a 3 V supply, the logic output levels are either 0 V or 3 V. This feature allows the AD7484 to interface to 3 V devices while still enabling the ADC to process signals at a 5 V supply. DIGITAL SUPPLY 4.75V TO 5.25V ANALOG SUPPLY 4.75V TO 5.25V + 10µF + 1nF 0.1µF 0.1µF 47µF 0.1µF VDRIVE DVDD AVDD ADM809 RESET MODE1 MODE2 WRITE CLIP NAP STBY CBIAS 1nF REFSEL AD780 2.5V REFERENCE REFIN 0.47µF AD7484 PARALLEL INTERFACE D0 TO D13 REFOUT 0.47µF CS CONVST RD BUSY VIN 0V TO 2.5V Figure 23. Typical Connection Diagram Rev. C | Page 16 of 20 02642-023 Offset (mV) −200 −78.12 +39.06 +200 MICROCONTROLLER/ MICROPROCESSOR D14 to D12 000 000 000 000 D11 to D0 (Twos Complement) 1010 1110 0010 1110 0000 0000 0001 0000 0000 0101 0001 1110 ×t j IN For example, if the desired SNR due to jitter is 100 dB with a maximum full-scale analog input frequency of 1.5 MHz, ignoring all other noise sources, the result is an allowable jitter on the CONVST falling edge of 1.06 ps. For a 14-bit converter (ideal SNR = 86.04 dB), the allowable jitter is greater than 1.06 ps, but due consider-ation must be given to the design of the CONVST circuitry to achieve 14-bit performance with large analog input frequencies. Table 9. Offset Register Examples Code (Decimal) −1310 −512 +256 +1310 (2π × f 1 AD7484 BOARD LAYOUT AND GROUNDING For optimum performance from the AD7484, it is recommended that a PCB with a minimum of three layers be used. One of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. The board should be designed in such a way that the analog and digital circuitry is separated and confined to certain areas of the board. This practice, along with not running digital and analog lines close together, helps to avoid coupling digital noise onto analog lines. Figure 24 to Figure 28 show a sample layout of the board area immediately surrounding the AD7484. Pin 1 is the bottom left corner of the device. The black area in each figure indicates the ground plane present on the middle layer. Figure 24 shows the top layer where the AD7484 is mounted with vias to the bottom routing layer highlighted. Figure 25 shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. Figure 26 shows the top and bottom routing layers overlaid. Figure 27 shows the bottom layer where the power routing is with the same vias highlighted. Figure 28 shows the silkscreen overlaid on the solder pads for the decoupling components, which are C1 to C6: 100 nF, C7 to C8: 470 nF, C9: 1 nF, and L1 to L4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2). 02642-024 02642-025 The power supply lines to the AD7484 are to be approximately 3 mm wide to provide low impedance paths and reduce the effects of glitches on the power supply lines. It is vital that good decoupling also be present. A combination of ferrites and decoupling capacitors should be used, as shown in Figure 23.The decoupling capacitors are to be as close to the supply pins as possible. This is made easier by the use of multilayer boards. The signal traces from the AD7484 pins can be run on the top layer, while the decoupling capacitors and ferrites can be mounted on the bottom layer where the power traces exist. The ground plane between the top and bottom planes provides excellent shielding. Figure 27. Bottom Layer Routing 02642-026 02642-027 Figure 24. Top Layer Routing Figure 28. Silkscreen and Bottom Layer Routing 02642-028 Figure 25. Bottom Layer Silkscreen Figure 26. Top and Bottom Routing Layers Rev. C | Page 17 of 20 AD7484 tACQ tCONV tQUIET t1 CONVST t2 BUSY t14 CS t8 t15 t3 RD t4 t7 02642-029 D[14:0] DATA VALID Figure 29. Parallel Mode READ Cycle CONVST t13 t12 CS RD t9 WRITE D[14:0] t11 02642-030 t10 OFFSET DATA Figure 30. Parallel Mode WRITE Cycle tCONV t1 CONVST N N+1 t2 t6 DATA N – 1 D[14:0] DATA N 02642-031 BUSY Figure 31. Parallel Mode 1 READ Cycle tCONV t1 CONVST N N+1 t2 t5 D[14:0] DATA N – 1 Figure 32. Parallel Mode 2 READ Cycle Rev. C | Page 18 of 20 DATA N 02642-032 BUSY AD7484 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 24 0.27 0.22 0.17 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 Figure 33. 48-Lead Plastic Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7484BSTZ EVAL-AD7484CBZ EVAL-CONTROLBRD2Z 1 2 3 Temperature Range −40°C to +85°C Package Description 48-Lead Plastic Quad Flatpack Package (LQFP) Evaluation Board 2 Controller Board 3 Package Option ST-48 Z = RoHS Compliant Part. This can be used as a standalone evaluation board or in conjunction with the controller board for evaluation/demonstration purposes. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. C | Page 19 of 20 AD7484 NOTES ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02642-0-12/09(C) Rev. C | Page 20 of 20