ETC A80960MC-25

80960MC
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
AND MEMORY MANAGEMENT UNIT
Commercial
■ High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
■ On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point
Standard
— Full Transcendental Support
— Four 80-Bit Registers
— 13.6 Million Whetstones/s
(Single Precision) at 25 MHz
■ 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
— Register Scoreboarding
FOUR
80-BIT FP
REGISTERS
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
■ On-Chip Memory Management Unit
■
■
■
■
— 4 Gbyte Virtual Address Space per
Task
— 4 Kbyte Pages with Supervisor/User
Protection
Built-in Interrupt Controller
— 32 Priority Levels
— 248 Vectors
— Supports M8259A
— 3.4 µs Latency @ 25 MHz
Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
Multitasking and Multiprocessor Support
— Automatic Task dispatching
— Prioritized Task Queues
Advanced Package Technology
— 132-Lead Ceramic Pin Grid Array
32-BIT
INSTRUCTION
EXECUTION
UNIT
MMU
80-BIT
FPU
32-BIT
BUS CONTROL
LOGIC
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICROINSTRUCTION
SEQUENCER
MICROINSTRUCTION
ROM
32-BIT
BURST
BUS
Figure 1. The 80960MC Processor’s Highly Parallel Architecture
© INTEL CORPORATION, 1997
September, 1997
Order Number: 273123-001
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estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
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Copyright © Intel Corporation 1997
80960MC
1.0 THE i960® MC PROCESSOR ................................................................................................................. .. 1
1.1 Key Performance Features ................................................................................................................. 2
1.1.1 Memory Space And Addressing Modes ................................................................................... 4
1.1.2 Data Types ............................................................................................................. .................. 4
1.1.3 Large Register Set ..................................................................................................... .............. 4
1.1.4 Multiple Register Sets .............................................................................................................. 5
1.1.5 Instruction Cache ..................................................................................................................... 5
1.1.6 Register Scoreboarding ................................................................................................. .......... 5
1.1.7 Memory Management and Protection ...................................................................................... 6
1.1.8 Floating-Point Arithmetic .............................................................................................. ............ 6
1.1.9 Multitasking Support ................................................................................................................ 7
1.1.10 Synchronization and Communication .................................................................................... 7
1.1.11 High Bandwidth Local Bus ..................................................................................................... 7
1.1.12 Multiple Processor Support .................................................................................................... 7
1.1.13 Interrupt Handling .................................................................................................... .............. 8
1.1.14 Debug Features ..................................................................................................................... 8
1.1.15 Fault Detection ....................................................................................................................... 8
1.1.16 Inter-Agent Communications (IAC) ........................................................................................ 9
1.1.17 Built-in Testability ................................................................................................................... 9
1.1.18 Compatibility with 80960K-Series ...................................................................................... .... 9
1.1.19 CHMOS .................................................................................................................................. 9
2.0 ELECTRICAL SPECIFICATIONS ................................................................................................ ........... 13
2.1 Power and Grounding ....................................................................................................................... 13
2.2 Power Decoupling Recommendations ......................................................................................... .... 13
2.3 Connection Recommendations ........................................................................................................ 13
2.4 Characteristic Curves ....................................................................................................................... 13
2.5 Test Load Circuit .............................................................................................................................. 16
2.7 DC Characteristics ............................................................................................................................ 17
2.6 Absolute Maximum Ratings .............................................................................................................. 17
2.8 AC Specifications ............................................................................................................................. 18
2.9 Design Considerations ..................................................................................................................... 22
3.0 MECHANICAL DATA .............................................................................................................................. 22
3.1 Packaging ......................................................................................................................................... 22
3.1.1 Pin Assignment ...................................................................................................................... 22
3.2 Pinout ............................................................................................................................................... 26
3.3 Package Thermal Specification ........................................................................................................ 28
4.0 WAVEFORMS ......................................................................................................................................... 30
5.0 REVISION HISTORY ............................................................................................................................... 35
iii
80960MC
FIGURES
Figure 1.
80960MC Programming Environment ........................................................................................ 1
Figure 2.
Instruction Formats .................................................................................................................... 4
Figure 3.
Multiple Register Sets Are Stored On-Chip ............................................................................... 6
Figure 4.
Connection Recommendations for Low Current Drive Network .............................................. 13
Figure 5.
Connection Recommendations for High Current Drive Network .............................................. 13
Figure 6.
Typical Supply Current vs. Case Temperature ........................................................................ 14
Figure 7.
Typical Current vs. Frequency (Room Temp) .......................................................................... 14
Figure 8.
Typical Current vs. Frequency (Hot Temp) .............................................................................. 15
Figure 9.
Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 15
Figure 10.
Capacitive Derating Curve ....................................................................................................... 15
Figure 11.
Test Load Circuit for Three-State Output Pins ......................................................................... 16
Figure 12.
Test Load Circuit for Open-Drain Output Pins ......................................................................... 16
Figure 13.
Drive Levels and Timing Relationships for 80960MC Signals ................................................. 18
Figure 14.
Timing Relationship of L-Bus Signals ................................................................................ ...... 19
Figure 15.
System and Processor Clock Relationship ............................................................................. . 19
Figure 16.
Processor Clock Pulse (CLK2) ................................................................................................ 21
Figure 17.
RESET Signal Timing .............................................................................................................. 21
Figure 18.
HOLD Timing ........................................................................................................................... 22
Figure 19.
132-Lead Pin-Grid Array (PGA) Package ................................................................................ 23
Figure 20.
80960MC PGA Pinout—View from Bottom (Pins Facing Up) .................................................. 24
Figure 21.
80960MC PGA Pinout—View from Top (Pins Facing Down) .................................................. 25
Figure 22.
25 MHz Maximum Allowable Ambient Temperature ................................................................ 29
Figure 23.
Non-Burst Read and Write Transactions Without Wait States ................................................. 30
Figure 24.
Burst Read and Write Transaction Without Wait States .......................................................... 31
Figure 25.
Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 32
Figure 26.
Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from
Quad Word Boundary (1, 0, 0, 0 Wait States) ......................................................................... 33
Figure 27.
Interrupt Acknowledge Transaction ......................................................................................... 34
Figure 28.
Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) ..... 35
TABLES
Table 1.
80960MC Instruction Set ........................................................................................................... 3
Table 2.
Memory Addressing Modes ....................................................................................................... 4
Table 3.
Sample Floating-Point Execution Times (µs) at 25 MHz ........................................................... 7
Table 4.
80960MC Pin Description: L-Bus Signals .................................................................................. 9
Table 5.
80960MC Pin Description: Support Signals ............................................................................. 11
Table 6.
DC Characteristics ................................................................................................................... 17
Table 7.
80960MC AC Characteristics (25 MHz) ...................................................................................20
Table 8.
80960MC PGA Pinout — In Pin Order .....................................................................................26
Table 9.
80960MC PGA Pinout — In Signal Order ................................................................................ 27
Table 10.
80960MC PGA Package Thermal Characteristics ................................................................... 28
iv
80960MC
1.0
THE i960® MC PROCESSOR
The 80960MC, a member of Intel’s i960® 32-bit
processor family, is ideally suited for embedded
applications. It includes a 512-byte instruction cache
and a built-in interrupt controller. The 80960MC has
a large register set, multiple parallel execution units
and a high-bandwidth burst bus. Using advanced
RISC technology, this processor is capable of
execution rates in excess of 9.4 million instructions
per second*. The 80960MC is well-suited for a wide
range of applications including non-impact printers,
I/O control and specialty instrumentation. The
embedded market includes applications as diverse
as
industrial
automation,
avionics,
image
processing, graphics and networking. These types of
applications require high integration, low power
consumption, quick interrupt response times and
* Relative to Digital Equipment Corporation’s VAX-11/780*
at 1 MIPS
high performance. Since time to market is critical,
embedded processors must be easy to use in both
hardware and software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
The 80960MC includes an integrated Floating Point
Unit (FPU), a Memory Management Unit (MMU),
multitasking support, and multiprocessor support.
Two commercial members of the i960® family
provide similar features: the 80960KB processor with
integrated FPU and the 80960KA without floatingpoint.
0000 0000H
FFFF FFFFH
ADDRESS SPACE
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FETCH
LOAD
STORE
INSTRUCTION CACHE
INSTRUCTION
STREAM
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
g0
g15
SIXTEEN 32-BIT GLOBAL REGISTERS
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0
r15
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 1. 80960MC Programming Environment
1
80960MC
1.1
Key Performance Features
6.
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960MC’s exceptional
performance:
1.
2.
3.
4.
5.
2
Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the 80960MC provides thirty-two 32-bit
registers. (See Figure 2.)
Fast Instruction Execution. Simple functions
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instructions are executed as quickly as possible. The
most frequently executed instructions such as
register-register moves, add/subtract, logical
operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
Load/Store Architecture. One way to improve
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other processors based on RISC technology, the 80960MC
has a Load/Store architecture. As such, only
the LOAD and STORE instructions reference
memory; all other instructions operate on registers. This type of architecture simplifies instruction decoding and is used in combination with
other techniques to increase parallelism.
Simple Instruction Formats. All instructions
in the 80960MC are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
alignment stage in the pipeline. To simplify the
instruction decoder, there are only five instruction formats; each instruction uses only one
format. (See Figure 3.)
Overlapped Instruction Execution. Load
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions can overlap the load. The
80960MC manages this process transparently
to software through the use of a register scoreboard. Conditional instructions also make use
of a scoreboard so that subsequent unrelated
instructions may be executed while the conditional instruction is pending.
7.
8.
Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value
is sent immediately to its destination register.
Yet at the same time, the value is put on a
bypass path to the ALU, thereby saving the
time that otherwise would be required to
retrieve the value for the next operation.
Bandwidth Optimizations. The 80960MC
gets optimal use of its memory bus bandwidth
because the bus is tuned for use with the onchip instruction cache: instruction cache line
size matches the maximum burst size for
instruction fetches. The 80960MC automatically fetches four words in a burst and stores
them directly in the cache. Due to the size of
the cache and the fact that it is continually filled
in anticipation of needed instructions in the
program flow, the 80960MC is relatively insensitive to memory wait states. The benefit is that
the 80960MC delivers outstanding performance even with a low cost memory system.
Cache Bypass. When a cache miss occurs,
the processor fetches the needed instruction
then sends it on to the instruction decoder at
the same time it updates the cache. Thus, no
extra time is spent to load and read the cache.
80960MC
Table 1. 80960MC Instruction Set
Data Movement
Load
Store
Move
Load Address
Load Physical Address
Comparison
Process Management
Floating Point
Schedule Process
Saves Process
Resume Process
Load Process Time
Modify Process Controls
Wait
Conditional Wait
Signal
Receive
Conditional Receive
Send
Send Service
Atomic Add
Atomic Modify
Add
Subtract
Multiply
Divide
Remainder
Scale
Round
Square Root
Sine
Cosine
Tangent
Arctangent
Log
Log Binary
Log Natural
Exponent
Classify
Copy Real Extended
Compare
Branch
Compare
Unconditional Branch
Conditional Compare
Conditional Branch
Compare and Increment Compare and Branch
Compare and Decrement
Conversion
Convert Real to Integer
Convert Integer to Real
Fault
Conditional Fault
Synchronize Faults
3
Decimal
Move
Add with Carry
Subtract with Carry
Debug
Modify Trace Controls
Mark
Force Mark
Bit and Bit Field
Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modify
Call/Return
Call
Call Extended
Call System
Return
Branch and Link
Miscellaneous
Flush Local Registers
Inspect Access
Modify Arithmetic
Controls
Test Condition Code
Logical
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Rotate
String
Move String
Move Quick String
Fill String
Compare String
Scan Byte for Equal
Arithmetic
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
80960MC
Control
Opcode
Displacement
Compare and
Branch
Opcode
Reg/Lit
Reg
Register to
Register
Opcode
Reg
Reg/Lit
Memory AccessShort
Opcode
Reg
Base
Memory AccessLong
Opcode
Reg
Base
M
Displacement
Modes
M
Ext’d Op
X
Mode
Reg/Lit
Offset
Scale
xx
Offset
Displacement
Figure 2. Instruction Formats
1.1.1
Memory Space And Addressing Modes
1.1.2
Data Types
The 80960MC allows each task (process) to address
a logical memory space of up to 4 Gbytes. Each
task’s address space is divided into four 1 Gbyte
regions and each region can be mapped to physical
addresses by zero, one, or two levels of page tables.
The region with the highest addresses (Region 3) is
common to all tasks.
The 80960MC recognizes the following data types:
In keeping with RISC design principles, the number
of addressing modes is minimal yet includes all
those necessary to ensure efficient execution of
high-level languages such as Ada, C, and Fortran.
Table 2 lists the memory accessing modes.
Non-Numeric:
Table 2. Memory Addressing Modes
• 12-Bit Offset
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
• 32-, 64- and 80-bit real numbers
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3
Large Register Set
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) + 32Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
4
The 80960MC programming environment includes a
large number of registers. 36 registers are available
at any time; this greatly reduces the number of
memory accesses required to perform algorithms,
which leads to greater instruction processing speed.
Two types of general-purpose registers are available: local and global. The 20 global registers
consist of sixteen 32-bit registers (G0 though G15)
and four 80-bit registers (FP0 through FP3). These
80960MC
registers perform the same function as the generalpurpose registers provided in other popular microprocessors. The term global refers to the fact that
these registers retain their contents across procedure calls.
The local registers are procedure-specific. For each
procedure call, the 80960MC allocates 16 local
registers (R0 through R15). Each local register is 32
bits wide. Any register can also be used for floatingpoint operations; the 80-bit floating-point registers
are provided for extended precision.
1.1.4
Multiple Register Sets
To further increase the efficiency of the register set,
multiple sets of local registers are stored on-chip
(See Figure 4). This cache holds up to four local
register frames, which means that up to three procedure calls can be made without having to access the
procedure stack resident in memory.
Although programs may have procedure calls nested
many calls deep, a program typically oscillates back
and forth between only two to three levels. As a
result, with four stack frames in the cache, the probability of having a free frame available on the cache
when a call is made is very high. Runs of representative C-language programs show that 80% of the calls
are handled without needing to access memory.
When four or more procedures are active and a new
procedure is called, the 80960MC moves the oldest
local register set in the stack-frame cache to a
procedure stack in memory to make room for a new
set of registers. Global register G15 is the frame
pointer (FP) to the procedure stack.
Global registers are not exchanged on a procedure
call, but retain their contents, making them available
to all procedures for fast parameter passing.
1.1.5
Instruction Cache
To further reduce memory accesses, the 80960MC
includes a 512-byte on-chip instruction cache. The
instruction cache is based on the concept of locality
of reference; most programs are typically not
executed in a steady stream but consist of many
branches, loops and procedure calls that lead to
jumping back and forth in the same small section of
code. Thus, by maintaining a block of instructions in
5
cache, the number of memory references required to
read instructions into the processor is greatly
reduced.
To load the instruction cache, instructions are
fetched in 16-byte blocks; up to four instructions can
be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction is
already in the cache when it is needed.
Code for small loops often fits entirely within the
cache, leading to an increase in processing speed
since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
is there on the procedure’s return.
1.1.6
Register Scoreboarding
The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by using register scoreboarding.
Register scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
contents is accompanied by a test of the scoreboard
bit to ensure that the load has completed before
processing continues. Since the processor does not
need to wait for the LOAD to complete, it can
execute additional instructions placed between the
LOAD and the instruction that uses the register
contents, as shown in the following example:
ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add R4, R5, R6
In essence, the two unrelated instructions between
LOAD and ADD are executed “for free” (i.e., take no
apparent time to execute) because they are
executed while the register is being loaded. Up to
three load instructions can be pending at one time
with three corresponding scoreboard bits set. By
exploiting this feature, system programmers and
compiler writers have a useful tool for optimizing
execution speed.
80960MC
ONE OF FOUR
LOCAL
REGISTER SETS
REGISTER
CACHE
LOCAL REGISTER SET
R0
0
31
R15
Figure 3. Multiple Register Sets Are Stored On-Chip
1.1.7
Memory Management and Protection
The 80960MC is ideal for multitasking applications
that require software protection and a large address
space. To ensure the highest level of performance
possible, the memory management unit (MMU) and
translation look-aside buffer (TLB) are contained onchip.
The 80960MC supports a conventional form of
demand-paged virtual memory in which the address
space is divided into 4-Kbyte pages. Studies indicate
that a 4-Kbyte page is the optimum size for a broad
range of applications.
Each page table entry includes a 2-bit page rights
field that specifies whether the page is a no-access,
read-only, or read-write page. This field is interpreted differently depending on whether the current
task (process) is executing in user or supervisor
mode, as shown below:
Rights
00
01
10
11
6
User
No Access
No Access
Read-Only
Read-Write
Supervisor
Read-Only
Read-Write
Read-Write
Read-Write
1.1.8
Floating-Point Arithmetic
In the 80960MC, floating-point arithmetic is an
integral part of the architecture. Having the floatingpoint unit integrated on-chip provides two advantages. First, it improves the performance of the chip
for floating-point applications, since no additional
bus overhead is associated with floating-point calculations, thereby leaving more time for other bus operations such as I/O. Second, the cost of using
floating-point operations is reduced because a
separate coprocessor chip is not required.
The 80960MC floating-point (real-number) data
types include single-precision (32-bit), double-precision (64-bit) and extended precision (80-bit) floatingpoint numbers. Any registers may be used to
execute floating-point operations.
The processor provides hardware support for both
mandatory and recommended portions of IEEE
Standard 754 for floating-point arithmetic, including
all arithmetic, exponential, logarithmic and other
transcendental functions. Table 3 shows execution
times for some representative instructions.
80960MC
Table 3. Sample Floating-Point Execution Times
(µs) at 25 MHz
Function
Add
Subtract
Multiply
Divide
32-Bit
0.4
0.4
0.7
1.3
64-Bit
0.5
0.5
1.3
2.9
Square Root
Arctangent
Exponent
Sine
Cosine
3.7
10.1
11.3
15.2
15.2
3.9
13.1
12.5
16.6
16.6
1.1.9
Multitasking Support
Multitasking programs commonly involve the monitoring and control of an external operation, such as
the activities of a process controller or the movements of a machine tool. These programs generally
consist of a number of processes that run independently of one another, but share a common
database or pass data among themselves.
The 80960MC offers several hardware functions
designed to support multitasking systems. One
unique feature, called self-dispatching, allows a
processor to switch itself automatically among
scheduled tasks. When self-dispatching is used, all
the operating system is required to do is place the
task in the scheduling queue.
When the processor becomes available, it
dispatches the task from the beginning of the queue
and then executes it until it becomes blocked, interrupted, or until its time-slice expires. It then returns
the task to the end of the queue (i.e., automatically
reschedules it) and dispatches the next ready task.
During these operations, no communication between
the processor and the operating system is necessary
until the running task is complete or an interrupt is
issued.
1.1.10 Synchronization and Communication
The 80960MC also offers instructions to set up and
test semaphores to ensure that concurrent tasks
remain synchronized and no data inconsistency
results. Special data structures, known as communication ports, provide the means for exchanging
parameters and data structures. Transmission of
7
information by means of communication ports is
asynchronous and automatically buffered by the
processor.
Communication between tasks by means of ports
can be carried out independently of the operating
system. Once the ports have been set up by the
programmer, the processor handles the message
passing automatically.
1.1.11 High Bandwidth Local Bus
The 80960MC CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus).
The L-Bus provides a direct communication path
between the processor and the memory and I/O
subsystem interfaces. The processor uses the L-Bus
to fetch instructions, manipulate memory and
respond to interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• High bandwidth reads and writes with 66.7
MBytes/s burst (at 25 MHz)
• Special signal to indicate whether a memory transaction can be cached
Table 4 defines L-bus signal names and functions;
Table 5 defines other component-support signals
such as interrupt lines.
1.1.12 Multiple Processor Support
One means of increasing the processing power of a
system is to run two or more processors in parallel.
Since microprocessors are not generally designed to
run in tandem with other processors, designing such
a system is usually difficult and costly.
The 80960MC solves this problem by offering a
number of functions to coordinate the actions of
multiple processors. First, messages can be passed
between processors to initiate actions such as
flushing a cache, stopping or starting another
processor, or preempting a task. The messages are
passed on the bus and allow multiple processors to
run together smoothly, with rare need to lock the bus
or memory.
80960MC
Second, a set of synchronization instructions help
maintain memory coherency. These instructions
permit several processors to modify memory at the
same time without inserting inaccuracies or ambiguities into shared data structures.
The self-dispatching mechanism — in addition to
being used in single-processor systems — provides
the means to increase the performance of a system
merely by adding processors. Each processor can
either work on the same pool of tasks (sharing the
same queue with other processors) or can be
restricted to its own queue.
When processors perform system operation, they
synchronize themselves by using atomic operations
and sending special messages between each other.
In theory, changing the number of processors in a
system does not require a software change.
Software executes correctly regardless of the
number of processors in the system; systems with
more processors simply execute faster.
1.1.13 Interrupt Handling
The 80960MC can be interrupted in two ways: by the
activation of one of four interrupt pins or by sending
a message on the processor’s data bus.
The 80960MC is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
An interrupt message is made up of a vector number
and an interrupt priority. When the interrupt priority is
greater than that of the currently running task, the
processor accepts the interrupt and uses the vector
as an index into the interrupt table. When the priority
of the interrupt message is below that of the current
task, the processor saves the information in a
section of the interrupt table reserved for pending
interrupts.
1.1.14 Debug Features
The 80960MC has built-in debug capabilities,
including two types of breakpoints and six trace
modes. Debug features are controlled by two
internal 32-bit registers: the Process-Controls Word
and the Trace-Controls Word. By setting bits in these
8
control words, a software debug monitor can closely
control how the processor responds during program
execution.
The 80960MC has both hardware and software
breakpoints. It provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automatically called.
The 80960MC also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960MC
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960MC’S
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.15 Fault Detection
The 80960MC has an automatic mechanism to
handle faults. There are ten fault types include
floating point, trace and arithmetic faults. When the
processor detects a fault, it automatically calls the
appropriate fault handling routine and saves the
current instruction pointer and necessary state information to make efficient recovery possible. The
processor posts diagnostic information on the type of
fault to a Fault Record. Like interrupt handling
routines, fault handling routines are usually written to
meet the needs of specific applications and are often
included as part of the operating system or kernel.
For each of the ten fault types, numerous subtypes
provide specific information about a fault. For
example, a floating point fault may have the subtype
set to an Overflow or Zero-Divide fault. The fault
handler can use this specific information to respond
correctly to the fault.
80960MC
1.1.16 Inter-Agent Communications (IAC)
To coordinate their actions, processors in a multiple
processor system need a means for communicating
with each other. The 80960MC does this through a
mechanism known as “IACs” — Inter-Agent Communication messages.
IAC messages cause a variety of actions including
starting and stopping processors, flushing instruction
caches and TLBs, and sending interrupts to other
processors in the system. The upper 16 Mbytes of
the processor’s physical memory space is reserved
for sending and receiving IAC messages.
1.1.17 Built-in Testability
Upon reset, the 80960MC automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. When a problem is discovered at any point
during the self-test, the 80960MC asserts its
FAILURE pin and does not begin program execution. Self test takes approximately 47,000 cycles to
complete.
System manufacturers can use the 80960MC’s selftest feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.18 Compatibility with 80960K-Series
Application programs written for the 80960K-Series
microprocessors can be run on the 80960MC
without modification. The 80960K-Series instruction
set forms the core of the 80960MC’s instructions, so
binary compatibility is assured.
1.1.19 CHMOS
The 80960MC is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semiconductor) process. The 80960MC is currently available
at 25 MHz.
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 1 of 3)
NAME
CLK2
LAD31:0
TYPE
DESCRIPTION
I
SYSTEM CLOCK provides the fundamental timing for 80960MC systems. It is
divided by two inside the 80960MC to generate the internal processor clock. Refer
to Figure 16, Processor Clock Pulse (CLK2) (pg. 21)
I/O
T.S.
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
from memory. During an address (Ta) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in
words.
LAD1
0
0
1
1
ALE
O
T.S.
LAD0
0
1
0
1
1 Word
2 Words
3 Words
4 Words
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active LOW and floats to a high impedance state during a hold cycle (Th).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
9
80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3)
NAME
TYPE
DESCRIPTION
ADS
O
O.D.
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta
state and deasserted during the following Td state. For a burst transaction, ADS is
asserted again every Td state where READY was asserted in the previous cycle.
W/R
O
O.D.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read.
It is latched on-chip and remains valid during Td cycles.
DT/R
O
O.D.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the L-Bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment;
it is high during Ta and Td cycles for a write. DT/R never changes state when DEN
is asserted.
DEN
O
O.D.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all Td and Tw states. The DEN# line is an open drain-output of the
80960MC.
READY
LOCK
I
I/O
O.D.
READY indicates that data on LAD lines can be sampled or removed. When
READY is not asserted during a Td cycle, the Td cycle is extended to the next cycle
by inserting a wait state (Tw ) and ADS is not asserted in the next cycle.
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. When the
pin is already asserted, the processor waits until it is not asserted. When the pin is
not asserted, the processor asserts LOCK during the Ta cycle of the read transaction. The processor deasserts LOCK in the Ta cycle of the write transaction.
During the time LOCK is asserted, a bus agent can perform a normal read or write
but not a RMW operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
BE3:0
O
O.D.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
The byte enables are provided in advance of data:
Byte enables asserted during Ta specify the bytes of the first data word.
Byte enables asserted during Td specify the bytes of the next data word, if any (the
word to be transmitted following the next assertion of READY).
Byte enables that occur during Td cycles that precede the last assertion of READY
are undefined. Byte enables are latched on-chip and remain constant from one Td
cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus
agents are required to assert only adjacent byte enables (e.g., asserting just BE0
and BE2 is not permitted) and are required to assert at least one byte enable.
Address bits A0 and A1 can be decoded externally from the byte enables.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
10
80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 3 of 3)
NAME
HOLD/
HLDAR
TYPE
DESCRIPTION
I
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it floats its
three-state bus lines and open-drain control lines, asserts HLDA and enters the Th
state. When HOLD deasserts, the processor deasserts HLDA and enters the Ti or
Ta state.
HOLD ACKNOWLEDGE RECEIVED: Indicates that the processor has acquired
the bus. When the processor is initialized as the secondary bus master this input is
interpreted as HLDAR.
Refer to Figure 18, HOLD Timing (pg. 22).
HLDA/
HOLDR
O
T.S.
HOLD ACKNOWLEDGE: Relinquishes control of the bus to another bus master.
When the processor is initialized as the primary bus master this output is
interpreted as HLDA. When HOLD is deasserted, the processor deasserts HLDA
and goes to either the Ti or Ta state.
HOLD REQUEST: Indicates a request to acquire the bus. When the processor is
initialized as the secondary bus master this output is interpreted as HOLDR.
Refer to Figure 18, HOLD Timing (pg. 22).
CACHE/
TAG
O
T.S.
CACHE indicates when an access is cacheable during a Ta cycle. It is not asserted
during any synchronous access, such as a synchronous load or move instruction
used for sending an IAC message. The CACHE signal floats to a high impedance
state when the processor is idle.
TAG is an input/output signal that, during Td and Tw cycles, identifies the contents
of a 32-bit word as either data (TAG = 0) or an access descriptor (TAG = 1).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
Table 5. 80960MC Pin Description: Support Signals (Sheet 1 of 2)
NAME
BADAC
TYPE
DESCRIPTION
I
BAD ACCESS, when asserted in the cycle following the one in which the last
READY of a transaction is asserted, indicates that an unrecoverable error has
occurred on the current bus transaction or that a synchronous load/store instruction
has not been acknowledged.
During system reset the BADAC signal is interpreted differently. When the signal is
high, it indicates that this processor will perform system initialization. When low,
another processor in the system will perform system initialization instead.
RESET
I
RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for BADAC and
IAC/INT0), the three-state output pins are placed in a high impedance state and
other output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The
HIGH to LOW transition of RESET should occur after the rising edge of both CLK2
and the external bus clock and before the next rising edge of CLK2.
Refer to Figure 17, RESET Signal Timing (pg. 21).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
11
80960MC
Table 5. 80960MC Pin Description: Support Signals (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
FAILURE
O
O.D.
INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
After RESET deasserts and before the first bus transaction begins, FAILURE
asserts while the processor performs a self-test. When the self-test completes
successfully, then FAILURE deasserts. The processor then performs a zero
checksum on the first eight words of memory. When it fails, FAILURE asserts for a
second time and remains asserted. When it passes, system initialization continues
and FAILURE remains deasserted.
IAC/INT0
I
INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines
how the signal is interpreted. To signal an interrupt or IAC request in a synchronous
system, this pin — as well as the other interrupt pins — must be enabled by being
deasserted for at least one bus cycle and then asserted for at least one additional
bus cycle. In an asynchronous system the pin must remain deasserted for at least
two bus cycles and then asserted for at least two more bus cycles.
LOCAL
PROCESSOR
NUMBER
LOCAL PROCESSOR NUMBER - this signal is interpreted differently during
system reset. When the signal is a high voltage level it indicates that this processor
is a primary bus master (local processor number = 0). When at a low voltage level it
indicates that this processor is a secondary bus master (local processor number
= 1).
INT1
I
INTERRUPT 1, like INT0, provides direct interrupt signaling.
INT2/INTR
I
INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. When INT2, it has the same interpretation as the INT0
and INT1 pins. When INTR, it is used to receive an interrupt request from an
external interrupt controller.
INT3/INTA
I/O
O.D.
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. When INT3, it has the same interpretation as
the INT0, INT1 and INT2 pins. When INTA, it is used as an output to control
interrupt-acknowledge transactions. The INTA output is latched on-chip and
remains valid during Td cycles; as an output, it is open-drain.
N.C.
N/A
NOT CONNECTED indicates pins should not be connected. Never connect any pin
marked N.C. as these pins may be reserved for factory use.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
12
80960MC
2.0
ELECTRICAL SPECIFICATIONS
2.1
Power and Grounding
NOTE:
Do not connect external logic to pins marked N.C.
VCC
OPEN-DRAIN OUTPUT
The 80960MC is implemented in CHMOS IV technology and therefore has modest power requirements. Its high clock frequency and numerous
output buffers (address/data, control, error and arbitration signals) can cause power surges as multiple
output buffers simultaneously drive new signal
levels. For clean on-chip power distribution, VCC and
VSS pins separately feed the device’s functional
units. Power and ground connections must be made
to all 80960MC power and ground pins. On the
circuit board, all Vcc pins must be strapped closely
together, preferably on a power plane; all Vss pins
should be strapped together, preferably on a ground
plane.
2.2
220 Ω
330 Ω
Low Drive Network:
VOH = 3.0 V
IOL = 20.7 mA
Figure 4. Connection Recommendations
for Low Current Drive Network
VCC
Power Decoupling
Recommendations
OPEN-DRAIN OUTPUT
180 Ω
Place a liberal amount of decoupling capacitance
near the 80960MC. When driving the L-bus the
processor can cause transient power surges, particularly when connected to a large capacitive load.
High Drive Network:
VOH = 3.4 V
IOL = 25.3 mA
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance is reduced by shortening
board traces between the processor and decoupling
capacitors as much as possible.
2.3
Connection Recommendations
For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, when
one or more interrupt lines are not used, they should
be pulled up. No inputs should ever be left floating.
All open-drain outputs require a pull-up device.
While in most cases a simple pull-up resistor is
adequate, a network of pull-up and pull-down resistors biased to a valid VIH (>3.0 V) and terminated in
the characteristic impedance of the circuit board is
recommended to limit noise and AC power
consumption. Figure 5 and Figure 6 show recommended values for the resistor network for low and
high current drive, assuming a characteristic impedance of 100 Ω. Terminating output signals in this
fashion limits signal swing and reduces AC power
consumption.
13
390 Ω
Figure 5. Connection Recommendations
for High Current Drive Network
2.4
Characteristic Curves
Figure 7 shows typical supply current requirements
over the operating temperature range of the
processor at supply voltage (VCC) of 5 V. Figure 8
and Figure 9 show the typical power supply current
(ICC ) that the 80960MC requires at various operating
frequencies when measured at three input voltage
(VCC ) levels and two temperatures.
For a given output current (IOL) the curve in
Figure 10 shows the worst case output low voltage
(VOL). Figure 11 shows the typical capacitive
derating curve for the 80960MC measured from 1.5V
on the system clock (CLK) to 1.5V on the falling
edge and 1.5V on the rising edge of the L-Bus
address/data (LAD) signals.
80960MC
380
VCC = 5.0 V
360
25 MHz
20 MHz
16 MHz
POWER SUPPLY CURRENT (mA)
340
320
300
280
260
240
220
200
-60 -40 -20 0
20
40
60
80
100 120 140
CASE TEMPERATURE (°C)
Figure 6. Typical Supply Current vs. Case Temperature
400
TEMP = +22°C
380
@5.5V
@4.5V
TYPICAL SUPPLY CURRENT (mA)
360
@5.0V
340
320
300
280
260
240
220
200
180
16
20
25
OPERATING FREQUENCY (MHz)
Figure 7. Typical Current vs. Frequency (Room Temp)
14
80960MC
380
TEMP = +22°C
360
@5.5V
TYPICAL SUPPLY CURRENT (mA)
340
@5.0V
@4.5V
320
300
280
260
240
220
200
180
160
16
20
25
OPERATING FREQUENCY (MHz)
Figure 8. Typical Current vs. Frequency (Hot Temp)
(TEMP = +85°C, VCC = 4.5V)
30
FALLING
THREE-STATE OUTPUT
VALID DELAY(ns)
OUTPUT LOW VOLTAGE (V)
(TEMP = +85°C, VCC = 4.5V)
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
50
OUTPUT LOW CURRENT(mA)
Figure 9. Worst-Case Voltage vs. Output Current
on Open-Drain Pins
15
25
20
15
10
RISING
5
0
0 20 40 60 80 100
CAPACITIVE LOAD(pF)
Figure 10. Capacitive Derating Curve
80960MC
2.5
Test Load Circuit
Figure 12 illustrates the load circuit used to test the
80960MC’s three-state pins; Figure 13 shows the
load circuit used to test the open drain outputs. The
open drain test uses an active load circuit in the form
of a matched diode bridge. Since the open-drain
outputs sink current, only the IOL legs of the bridge
are necessary and the IOH legs are not used. When
the 80960MC driver under test is turned off, the
output pin is pulled up to VREF (i.e., VOH). Diode D1
is turned off and the IOL current source flows through
diode D2.
When the 80960MC open-drain driver under test is
on, diode D1 is also on and the voltage on the pin
being tested drops to VOL. Diode D2 turns off and IOL
flows through diode D1.
THREE-STATE OUTPUT
CL
CL = 50 pF for all signals
Figure 11. Test Load Circuit for Three-State
Output Pins
IOL
OPEN-DRAIN OUTPUT
D1
CL
D2
I OL Tested at 25 mA
VREF = VCC
D1 and D2 are matched
CL = 50 pF for all signals
Figure 12. Test Load Circuit for Open-Drain
Output Pins
16
80960MC
2.6
Absolute Maximum Ratings
Operating Temperature (PGA) ......
Storage Temperature.....................
Voltage on Any Pin ........................
Power Dissipation ..........................
2.7
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings
only. Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions”
may affect device reliability.
0° C to +85° C Case
–65° C to +150° C
–0.5 V to VCC +0.5 V
2.5 W (25 MHz)
DC Characteristics
PGA:
80960MC (25 MHz) TCASE = 0° C to +85° C, VCC = 5V ± 5%
Table 6. DC Characteristics
Symbol
Parameter
VIL
Input Low Voltage
Min
Max
Units
–0.3
+0.8
V
Notes
VIH
Input High Voltage
2.0
VCC + 0.3
V
VCL
CLK2 Input Low Voltage
–0.3
+0.8
V
VCH
CLK2 Input High Voltage
0.55 VCC
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
(1,2)
VOH
Output High Voltage
V
(3,4)
ICC
Power Supply Current:
16 MHz
20 MHz
25 MHz
315
360
420
mA
mA
mA
(5)
(5)
(5)
ILI
Input Leakage Current
±15
µA
0 ≤ VIN ≤ VCC
2.4
ILO
Output Leakage Current
±15
µA
0.45 ≤ VO ≤ VCC
CIN
Input Capacitance
10
pF
fC = 1 MHz (6)
CO
Output Capacitance
12
pF
fC = 1 MHz (6)
CCLK
Clock Capacitance
10
pF
fC = 1 MHz (6)
NOTES:
1. For three-state outputs, this parameter is measured at:
Address/Data
4.0 mA
Controls
5.0 mA
2. For open-drain outputs 25 mA
3. This parameter is measured at:
Address/Data
–1.0 mA
Controls
–0.9 mA
–5.0 mA
ALE
4. Not measured on open-drain outputs.
5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions
in Figure 12 and Figure 13. Figure 7, Figure 8 and Figure 9 indicate typical values.
6. Input, output and clock capacitance are not tested.
17
80960MC
2.8
For input timings the specifications refer to the time
at which the signal reaches (for input setup) or
leaves (for hold time) the TTL levels of LOW (0.8 V)
or HIGH (2.0 V). All AC testing should be done with
input voltages of 0.4 V and 2.4 V, except for the
clock (CLK2), which should be tested with input
voltages of 0.45 V and 0.55 VCC.
AC Specifications
This section describes the AC specifications for the
80960MC pins. All input and output timings are specified relative to the 1.5 V level of the rising edge of
CLK2. For output timings the specifications refer to
the time it takes the signal to reach 1.5 V.
A
EDGE
CLK2
B
1.5V
D
C
1.5V
A
B
1.5V
C
1.5V
0.8V
OUTPUTS:
LAD 31:0
ADS
W/R, DEN
BE3:0
HLDA/HOLDR
CACHE
LOCK, INTA
T6
T9
1.5V
T8
T13
T8
T14
1.5V
1.5V
ALE
1.5V
VALID OUTPUT
T7
T6
T9
1.5V
DT/R
T10
INPUTS:
LAD31:0
BADAC
IAC/INT0, INT1
INT2/INTR, INT3
HOLD, HLDAR
LOCK
READY
VALID OUTPUT
T11
2.0V
2.0V
0.8V
0.8V
T12
1.5V
T11
2.0V
2.0V
0.8V
0.8V
VALID INPUT
Figure 13. Drive Levels and Timing Relationships for 80960MC Signals
18
80960MC
Ta
Td
Ta
Tr
Td
Td
Tr
T1
T3
CLK2
T2
CLK
T6
LAD
(31-0)
T13
T9
Address
T10
T11
T6
T13
Address
T8
Data
T8 T14
T9
T6
Data
T9
ALE#
T7
T7
ADS#
BE(0:3)#
T13
T14
T9
T13
W/R#
T9
T6
T9
T6
T14
DT/R
T6
T6
DEN#
T12 T11
T12 T11
READY#
T12 T11
A4484-01
Figure 14. Timing Relationship of L-Bus Signals
Bus
State
Bus
State
Bus
State
Ta
Td
Tr
CLK2
CLK
Figure 15. System and Processor Clock Relationship
19
80960MC
Table 7. 80960MC AC Characteristics (25 MHz)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock
T1
Processor Clock Period (CLK2)
20
125
ns
VIN = 1.5V
T2
Processor Clock Low Time (CLK2)
5
ns
VIL = 10% Point = 1.2V
T3
Processor Clock High Time (CLK2)
5
ns
VIH = 90% Point = 0.1V + 0.5 VCC
T4
Processor Clock Fall Time (CLK2)
10
ns
VIN = 90% Point to 10% Point (1)
T5
Processor Clock Rise Time (CLK2)
10
ns
VIN = 10% Point to 90% Point (1)
Synchronous Outputs
Output Valid Delay
2
18
ns
HLDA Output Valid Delay
4
23
ns
T7
ALE Width
12
T8
ALE Output Valid Delay
2
18
ns
T9
Output Float Delay
2
18
ns
(2)
T9H
HLDA Output Float Delay
4
20
ns
(2)
T10
Input Setup 1
3
ns
(3)
T11
Input Hold
5
ns
(3)
HOLD Input Hold
4
ns
T12
Input Setup 2
7
ns
T13
Setup to ALE Inactive
8
ns
T14
Hold after ALE Inactive
8
ns
T15
Reset Hold
3
ns
T16
Reset Setup
5
ns
T17
Reset Width
820
ns
T6
T6H
ns
Synchronous Inputs
T11H
41 CLK2 Periods Minimum
NOTES:
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than ILO. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be synchronous or asynchronous.
20
80960MC
T1
T3
HIGH LEVEL (MIN) 0.55VCC
90%
1.5 V
10%
LOW LEVEL (MAX) 0.8V
T5
T2
T4
Figure 16. Processor Clock Pulse (CLK2)
CLK2
CLK
RESET
...
...
...
FIRST
A B C
D
A
T15 T16
T17
OUTPUTS
...
INIT PARAMETERS (BADAC,
INT0/IAC) MUST BE SET UP 8 CLOCKS
PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD
BEYOND THIS CLK2 EDGE
Figure 17. RESET Signal Timing
21
T15 = RESET HOLD
T16 = RESET SETUP
T17 = RESET WIDTH
80960MC
Th
Th
Th
Th
CLK2
CLK
T6h
T9h
HOLDR
T12
T11h
HOLD
T6h
T9h
HLDA
T12
T11h
HLDAR
Primary
Secondary
HOLD
HLDA
D
HOLDR
HOLDAR
D
Delay of 5 ns Minimum
is Required
A4490-01
Figure 18. HOLD Timing
2.9
Design Considerations
Input hold times can be disregarded by the designer
whenever the input is removed because a subsequent output from the processor is deasserted (e.g.,
DEN becomes deasserted).
In other words, whenever the processor generates
an output that indicates a transition into a subsequent state, the processor must have sampled any
inputs for the previous state.
Similarly, whenever the processor generates an
output that indicates a transition into a subsequent
state, any outputs that are specified to be three
stated in this new state are guaranteed to be three
stated.
22
3.0
MECHANICAL DATA
3.1
Packaging
The 80960MC is available in one package type: a
132-lead ceramic pin-grid array (PGA). Pins are
arranged 0.100 inch (2.54 mm) center-to-center, in a
14 by 14 matrix, three rows around (see Figure 20).
Dimensions for the PGA package type is given in the
Intel Packaging handbook (Order #240800).
3.1.1
Pin Assignment
Figure 21 shows the view from the PGA bottom (pins
facing up). Table 8 and Table 9 list the function of
each PGA pin.
80960MC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A B C D
E
F G H
J
K
L M N
P
Figure 19. 132-Lead Pin-Grid Array (PGA) Package
23
80960MC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
VCC
N.C. N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
N.C. VSS
VCC
VSS
N.C. N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
N.C. N.C.
N.C.
N.C.
VCC
VSS
VSS VCC
N.C.
N.C.
N.C. N.C.
VSS
VCC
N.C. N.C.
N.C.
DEN
N.C.
VCC
VSS N.C.
N.C.
BE3
FAIL
VSS
VCC N.C.
N.C.
DT/R
BE2
VSS
N.C. N.C.
N.C.
W/R
BE0 LOCK
N.C. N.C.
N.C.
LAD30 READY BE1
N.C. N.C.
N.C.
LAD29 LAD31 CACHE
N.C. N.C.
N.C.
LAD28 LAD26 LAD27
N.C. VSS
N.C.
VCC N.C.
N.C.
INT3 INT1
INT0
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
ALE
ADS HLDA
C
C
HOLD LAD25 BADAC VCC VSS LAD20 LAD13 LAD8 LAD3 VCC
VSS
B
B
LAD23 LAD24 LAD22 LAD21 LAD18 LAD15 LAD12 LAD10 LAD6 LAD2 CLK2 LAD0 RESET VSS
A
A
VCC
1
VSS LAD19 LAD17 LAD 16 LAD14 LAD11 LAD9 LAD7 LAD5 LAD4 LAD1 INT2
2
3
4
5
6
7
8
9
10
11
12
13
VCC
14
Figure 20. 80960MC PGA Pinout—View from Bottom (Pins Facing Up)
24
80960MC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VCC
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
N.C.
N.C.
N.C.
VCC
VSS
N.C.
N.C.
N.C.
N.C.
VCC
VSS
VSS
VCC
N.C.
N.C.
N.C.
VSS
VCC
N.C.
DEN
N.C.
N.C.
VCC
VSS
FAIL
BE3
N.C.
N.C.
N.C.
VSS
BE2
DT/R
N.C.
N.C.
N.C.
LOCK
BE0
W/R
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
N.C.
LAD27 LAD26 LAD28
N.C.
N.C.
VCC
HLDA ADS
INT0
INT1 INT3
P
P
N
M
N
M
L
L
K
J
H
G
F
J
H
XXXXXXXX
XXXXXX
XXXXXX
A80960MC-25
K
G
BE1 READY LAD30
F
CACHE LAD31 LAD29
E
E
D
D
ALE
C
C
VSS
VCC LAD3 LAD8 LAD13 LAD20 VSS
VCC BADAC LAD25 HOLD
B
B
VSS RESET LAD0 CLK2 LAD2 LAD6 LAD10 LAD12 LAD15 LAD18 LAD21 LAD 22 LAD24 LAD23
A
A
VCC
14
INT2 LAD1 LAD4 LAD5 LAD7 LAD9 LAD11 LAD14 LAD16 LAD17 LAD 19 VSS
13
12
11
10
9
8
7
6
5
4
3
2
VCC
1
Figure 21. 80960MC PGA Pinout—View from Top (Pins Facing Down)
25
80960MC
3.2
Pinout
Table 8. 80960MC PGA Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A1
VCC
C6
LAD20
H1
W/R
M10
Signal
VSS
A2
V SS
C7
LAD13
H2
BE0
M11
VCC
A3
LAD19
C8
LAD8
H3
LOCK
M12
N.C.
A4
LAD17
C9
LAD3
H12
N.C.
M13
N.C.
A5
LAD16
C10
VCC
H13
N.C.
M14
N.C.
A6
LAD14
C11
VSS
H14
N.C.
N1
VSS
A7
LAD11
C12
INT3/INTA
J1
DT/R
N2
N.C.
A8
LAD9
C13
INT1
J2
BE 2
N3
N.C.
A9
LAD7
C14
IAC/INT0
J3
VSS
N4
N.C.
A10
LAD5
D1
ALE
J12
N.C.
N5
N.C.
A11
LAD4
D2
ADS
J13
N.C.
N6
N.C.
A12
LAD1
D3
HLDA/HOLDR
J14
N.C.
N7
N.C.
A13
INT2/INTR
D12
VCC
K1
BE3
N8
N.C.
A14
VCC
D13
N.C.
K2
FAILURE
N9
N.C.
B1
LAD23
D14
N.C.
K3
VSS
N10
N.C.
B2
LAD24
E1
LAD28
K12
VCC
N11
N.C.
B3
LAD22
E2
LAD26
K13
N.C.
N12
N.C.
B4
LAD21
E3
LAD27
K14
N.C.
N13
N.C.
N.C.
B5
LAD18
E12
N.C.
L1
DEN
N14
B6
LAD15
E13
VSS
L2
N.C.
P1
V CC
B7
LAD12
E14
N.C.
L3
VCC
P2
N.C.
B8
LAD10
F1
LAD29
L12
VSS
P3
N.C.
B9
LAD6
F2
LAD31
L13
N.C.
P4
N.C.
B10
LAD2
F3
CACHE/TAG
L14
N.C.
P5
N.C.
B11
CLK2
F12
N.C.
M1
N.C.
P6
N.C.
B12
LAD0
F13
N.C.
M2
VCC
P7
N.C.
B13
RESET
F14
N.C.
M3
VSS
P8
N.C.
N.C.
B14
VSS
G1
LAD30
M4
VSS
P9
C1
HOLD/HLDAR
G2
READY
M5
VCC
P10
N.C.
C2
LAD25
G3
BE1
M6
N.C.
P11
N.C.
N.C.
C3
BADAC
G12
N.C.
M7
N.C.
P12
C4
VCC
G13
N.C.
M8
N.C.
P13
VSS
C5
V SS
G14
N.C.
M9
N.C.
P14
V CC
NOTES: Do not connect any external logic to any pins marked N.C.
26
80960MC
Table 9. 80960MC PGA Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
ADS
D2
LAD15
B6
N.C.
J14
N.C.
Pin
P9
ALE
D1
LAD16
A5
N.C.
K13
N.C.
P10
BADAC
C3
LAD17
A4
N.C.
K14
N.C.
P11
P12
BE0
H2
LAD18
B5
N.C.
L13
N.C.
BE1
G3
LAD19
A3
N.C.
L14
N.C.
L2
BE2
J2
LAD20
C6
N.C.
M1
READY
G2
BE3
K1
LAD21
B4
N.C.
M6
RESET
B13
CACHE
F3
LAD22
B3
N.C.
M7
VCC
A1
CLK2
B11
LAD23
B1
N.C.
M8
VCC
A14
DEN
L1
LAD24
B2
N.C.
M9
VCC
C4
DT/R
J1
LAD25
C2
N.C.
M12
VCC
C10
FAILURE
K2
LAD26
E2
N.C.
M13
VCC
D12
HLDA/HOLDR
D3
LAD27
E3
N.C.
M14
VCC
K12
HOLD/HLDAR
C1
LAD28
E1
N.C.
N2
VCC
L3
IAC/INT0
C14
LAD29
F1
N.C.
N3
VCC
M2
INT1
C13
LAD30
G1
N.C.
N4
VCC
M5
INT2/INTR
A13
LAD31
F2
N.C.
N5
VCC
M11
INT3/INTA
C12
LOCK
H3
N.C.
N6
VCC
P1
LAD0
B12
N.C.
D13
N.C.
N7
VCC
P14
A12
N.C.
D14
N.C.
N8
VSS
A2
B10
N.C.
E12
N.C.
N9
VSS
B14
LAD3
C9
N.C.
E14
N.C.
N10
VSS
C5
LAD4
A11
N.C.
F12
N.C.
N11
VSS
C11
LAD5
A10
N.C.
F13
N.C.
N12
VSS
E11
LAD6
B9
N.C.
F14
N.C.
N13
VSS
J3
LAD7
A9
N.C.
G12
N.C.
N14
VSS
K3
LAD8
C8
N.C.
G13
N.C.
P2
VSS
L12
M3
LAD9
A8
N.C.
G14
N.C.
P3
VSS
LAD10
B8
N.C.
H12
N.C.
P4
VSS
M4
LAD11
A7
N.C.
H13
N.C.
P5
VSS
M10
LAD12
B7
N.C.
H14
N.C.
P6
VSS
N1
LAD13
C7
N.C.
J12
N.C.
P7
VSS
P13
LAD14
A6
N.C.
J13
N.C.
P8
W/R
H1
NOTE:
27
LAD1
LAD2
Do not connect external logic to any pins marked N.C.
80960MC
3.3
Maximum allowable ambient temperature (TA)
permitted without exceeding TC is shown by the
graphs in Figure 23, Figure 24 and Figure 25. The
curves assume the maximum permitted supply
current (ICC ) at each speed, VCC of +5.0 V and a
TCASE of +85° C (PGA).
Package Thermal Specification
The 80960MC is specified for operation when case
temperature is within the range 0°C to 85°C (PGA).
Measure case temperature at the top center of the
package. Ambient temperature can be calculated
from:
•
TJ = TC + P*θjc
•
TA = TJ + P*θja
•
TC = TA + P*[θja−θjc]
Values for θja and θjc for various airflows are given in
Table 10 for the PGA package. The PGA’s θja can
be reduced by adding a heatsink.
Table 10. 80960MC PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θ Junction-to-Case
2
2
2
2
2
2
2
θ Case-to-Ambient
19
18
17
15
12
10
9
(No Heatsink)
θ Case-to-Ambient
16
15
14
12
9
7
6
15
14
13
11
8
6
5
(Unidirectional
Heatsink)
NOTES:
1. This table applies to 80960MC PGA plugged into socket or soldered directly to board.
2. θ JA = θJC + θCA
3. θ J-CAP = 4°C/W (approx.)
θ J-PIN = 4°C/W (inner pins) (approx.)
θ J-PIN = 8°C/W (outer pins) (approx.)
28
θJC
θJ-CAP
(Omnidirectional
Heatsink)
θ Case-to-Ambient
θJA
θJ-PIN
80960MC
85
80
TEMPERATURE (o C)
75
70
65
60
55
50
45
40
0
100
200
300
400
500
600
700
AIRFLOW (ft/min)
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
Figure 22. 25 MHz Maximum Allowable Ambient Temperature
29
800
80960MC
4.0
WAVEFORMS
The following figures present waveforms for various transactions on the 80960MC’S local bus:
• Figure 23, Non-Burst Read and Write Transactions Without Wait States (pg. 30)
• Figure 24, Burst Read and Write Transaction Without Wait States (pg. 31)
• Figure 25, Burst Write Transaction with 2, 1, 1, 1 Wait States (pg. 32)
• Figure 26, Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word
Boundary (1, 0, 0, 0 Wait States) (pg. 33)
• Figure 27, Interrupt Acknowledge Transaction (pg. 34)
• Figure 28, Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) (pg. 35)
Ta
Td
Tr
Ta
Td
Tr
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 23. Non-Burst Read and Write Transactions Without Wait States
30
80960MC
Ta
Td
Td
Tr
Ta
Td
Td
Td
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 24. Burst Read and Write Transaction Without Wait States
31
Td
Tr
80960MC
Ta
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States
32
Td
Tr
80960MC
Ta
Tw
Td
Td
Td
Td
Tr
Ta
Tw
Td
Tr
CLK2
CLK
LAD31:0
ALE
ADS
BE3:2
BE1:0
W/R
DT/R
DEN
READY
Figure 26. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad
Word Boundary (1, 0, 0, 0 Wait States)
33
80960MC
PREVIOUS
CYCLE
INTERRUPT
ACKNOWLEDGEMENT
INTERRUPT
ACKNOWLEDGEMENT
IDLE
(5 BUS STATES)
CYCLE 1
TX
TX
Ta
Td
CYCLE 2
Tr
TI
TI
TI
TI
TI
Ta
Tw
Td
Tr
CLK2
CLK
INTR
LAD31:0
ADDR
ADDR
VECTOR
ALE
ADS
INTA
DT/R
DEN
LOCK
READY
NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.
Figure 27. Interrupt Acknowledge Transaction
34
80960MC
PBM BUS
STATE
SBM BUS
STATE
Ta
Td
Th
Th
Th
Th
Ta
Td
Td
Th
Th
Th
Th
Th
Ti
Thr
Thr
Thr
Ta
Td
Tr
Thr
Thr
Thr
Thr
Ta
Td
Td
Tr
Ti
CLK
LAD31_
LAD0
Addr
Data
Addr
Data
Addr
Data
Data
Addr
Data
Data
W/R#
PBM ALE#
SBM ALE#
READY#
SBM
HOLDR
PBM
HOLD
PBM
HLDA
SBM
HLDAR
A4492-01
Figure 28. Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master)
5.0
REVISION HISTORY
No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to
date is incorporated into this revision. The sections significantly changed since the previous revision are:
Section
Last
Rev.
Description
This is the initial commercial data sheet for the A80960MC.
35