ETC ACS8515REV2.1LC/P

ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
Line Card Protection Switch
for SONET or SDH Network Elements
FINAL
Description
Features
The ACS8515 is a highly integrated, single-chip
solution for ‘hit-less’ protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching against master clock failure.
A further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g.
8 kHz distributed on the back plane and
19.44 MHz generated on the line cards.
An SPI(1) compatible serial port is incorporated,
providing access to the configuration and status
registers for device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full temperature calibration - as required by the application.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
•Suitable for Stratum 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia
specifications
•Three SEC input clocks, from 2 kHz to
155.52 MHz
•Generates two SEC output clocks, up to
311.04 MHz
•Frequency translation of SEC input clock to a
different local line card clock
•Robust input clock source frequency and
activity monitoring on all inputs
•Supports Free-run, Locked and Holdover
modes of operation
•Automatic ‘hit-less’ source switchover on loss
of input
•External force fast switch between SEC inputs
•Phase build out for output clock phase
continuity during input switchover
•SPI(1) compatible serial microprocessor interface
•Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
•Single +3.3 V operation. +5 V I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 64 pin LQFP package
(1) SPI is a trademark of Motorola Corporation
Block Diagram
Figure 1. Simple Block Diagram
3 x S EC Input
Mas ter/Slave
+ Standby:
N x 8kHz
1.544/2.048MHz
6.48M Hz
19.44MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
MFrSync
3xSEC
Input
Ports
2xSEC
APLL
Monitors
DPLL
Frequency Synthes is
Frequency
Dividers
MFrSync
Chip C lock
Generator
Priority
T able
Register
Set
Output
Ports
FrSync
MFrSync
2 x S EC Output
including:
1.544/2.048MH z
3.088/4.096MH z
6.176/8.192MH z
12.352/16.384MH z
19.44MH z
38.88MH z
155.52MH z
311.04MH z
2kHz MF rSync
8kHz FrSync
SPI Compatible Serial
Microprocessor Port
TCXO or XO
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ACS8515 Rev2.1 LC/P
FINAL
ADVANCED COMMUNICATIONS
Table of Contents
List of Sections
Description ................................................................................................................................................................................................ 1
Block Diagram ........................................................................................................................................................................................... 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 4
Pin Descriptions ........................................................................................................................................................................................ 5
Functional Description ............................................................................................................................................................................. 7
Local Oscillator Clock ..................................................................................................................................................................................... 7
Crystal Frequency Calibration ........................................................................................................................................................ 7
Input Reference Clock Ports ......................................................................................................................................................................... 8
Input Wander and Jitter Tolerance ............................................................................................................................................................ 10
Output Clock Ports ........................................................................................................................................................................................ 11
Low Speed Output Clock ................................................................................................................................................................ 11
High Speed Output Clock .............................................................................................................................................................. 12
Frame Sync and Multi-Frame Sync Clocks ................................................................................................................................ 12
Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 12
Output Wander and Jitter ............................................................................................................................................................................ 13
Phase Variation ............................................................................................................................................................................................. 14
Phase Build Out ............................................................................................................................................................................................. 16
Microprocessor Interface ............................................................................................................................................................................. 16
Register Set ..................................................................................................................................................................................... 16
Configuration Registers ................................................................................................................................................................. 16
Status Registers .............................................................................................................................................................................. 16
Register Access ............................................................................................................................................................................... 17
Interrupt Enable and Clear ......................................................................................................................................................................... 17
Register Map .................................................................................................................................................................................................. 18
Register Map Description ........................................................................................................................................................................... 21
Selection of Input Reference Clock Source ............................................................................................................................................. 29
Automatic Control Selection ........................................................................................................................................................ 29
Ultra Fast Switching ....................................................................................................................................................................... 30
External Protection Switching ..................................................................................................................................................... 30
Activity Monitoring ....................................................................................................................................................................................... 30
Modes of Operation ...................................................................................................................................................................................... 32
Free-run Mode ................................................................................................................................................................................. 32
Pre-Locked Mode ............................................................................................................................................................................ 32
Locked Mode .................................................................................................................................................................................... 32
Lost-Phase Mode ............................................................................................................................................................................. 33
Holdover Mode ................................................................................................................................................................................ 33
Pre-Locked(2) Mode ........................................................................................................................................................................ 33
Power On Reset - PORB ............................................................................................................................................................................... 33
Electrical Specification .......................................................................................................................................................................... 35
Serial Microprocessor Interface Timing ............................................................................................................................................... 44
Package Information .............................................................................................................................................................................. 46
Thermal Conditions ....................................................................................................................................................................................... 47
Application Information .......................................................................................................................................................................... 48
Appendix A Rev2.1 Changes Described ............................................................................................................................................... 49
Revision History ...................................................................................................................................................................................... 49
Ordering Information .............................................................................................................................................................................. 50
Disclaimers ..................................................................................................................................................................................................... 50
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List of Figures
Figure 1. Simple Block Diagram .............................................................................................................................................................. 1
Figure 2. ACS8515 Pin Diagram ............................................................................................................................................................. 4
Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) .................................................................................................................... 11
Figure 4. Minimum Input Jitter Tolerance (DS1/E1) ........................................................................................................................... 12
Figure 5. Wander and Jitter Transfer Measured Characteristics ........................................................................................................ 14
Figure 6. Maximum Time Interval Error of TOUT0 Output Port ........................................................................................................... 15
Figure 7. Time Deviation of TOUT0 Output Port ................................................................................................................................... 15
Figure 8. Phase Error Accumulation of TOUT0 Output Port in Holdover Mode ................................................................................. 15
Figure 9. Inactivity and Irregularity Monitoring .................................................................................................................................... 30
Figure 10. Automatic Mode Control State Diagram ............................................................................................................................ 34
Figure 11. Recommended Line Termination for PECL Input/Output Ports ....................................................................................... 38
Figure 12. Recommended Line Termination for LVDS Input/Output Ports ....................................................................................... 39
Figure 13. Input/Output Timing ............................................................................................................................................................. 43
Figure 14. Serial Interface Read Access Timing .................................................................................................................................. 44
Figure 15. Serial Interface Write Access Timing ................................................................................................................................. 45
Figure 16. LQFP Package ....................................................................................................................................................................... 46
Figure 17. Typical 64 Pin LQFP Footprint .............................................................................................................................................. 47
Figure 18. Simplified Application Schematic ....................................................................................................................................... 48
List of Tables
Table 1. Power Pins .................................................................................................................................................................................... 5
Table 2. No Connections ............................................................................................................................................................................ 5
Table 3. Other Pins ..................................................................................................................................................................................... 6
Table 4. Input Reference Source Selection and Group Allocation ....................................................................................................... 9
Table 5. Input Reference Source Jitter Tolerance ................................................................................................................................ 10
Table 6. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 11
Table 7. Amplitude and Frequency values for Jitter Tolerance ............................................................................................................ 12
Table 8. Output Reference Source Selection Table ............................................................................................................................. 13
Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 13
Table 10. Register Map ........................................................................................................................................................................... 18
Table 11. Register Map Description ...................................................................................................................................................... 21
Table 12. Absolute Maximum Ratings ................................................................................................................................................... 35
Table 13. Operating Conditions .............................................................................................................................................................. 35
Table 14. DC Characteristics: TTL Input Pad ......................................................................................................................................... 35
Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up ..................................................................................................... 36
Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down ................................................................................................ 36
Table 17. DC Characteristics: TTL Output Pad ...................................................................................................................................... 36
Table 18. DC Characteristics: PECL Input/Output Pad ....................................................................................................................... 37
Table 19. DC Characteristics: LVDS Input/Output Pad ....................................................................................................................... 38
Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813) .............................................................................. 39
Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) .............................................................................. 40
Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3) .............................................................. 40
Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) ................................................................ 41
Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411) ................................................................... 41
Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) .............................................................................. 42
Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499) ........................................................... 42
Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE) .............................................................. 42
Table 28. Serial Interface Read Access Timing .................................................................................................................................... 45
Table 29. Serial Interface Write Access Timing ................................................................................................................................... 45
Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) ...................................................................................... 47
Table 31. Revision History ...................................................................................................................................................................... 49
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Pin Diagram
Figure 2. ACS8515 Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
IC
AGND
VA1+
INTREQ
REFCLK
DGND
VD+
VD+
DGND
DGND
VD+
SRCSW
VA2+
AGND
IC
FrSync
MFrSync
O1POS
O1NEG
GND_DIFF
VDD_DIFF
SEC1_POS
SEC1_NEG
SEC2_POS
SEC2_NEG
VDD5
Sync2k
SEC1
SEC2
DGND
VDD
1
ACS8515
LC/P
Rev 2.1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SONSDHB
IC
IC
IC
IC
NC
DGND
VDD
O2
NC
VDD
DGND
SDO
IC
IC
IC
PORB
SCLK
VDD
VDD
CSB
SDI
CLKE
IC
DGND
VDD
VDD
IC
VDD
IC
SEC3
IC
NC - Not Connected, IC - Internally Connected
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Pin Descriptions
Table 1. Power Pins
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
8, 9, 12
VD+
P
-
S u p p l y v ol t ag e: Digital sup p ly to gates in analog section,
+3.3 Volts. +/- 10%
22
VDD_DIFF
P
-
S u p p l y v ol t ag e: Digital sup p ly for differential outp ut p ins 19 &
20, +3.3 Volts. +/- 10%
27
VDD5
P
-
V D D 5: Digital sup p ly for +5 Volts tolerance to inp ut p ins. Connect
to +5 volts (+/- 10%) for clamp ing to +5 v. Connect to VDD for
clamp ing to +3.3 v. Leave floating for no clamp ing, inp ut p ins
tolerant up to +5.5 v.
32, 36, 38,
39, 45, 46,
54, 57
VDD
P
-
S u p p l y v ol t ag e: Digital sup p ly to logic, +3.3 Volts. +/- 10%
4
VA1+
P
-
S u p p l y v ol t ag e: Analog sup p ly to clock multip ying APLL, +3.3
Volts. +/- 10%
14
VA2+
P
-
S u p p l y v ol t ag e: Analog sup p ly to outp ut APLL, +3.3 Volts. +/- 10%
7, 10, 11,
31, 40, 53,
58
DGN D
P
-
S u p p l y G r ou n d : Digital ground for logic
21
GN D_DIFF
P
-
S u p p l y G r ou n d : Digital ground for differential outp ut p ins 19 &
20
1, 3, 15
AGN D
P
-
S u p p l y G r ou n d : Analog ground
Table 2. No Connections
PIN
SYM B OL
IO
T YPE
55, 59
NC
-
-
N o t C o n n e ct e d : Leave to Float
2, 16, 33,
35, 60, 61,
62, 63
IC
-
-
I n t e r n al l y C o n n e ct e d : Leave to Float
37
IC
-
-
I n t e r n al l y co n n e ct e d : Leave to Float. Reserved for JTA G control
reset inp ut on next revision
41
IC
-
-
I n t e r n al l y co n n e ct e d : Leave to Float. Reserved for JTA G test mod e
select inp ut on next revision
49
IC
-
-
I n t e r n al l y co n n e ct e d : Leave to Float. Reserved for JTA G
b ound ary scan clock inp ut on next revision
50
IC
-
-
I n t e r n al l y co n n e ct e d : Leave to Float. Reserved for JTA G serial test
d ata outp ut on next revision
51
IC
-
-
I n t e r n al l y co n n e ct e d : Leave to Float. Reserved for JTA G serial test
d ata inp ut on next revision
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N A M E /DE SCR I P T I O N
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ACS8515 Rev2.1 LC/P
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Table 3. Other Pins
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
5
IN T R E Q
O
-
6
REFCLK
I
TTL
R ef er en ce cl ock : 12.8 MHz (refer to section headed Local
Oscillator Clock)
13
SRCSW
I
T T LD
S ou r ce sw i t ch i n g : Force fast source sw itching on SEC1 and SEC2
17
FrSync
O
TTL
O u t p u t r ef er en ce: 8 kHz Frame Sync, 50:50 mark/sp ace ratio
outp ut
18
MFrSync
O
TTL
O u t p u t r ef er en ce: 2 kHz Multi-Frame Sync, 50:50 mark/sp ace
ratio outp ut
19
20
O1POS
O1N EG
O
LVDS/
PECL
O u t p u t r ef er en ce: Programmab le, default 38.88 MHz LVDS
23
24
SEC1_POS
SEC1_N EG
I
LVDS/
PECL
I n p u t r ef er en ce: Programmab le, default 19.44 MHz LVDS
25
26
SEC2_POS
SEC2_N EG
I
PECL/
LVDS
I n p u t r ef er en ce: Programmab le, default 19.44 MHz PECL
28
Sync2k
I
T T LD
M u l t i - Fr am e S y n c 2 k H z : Multi-Frame Sync inp ut
29
SEC1
I
T T LD
I n p u t r ef er en ce: Programmab le, default 8 kHz
30
SEC2
I
T T LD
I n p u t r ef er en ce: Programmab le, default 8 kHz
34
SEC3
I
T T LD
I n p u t r ef er en ce: External standb y reference clock source,
p rogrammab le, default 19.44 MHz
42
CLKE
I
T T LD
S C L K ed g e sel ect : SCLK active edge select, CLKE=1 selects
falling edge of SCLK to b e active, CLKE = 0 for rising edge
43
SDI
I
T T LD
M i cr op r ocessor i n t er f ace ad d r ess: Serial data inp ut
44
CSB
I
T T LU
C h i p sel ect ( act i v e l ow ) : This p in is asser ted Low b y the
microp rocessor to enab le the microp rocessor inter face
47
SCLK
I
T T LD
A d d r ess L at ch E n ab l e: default Serial data clock. When this p in
transitions from low to high, the address b us inp uts are latched
into the internal registers
48
PORB
I
T T LU
P ow er on r eset : Master reset. If PORB is forced Low, all internal
states are reset b ack to default values
I n t er r u p t r eq u est : Softw are Interrup t enab le
Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor
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Table 3 (continued).
PIN
SYM B OL
IO
T YPE
52
SDO
O
T T LD
M i cr o p r o ce sso r i n t e r f ace ad d r e ss: Serial d ata outp ut
56
O2
O
TTL
O u t p u t r e f e r e n ce : 19.44 MHz fixed
T T LD
S O N E T S D H B : SON ET or SDH freq uency select: sets th e initial
p ow er-up state (or state after a PORB) of th e SON ET/SDH
freq uency selection registers, ad d r 34h , b it 2 and ad d r 38, b its 5
and 6. Wh en low SDH rates are selected (2.048 MHz etc) and
w h en set h igh SON ET rates are selected (1.544 MHz etc). Th e
register states can b e ch anged after p ow er up b y softw are.
64
SON SDHB
I
N A M E /DE SCR I P T I O N
Functional Description
The ACS8515 is a highly integrated, single-chip
solution for ‘hit-less’ protection switching of SEC
clocks from Master and Slave SETS clock cards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the
inputs and will implement automatic system
protection switching for Master/Slave SEC clock
failure. The standby SEC clock will be selected
if both the Master and Slave input clocks fail.
The selection of the Master/Slave input can
also be forced by a Force Fast Switch pin.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card - e.g. 8 kHz
distributed on the back plane and 19.44 MHz
generated on the line cards.
The ACS8515 has three SEC clock inputs
(Master, Slave and Standby) and a single MultiFrame Sync input, for synchronising the frame
and multi-frame sync outputs.
The ACS8515 generates two SEC clock outputs
via PECL/LVDS and TTL ports, with spot
frequencies from 1.544/2.048 MHz up to
311.04 MHz. The ACS8515 also provides an
8 kHz Frame Sync and 2 kHz Multi-Frame Sync
output clock.
The ACS8515 has a high tolerance to input
jitter and wander. The jitter/wander transfer is
programmable (0.1 Hz up to 20 Hz cut-off
points).
Revision 1.05/December 2002 ãSemtech Corp.
7
The ACS8515 includes an SPI compatible serial
microprocessor port, providing access to the
configuration and status registers for device
setup.
Local Oscillator Clock
The Master system clock on the ACS8515
requires an external clock oscillator of frequency
12.80 MHz. The exact clock specification is
dependent on the quality of Holdover
performance required in the application.
In most Line Card protection switching
applications where there is a high chance that
at least one SEC reference input will be
available, the long term stability requirement
for Holdover is not appropriate and an
inexpensive crystal local oscillator can be used.
In other applications where there may be a
requirement for longer term Holdover stability
to meet the ITU standards for Stratum 3, a
higher quality oscillator can be used.
Please contact Semtech for information on
crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less
important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
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+/- 50 ppm adjustment would be sufficient to
cope with most crystals, in fact the range is an
order of magnitude larger due to the use of
two 8 bit register locations. The setting of the
conf_nominal_frequency register allows for this
adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm
for each LSB step. The default value (in decimal)
is 39321. The minimum being 0 and the
maximum 65535, giving a -700 ppm to +500
ppm adjustment range of the output
frequencies.
For example, if the crystal was oscillating at
12.8 MHz + 5 ppm, then the calibration value
in the register to give a - 5 ppm adjustment in
output frequencies to compensate for the
crystal inaccuracy, would be :
39321 - (5 / 0.02) = 39071 (decimal)
The TTL ports (compatible also with CMOS
signals) support clock speeds up to 100 MHz,
with the highest spot frequency being 77.76
MHz. Clock speeds above 100 MHz should not
be applied to the TTL ports. The PECL/LVDS
ports support the full range of clock speeds,
up to 155.52 MHz.
The actual spot frequencies supported are:
•2 kHz
•4 kHz
•8 kHz (and N x 8 kHz),
•1.544 MHz (SONET)/2.048 MHz (SDH),
•6.48 MHz,
The ACS8515 supports up to three individual input
reference clock sources via TTL/CMOS and PECL/
LVDS technologies. These interface technologies
support +3.3 V and +5 V operation.
Input Reference Clock Ports
The input reference clock ports are arranged in
groups. Group one comprises a TTL port (SEC1)
and a PECL/LVDS port (SEC1POS and
SEC1NEG). Group two comprises a TTL port
(SEC2) and a PECL/LVDS port (SEC2POS and
SEC2NEG). Group three comprises a TTL port
(SEC3). For group one and group two, only one
of the two input ports types must be active at
any time, the other must not be driven by a
reference input. Unused PECL/LVDS differential
inputs should be fixed with one input high (VDD)
and the other low (GND), or set in LVDS mode
and left floating (in which case one input is
internally pulled high and the other low).
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
Revision 1.05/December 2002 ãSemtech Corp.
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
64). Specific frequencies and priorities are set
by configuration.
8
•19.44 MHz,
•25.92 MHz,
•38.88 MHz,
•51.84 MHz,
•77.76 MHz,
•155.52 MHz.
The frequency selection is programmed via the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg.
19.44 MHz will lock the DPLL phase
comparisons at 19.44 MHz. It is, however,
possible to utilise an internal pre-divider to the
DPLL to divide the input frequency before it is
used for phase comparisons in the DPLL. This
pre-divider can be used in one of 2 ways;
1. Any of the supported spot frequencies can be divided to
8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate
cnfg_ref_source_frequency register location. For good jitter
tolerance for all frequencies and for operation at
19.44 MHz and above, use lock8K. It is possible to choose
which edge of the 8kHz input to lock to, by setting the
appropriate bit of the cnfg_control1 register.
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Table 4. Input Reference Source Selection and Group Allocation
S E C S o u r ce G r o u p
D e f au l t
P ri ori t y
1
1 (4)
2
3 (5)
Up to 155.52MHz (N ote 2)
Default (SON ET/SDH):
19.44MHz
1
2 (6)
Up to 155.52MHz (N ote 2)
Default (SON ET/SDH):
19.44MHz
2
4 (7)
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET/SDH):
3
5 (10)
TTL/CMOS
2kHz Multi Frame Sync
-
-
P o r t N am e
I n p u t P or t
Te c h n o l o g y
SEC1
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET/SDH):
8kHz
SEC2
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET/SDH):
8kHz
SEC1
LVDS/PECL
LVDS default
SEC2
PECL/LVDS
PECL default
SEC3
SYN C1
Fr eq u en ci es S u p p or t ed
19.44MHz
(N ote 3)
Notes for Table 4.
Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency
being 77.76 MHz. The actual spot frequencies are 2 kHz, 4 kHz, 8 kHz, N x 8 kHz, 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz.
Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output
clock frequencies available for SONET and SDH applications.
Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the
ACS8510.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
2. Any multiple of any supported frequency can be
supported by using the "DivN" feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to lock at 8 kHz independently of the
frequencies and configurations of the other inputs.
Any reference input with the ‘DivN’ bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<214-1. The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
Revision 1.05/December 2002 ãSemtech Corp.
9
input frequency. When using the ‘DivN’ feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in cnfg_ref_source_frequency register). Any
input set to DivN must have the frequency
monitors disabled (if the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the ‘DivN’ feature, only one N can be
programmed, hence all inputs using the ‘DivN’
feature must require the same division to get
to 8 kHz.
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PECL and LVDS ports support the spot clock
frequencies listed above plus 155.52 MHz. The
choice of PECL or LVDS compatibility is
programmed via the cnfg_differential_inputs
register.
Unused PECL/LVDS differential inputs should
be fixed with one input high (VDD) and the other
input low (GND), or set in LVDS mode and left
floating, in which case one input is internally
pulled high and the other low.
Input Wander and Jitter Tolerance
The ACS8515 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI DS1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for
each input port in Table 5. Minimum jitter
tolerance masks are specified in Figures 3 and
4, and Tables 6 and 7, respectively. The
ACS8515 will tolerate wander and jitter
components greater than those shown in Figure
3 and Figure 4, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The ‘8klocking’ mode
should be engaged for high jitter tolerance
according to these masks.
All reference clock ports are monitored for
quality, including frequency offset and general
activity. Single short-term interruptions in
selected reference clocks may not cause
rearrangements, whilst longer interruptions, or
multiple, short-term interruptions, will cause
rearrangements, as will frequency offsets which
are sufficiently large or sufficiently long to cause
loss-of-lock in the phase-locked loop. The failed
reference source will be removed from the
priority table and declared as unserviceable,
until its perceived quality has been restored to
an acceptable level.
Table 5. Input Reference Source Jitter Tolerance
J i t t er
To l e r a n c e
Fr eq u en cy M on i t or
A c c e p t an c e R an g e
G.703
G.783
G.823
+/- 16.6 p p m
GR-1244-CORE
Fr eq u en cy
A c c e p t an c e R an g e
( Pull-in)
Fr eq u en cy
A c c e p t an c e
R an g e ( H o l d - i n )
Fr eq u en cy
A c c e p t an c e R an g e
( P u l l - ou t )
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
Notes for Table 5.
Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the
external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.
Note 2. The default acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency
of 12.8 MHz. This range is also programmable from 0 to 80 ppm in 0.08 ppm steps.
Revision 1.05/December 2002 ãSemtech Corp.
10
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The registers sts_curr_inc_offset (address 0C,
0D, 07) report the frequency of the DPLL with
respect to the external TCXO frequency. This is
a 19 bit signed number with one LSB
representing 0.0003 ppm (range of +/- 80
ppm). Reading this regularly can show how the
currently locked source is varying in value e.g.
due to wander on its input.
Output Clock Ports
The ACS8515 supports two SEC output clocks,
on TTL and PECL/LVDS ports, and a pair of
secondary output clocks, ‘Frame-Sync’ and
‘Multi-Frame-Sync’. The two output clocks are
individually controllable. The ‘Frame-Sync’ and
‘Multi-Frame-Sync’ are derived from the main
SEC clock. The frequencies of the output clock
are selectable from a range of pre-defined spot
frequencies, with a variety of output
technologies supported, as defined in Table 8.
The ACS8515 performs automatic frequency
monitoring with an acceptable input frequency
offset range of +/- 16.6 ppm. The ACS8515
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the frequency monitors should be
disabled so the input reference source is not
automatically rejected as out of frequency
range.
Low Speed Output Clock
The O2 SEC clock is supplied on a TTL port with
a fixed frequency of 19.44 MHz.
Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)
(for inputs supporting G.783 compliant sources)
$
$
$
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ORJVFDOH
I
I
I
I
I
I
I
I
I
Table 6. Amplitude and Frequency values for Jitter Tolerance
(for inputs supporting G.783 compliant sources)
ST M
l evel
STM-1
P e ak t o p e ak am p l i t u d e
( u n i t I n t e r v al )
Fr eq u en cy ( H z )
A0
A1
A2
A3
A4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
2800
311
39
1.5
0.15
12u
178u
1.6m
15.6m
0.125
19.3
500
6.5k
65k
1.3m
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11
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Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
(for inputs supporting G.783 compliant sources)
3HDNWRSHDNMLWWHUDQGZDQGHUDPSOLWXGHORJ
VFDOH
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ORJVFDOH
I
I
I
I
Table 7. Amplitude and Frequency values for Jitter Tolerance
(for inputs supporting G.783 compliant sources)
Ty p e
S p ec.
A mp litud e
( U I p k-p k)
Fr e q u e n cy
( Hz )
A1
A2
F1
F2
F3
F4
DS1
G R - 1244- C O R E
5
0.1
10
500
8k
40k
E1
I T U G. 823
1.5
0.2
20
2.4k
18k
100k
High Speed Output Clock
Frame Sync and Multi-Frame Sync Clocks
The O1 SEC clock is supplied on a PECL/LVDS
port with spot frequencies of;
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs FrSync
and MFrSync. The FrSync and MFrSync clocks
have a 50:50 mark/space ratio.
•19.44 MHz,
•38.88 MHz,
Low Jitter Multiple E1/DS1 Outputs
•155.52 MHz,
•311.04 MHz,
•Dig 1.
(where Dig 1 is 1.544 MHz (SONET)/2.048 MHz
(SDH), and multiples of 2, 4 and 8 depending
on SONET/SDH mode setting).
The actual frequency is selectable via the
cnfg_differential_outputs register. The O1 port
can also support 311.04 MHz, which is enabled
via the cnfg_T0_output_enable register. The O1
port can be made LVDS or PECL compatible via
the cnfg_differential_outputs register.
Revision 1.05/December 2002 ãSemtech Corp.
12
This feature added to Rev2.1 is activated using
the cnfg_control1 register. This sends a frequency of twice the Dig2 rate (see reg addr 39h,
bits 7:6) to the APLL instead of the normal
77.76MHz. For this feature to be used, the Dig2
rate must only be set to 12352kHz/16384kHz
using the cnfg_T0_output_frequencies register.
The normal OC3 rate outputs are then replaced
with E1/DS1 multiple rates. The E1(SONET)/
DS1(SDH) selection is made in the same way as
for Dig2 using the cnfg_T0_output_enable register. Table 9 shows the relationship between
primary output frequencies and the corresponding output in E1/DS1 mode, and which output
they are available from.
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ACS8515 Rev2.1 LC/P
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the application and operating state. Wander and
jitter attenuation is performed by using a digital
phase-locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
store is required to prevent data loss. But, since
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
1. The magnitude of wander and jitter on the selected
input reference clock (in locked mode);
2. The internal wander and jitter transfer characteristic
(in Locked mode);
3. The jitter on the local oscillator clock;
4. The wander on the local oscillator clock (in Holdover
mode).
Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
Table 8. Output Reference Source Selection Table
P or t
N am e
O u t p u t P or t
Te c h n o l o g y
O1
LVDS/PECL
LVDS default
O2
TTL/CMOS
19.44 MHz fixed
FrSync
TTL/CMOS
FrSync, 8 kHz. 50:50 mark/sp ace ratio
MFrSync
TTL/CMOS
MFrSync, 2 kHz. 50:50 mark/sp ace ratio
Fr eq u en ci es S u p p or t ed
19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz, Dig1
Dig1 is 1.544 MHz/2.048 MHz and multip les of 2, 4 and 8
Notes for Table 8.
Dig 1 is shown as either 1.544 MHz or 2.048 MHz, where 1.544 MHz is SONET and 2.048 MHz is SDH. Pin SONSDHB controls
the default frequency output. When SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.
Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs
M od e
Default
Fr eq t o
A PLL
A P L L M u l t i p l i er
77.76
4
A PLL
Fr eq
cl k _ f i l t
cl k _
f i l t /2
cl k _
f i l t /4
cl k _
f i l t /6
cl k _
f i l t /8
cl k _
f i l t / 12
cl k _
f i l t / 16
cl k _
f i l t / 48
DP L L
Fr eq
311.04
311.04
155.52
77.76
51.84
38.88
25.92
19.44
6.48
77.76
n value
16
8
4
n x E1
32.768
4
131.072 131.072 65.536 32. 768 21.84533 16. 384 10.92267
8.192
2.730667
77.76
n x T1
24.704
4
98.816
6.176
2.058667
77.76
98.816
49.408
24. 704 16.46933 12. 352 8.234667
Frequencies Availab le b y Outp ut
O1
O1
O1
O2
Revision 1.05/December 2002 ãSemtech Corp.
13
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Figure 5. Wander and Jitter Transfer Measured Characteristics
%
G
Q
L
D *
+]
+]
+]
+]
+]
+]
+]
+]
)UHTXHQF\+]
any buffer store potentially increases latency,
wander may often only need to be removed at
specific points within a network where buffer
stores are acceptable, such as at digital cross
connects. Otherwise, wander is sometimes not
required to be attenuated and can be passed
through transparently. The ACS8515 has
programmable wander transfer characteristics
in a range from 0.1 Hz to 20 Hz. The wander
and jitter transfer characteristic is shown in
Figure 5.
Wander on the local oscillator clock will not
have significant effect on the output clock whilst
in locked mode, so long as the DPLL bandwidth
is set high enough so that the DPLL can
compensate quickly enough for any frequency
changes in the crystal. In Free-run or Holdover
mode wander on the crystal is more significant.
Variation in crystal temperature or supply
voltage both cause drifts in operating frequency,
as does ageing. These effects must be limited
by careful selection of a suitable component
for the local oscillator, as specified in the section
‘Local Oscillator Clock’.
Revision 1.05/December 2002 ãSemtech Corp.
14
Phase Variation
There will be a phase shift across the ACS8515
between the selected input reference source
and the output clock. This phase shift may vary
over time but will be constrained to lie within
specified limits. The phase shift is characterized
using two parameters, MTIE (Maximum Time
Interval Error), and TDEV (Time Deviation), which,
although being specified in all relevent
specifications, differ in acceptable limits in each
one. Typical measurements for the ACS8515
are shown in Figures 6 and 7, for locked mode
operation. Figure 8 shows a typical
measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation
during Holdover is specified in several ways
depending upon the particular circumstances
pertaining:
1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to Holdover
to Locked) be limited to an accumulation rate no greater
than 0.05 ppm during a 15 second interval.
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Figure 6. Maximum Time Interval Error of T OUT0 Output Port
1 00
G .8 1 3 o p tion 1 , co n sta n t te m p e rature w an de r lim it
T im e
(n s)
10
1
M T IE m e a su re m e n t o n 1 5 5 M H z o u tp u t, 1 9.44 M H z i/p (8 kH z lo ckin g),
V e c tro n 6 6 6 4 x tal
0 .1
0 .0 1
0 .01
1
0.1
10
100
1000
10000
O b s erv a tio n in terva l (s)
Figure 7. Time Deviation of T OUT0 Output Port
10
G .813 op tio n 1 con stan t tem perature w ander lim it
T im e
(ns )
1
0.1
T D E V m ea su rem e nt on 1 55 M H z output, 1 9.4 4 M H z i/p (8kH z lock ing),
V ectron 6 664 xtal
0 .01
0.01
0 .1
1
10
100
10 00
10 000
O b s erv ation in terv al (s)
Figure 8. Phase Error Accumulation of T OUT0 Output Port in Holdover Mode
10000000
Phase Error (ns)
1000000
P e rm itte d P h a s e E rro r L im it
100000
10000
1000
100
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T y p ic a l m e a s u re m e n t, 2 5 °C c o n s ta n t te m p e ra tu re
10000
1000
15
100000
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2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not exceed
{(a1+a2)S+0.5bS2+c}
where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10-4 ns/s2 (allowance for ageing)
c = 120 ns (allowance for entry into Holdover mode).
3. ANSI Tin1.101-1994, Section 8.2.2, requires that the
phase variation be limited so that no more than 255 slips
(of 125 µs each) occur during the first day of Holdover.
This requires a frequency accuracy better than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm
Temperature variation is not restricted, except to within
the normal bounds of 0 to 50 Celsius.
4. Bellcore GR.1244.CORE, Section 5.2., Table 4, shows
that an initial frequency offset of 50 ppb is permitted on
entering Holdover, whilst a drift over temperature of 280
ppb is allowed; an allowance of 40 ppb is permitted for all
other effects.
5. ITU G.822, Section 2.6, requires that the slip rate during
category(b) operation (interpreted as being applicable to
Holdover mode operation) be limited to less than 30 slips
(of 125 µs each) per hour
((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm
on the output will still be less than the 120 ns
allowed for in the G.813 spec.
The actual
value is dependant on the frequency being
locked to.
The PBO requirement, as specified in Telcordia
GR1244-CORE, Section 5.7, in that a phase
transient of greater than 3.5 µs occuring in
less than 0.1 seconds should be absorbed, will
be implemented on a future version. ITU-T
G.813 states that the max allowable short term
phase transient response, resulting from a
switch from one clock source to another, with
Holdover mode entered in between, should be
a maximum of 1 µs over a 15 second interval.
The maximum phase transient or jump should
be less than 120 ns at a rate of change of less
than 7.5 ppm and the Holdover performance
should be better than 0.05 ppm.
On the ACS8515, PBO can be enabled, disabled
or frozen using the µP interface. By default, it
is enabled. When PBO is enabled, it can also
be frozen, which will disable the PBO operation
on the next input reference switch, but will
remain with the current offset. If PBO is
disabled while the device is in the Locked mode,
there will be a phase jump on the output SEC
clocks as the DPLL locks back to 0 degree
phase error.
Phase Build Out
Microprocessor Interface
Phase Build Out (PBO) is the function to minimise
phase transients on the output SEC clock during
input reference switching or mode switching. If
the currently selected input reference clock
source is lost (due to a short interruption, out
of frequency detection, or complete loss of
reference), the second, next highest priority
reference source will be selected. During this
transition, the Lost_Phase mode is entered.
The ACS8515 incorporates a serial
microprocessor interface that is compatible with
the Serial Peripheral Interface (SPI) for device
setup.
The typical phase disturbance on clock
reference source switching will be less than
10 ns on the ACS8515. For clock reference
switching caused by the main input failing or
being disconnected, then the phase disturbance
Revision 1.05/December 2002 ãSemtech Corp.
16
Register Set
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit-significance decreasing towards the
right-most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g., flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map.
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Configuration Registers
Interrupt Enable and Clear
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pinsettable. All configuration registers can be read
out over the microprocessor port.
Interrupt requests are flagged on pin INTREQ
(active High).
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the chip_revision register.
Configuration registers may be written to or read
from at any time (the complete 8-bit register
must be written, even if only one bit is being
modified). All status registers may be read at
any time and, in some status registers (such as
the sts_interrupts register), any individual data
field may be cleared by writing a ‘1’ into each
bit of the field (writing a ‘0’ value into a bit will
not affect the value of the bit). Details of each
register are given in the Register Map and
Register Map Description sections.
Revision 1.05/December 2002 ãSemtech Corp.
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Bits in the interrupt status register are set (high)
by the following conditions;
1. Any reference source becoming valid or going invalid
2. A change in the operating state (eg. Locked, Holdover
etc.)
3. A brief loss of the currently selected reference source
All interrupt sources are maskable via the mask
register cnfg_interrupt_mask, each one being
enabled by writing a '1' to the appropriate bit.
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependent
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
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Register Map
Shaded areas in the map are ‘don’t care’ and writing either 0 or 1 will not affect any function of
the device.
Bits labelled ‘Set to 0’ or ‘Set to 1’ must be set as stated during initialisation of the device,
either following power up, or after a power on reset (PORB). Failure to correctly set these bits
may result in the device operating in an unexpected way.
Some registers do not appear in this list, for example 07 and 08. These are either not used, or
have test functionality. Do not write to any undefined registers as this may cause the device to
operate in a test mode. If an undefined register has been inadvertently addressed, the device
should be reset to ensure the undefined registers are at default values.
Table 10. Register Map
A d d r. P ar am e t e r N am e
( Hex )
D at a B i t
7 ( m sb )
02
ch ip _revision
(read only)
03
cnfg_control1
(read /w rite)
04
cnfg_control2
(read /w rite)
05
sts_interrup ts
(read /w rite)
09
0A
4
A nalog
d iv sync
Set to '0'
3
Set to '0'
Ph ase loss flag limit
SEC2DIFF
1
0 ( l sb )
8k Ed ge
Polarity
Set to '0'
Set to '0'
Set to '0'
Set to '1'
Set to '0'
SEC1DIFF
SEC2
SEC1
Main ref
failed
SEC3
Op erating mod e (2:0)
sts_p riority_tab le
(read only)
High est p riority valid source
Currently selected reference source
3rd h igh est p riority valid source
2nd h igh est p riority valid source
sts_curr_inc_offset
(read only)
Current increment offset (7:0)
0D
Current increment offset (15:8)
Current increment offset (18:16)
07
0E
2
sts_op erating_mod e
(read only)
0B
0C
5
Ch ip revision numb er (7:0)
Op erating
mod e
06
6
sts_sources_valid
(read only)
SEC2DIFF
SEC1DIFF
SEC2
SEC1
0F
11
SEC3
sts_reference_sources
(read /w rite)
12
status <SEC2>
status <SEC1>
status <SEC2DIFF>
status <SEC1 DIFF>
status <SEC3>
14
18
cnfg_ref_selection_p riority
(read /w rite)
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
19
p rogrammed _p riority <SEC2>
p rogrammed _p riority <SEC1>
1A
p rogrammed _p riority <SEC2DIFF>
p rogrammed _p riority <SEC1DIFF>
Revision 1.05/December 2002 ãSemtech Corp.
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Set to '0'
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Table 10. Register Map (continued).
A d d r. P ar am e t e r N am e
( Hex )
D at a B i t
7 ( m sb )
6
5
4
3
2
1
0 ( l sb )
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1D
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1E
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
d ivn
lock8k
b ucket_id <SEC1> (1:0)
reference_source_freq uency <SEC1> (3:0)
23
d ivn
lock8k
b ucket_id <SEC2> (1:0)
reference_source_freq uency <SEC2> (3:0)
24
d ivn
lock8k
b ucket_id
<SEC1DIFF> (1:0)
reference_source_freq uency <SEC1DIFF> (3:0)
25
d ivn
lock8k
b ucket_id
<SEC2DIFF> (1:0)
reference_source_freq uency <SEC2DIFF> (3:0)
28
d ivn
lock8k
b ucket_id <SEC3> (1:0)
reference_source_freq uency <SEC3> (3:0)
1B
1C
22
cnfg_ref_selection_p riority
(read /w rite)
(continued )
cnfg_ref_source_freq uency
(read /w rite)
32
cnfg_op erating_mod e
(read /w rite)
33
cnfg_ref_selection
(read /w rite)
34
cnfg_mod e
(read /w rite)
35
cnfg_control3
(read /w rite)
36
cnfg_d ifferential_inp uts
(read /w rite)
38
cnfg_outp ut_enab le
(read /w rite)
39
cnfg_O1_outp ut_freq uencies
(read /w rite)
3A
cnfg_d ifferential_outp ut
(read /w rite)
3B
3C
3D
40
41
cnfg_b and w id th
(read /w rite)
Forced op erating mod e
force_select_reference_source
A u to
external
2k enab le
311.04
MHz on O1
Ph ase
alarm
timeout
enab le
Clock
ed ge
Set to '0'
Set to '1'
Set to '0'
1=SON ET
0=SDH
for Dig1
Set to '0'
External 2k
Sync enab le
Rever tive
mod e
SON ET/
SDH I/P
SEC2DIFF
PECL
SEC1DIFF
PECL
Set to '0'
O2 enab le
Set to '0'
Set to '0'
Set to '0'
Set to '0'
O1 LV DS
enab le
O1 PECL
enab le
Digital 1
O1 freq uency selection
A uto b /w
sw itch
acq /lock
A cq uisition b and w id th
cnfg_nominal_freq uency
(read /w rite)
cnfg_h old over_offset
(read /w rite)
p rogrammed _p riority <SEC3>
Set to '0'
N ormal/locked b and w id th
N ominal freq uency (7:0)
N ominal freq uency (15:8)
Set to '0'
cnfg_freq _limit
(read /w rite)
DPLL Freq uency offset limit (7:0)
DPLL Freq uency offset
limit (9:8)
42
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19
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Table 10. Register Map (continued).
A d d r. P ar am et er N am e
( Hex )
43
cnfg_interrup t_mask
(read/w rite)
44
D at a B i t
7 ( m sb )
6
5
4
3
2
1
0 ( l sb )
Set to '0'
Set to '0'
status
SEC2DIFF
status
SEC1DIFF
status
SEC2
status
SEC1
Set to '0'
Set to '0'
Op er. mode
Main ref
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
status
SEC3
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
45
46
cnfg_freq_divn
(read/w rite)
Divide-inp ut-b y-n ratio (7:0)
Divide-inp ut-b y-n ratio (13:8)
47
48
cnfg_monitors
(read/w rite)
Ultra-fast
sw itching
External
source
sw itch
enab le
Freeze
p hase
b uildout
Phase
b uildout
enab le
50
cnfg_activ_up p er_threshold 0
(read/w rite)
Configuration 0: Activity alarm set threshold (7:0)
51
cnfg_activ_low er_threshold 0
(read/w rite)
Configuration 0: Activity alarm reset threshold (7:0)
52
cnfg_b ucket_size 0
(read/w rite)
53
cnfg_decay_rate 0
(read/w rite)
54
cnfg_activ_up p er_threshold 1
(read/w rite)
Configuration 1: Activity alarm set threshold (7:0)
55
cnfg_activ_low er_threshold 1
(read/w rite)
Configuration 1: Activity alarm reset threshold (7:0)
56
cnfg_b ucket_size 1
(read/w rite)
57
cnfg_decay_rate 1
(read/w rite)
58
cnfg_activ_up p er_threshold 2
(read/w rite)
Configuration 2: Activity alarm set threshold (7:0)
59
cnfg_activ_low er_threshold 2
(read/w rite)
Configuration 2: Activity alarm reset threshold (7:0)
5A
cnfg_b ucket_size 2
(read/w rite)
5B
cnfg_decay_rate 2
(read/w rite)
5C
cnfg_activ_up p er_threshold 3
(read/w rite)
Configuration 3: Activity alarm set threshold (7:0)
5D
cnfg_activ_low er_threshold 3
(read/w rite)
Configuration 3: Activity alarm reset threshold (7:0)
5E
cnfg_b ucket_size 3
(read/w rite)
5F
cnfg_decay_rate 3
(read/w rite)
Revision 1.05/December 2002 ãSemtech Corp.
Frequency monitors
configuration (1:0)
Configuration 0: Activity alarm b ucket size (7:0)
Configuration 0:
decay_rate (1:0)
Configuration 1: Activity alarm b ucket size (7:0)
Configuration 1:
decay_rate (1:0)
Configuration 2: Activity alarm b ucket size (7:0)
Configuration 2:
decay_rate (1:0)
Configuration 3: Activity alarm b ucket size (7:0)
Configuration 3:
decay_rate (1:0)
20
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Register Map Description
Table 11. Register Map Description
A d d r. P ar am e t e r N am e
( Hex )
02
D e scr i p t i o n
ch ip _revision
Th is read -only register contains th e ch ip revision numb er
Th is revision = 1
Last revision (engineering samp les) = 0
cnfg_control1
Bi ts (7:6)
D e f au l t
Val u e ( b i n )
00000001
Unused
Bit 5
=1 32/24MHz to APLL: Feeds 2x D i g2 frequency to the APLL i nstead of the normal 77.76Mhz.
Thus the normal OC 3/STM1 outputs are replaced wi th multi ple E1/T1 rates. Note: D i g2 set bi ts
(Reg. 39h Bi ts (7:6)) must be set to 11 for thi s mode.
=0 77.76MHz to APLL
Bit 4
=1 Synchroni zes the di vi ders i n the output APLL secti on to the di vi ders i n the D PLL secti on
such that thei r phases ali gn. Thi s i s necessary i n order to have phase ali gnment between i nputs
and output clocks at OC 3 deri ved rates (6.48 MHz to 77.76 MHz). Keepi ng thi s bi t hi gh may be
necessary to avoi d the di vi ders getti ng out of synchroni zati on when qui ck changes i n frequency
occur such as a force i nto Free-Run.
=0 The di vi ders may get out of phase followi ng step changes i n frequency, but i n thi s mode the
correct number of hi gh frequency edges i s guarenteed wi thi n any synchroni zati on peri od. The
output wi ll frequency lock (default).
The devi ce wi ll always remai n i n synchroni zati on 2 seconds from a reset, before the default
setti ng appli es.
03
Bi ts 3
X X 000000
Test control - leave unchanged, or set to '0'
Bit 2
=1 When i n 8k locki ng mode the system wi ll lock to the ri si ng i nput clock edge.
=0 When i n 8k locki ng mode the system wi ll lock to the falli ng i nput clock edge.
04
cnfg_control2
Bi ts (1:0)
Test controls - leave unchanged, or set to '00'
Bits (7:6)
Unused.
XX100010
Bits (5:3) d efine th e p h ase loss flag limit. By d efault set to 4 (100) w h ich corresp ond s to
ap p roximately 140°. A low er value sets a corresp ond ing low er p h ase limit. Th e flag limit
d etermines th e value at w h ich th e DPLL ind icates p h ase lost as a result of inp ut jitter, a p h ase
jump , or a freq uency jump on th e inp ut.
Bits (2:0)
sts_interrup ts
Test controls - leave unch anged or set to '010'.
Th is register contains one b it for each b it of sts_sources_valid , one for loss of reference th e
d evice w as locked to, and anoth er for th e op erating mod e. A ll b its are active h igh .
A ll b its excep t th e 'main ref failed ' b it (b it 14) are set on a 'ch ange' in th e state of th e relevent
status b it, i.e. if a source b ecomes valid , or goes invalid it w ill trigger an interrup t. If th e
Op erating Mod e (register 9) ch anges state th e interrup t w ill b e generated .
Bit 14 (main ref failed ) of th e interrup t status register is used to flag inactivity on th e reference
th at th e d evice is locked to much more q uickly th an th e activity monitors can sup p or t. If b it 6 of
th e cnfg_monitors register (register 48) (flag ref loss on TDO) is set, th en th e state of th is b it is
d riven onto th e TDO p in of th e d evice.
A ll b its are maskab le b y th e b its in th e cnfg_interrup t_mask register. Each b it may b e cleared
ind ivid ually b y w riting a '1' to th at b it, th us resetting th e interrup t. A ny numb er of b its can b e
cleared w ith a single w rite op eration. Writing '0's w ill h ave no effect.
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Table 11. Register Map Description (continued).
A d d r. P ar am et er N am e
( Hex )
05
sts_interrup ts
(continued)
06
09
sts_op erating_mode
sts_p riority_tab le
D e scr i p t i o n
Bits (7:6)
Unused
B it 5
SEC2DIFF (sts_interrup ts b it 5)
B it 4
SEC1DIFF (sts_interrup ts b it 4)
B it 3
SEC2 (sts_interrup ts b it 3)
B it 2
SEC1 (sts_interrup ts b it 2)
Bits (1:0)
Unused
B i ts 7
Op erating mode (sts_interrup ts b it 15)
B it 6
Main ref failed (sts_interrup ts b it 14)
Bits (5:1)
Unused
B it 0
SEC 3 (sts_interrup ts b it 8)
D e f au l t
Val u e ( b i n )
XX0000XX
00XXXXX0
This read-only register holds the current op erating state of the main state machine. Figure 10
show how the values of the 'op erating state' variab le match w ith the individual states.
Bits (7:3)
Unused
Bits (2:0)
001
010
100
110
101
111
State
Freerun (default)
Holdover
Locked
Pre-locked
Pre-locked2
Phase lost
XXXXX001
This is a 16-b it read-only register.
Bits (15:12) Third-highest p riority valid source: this is the channel numb er of the inp ut reference
source w hich is valid and has the next-highest p riority to the second-highest-p riority valid source.
Bits (11:8) Second-highest p riority valid source: this is the channel numb er of the inp ut reference
source w hich is valid and has the next-highest p riority to the highest-p riority valid source.
Bits (7:4) Highest-p riority valid source: this is the channel numb er of the inp ut reference source
w hich is valid and has the highest p riority; it may not b e the same as the currently-selected
reference source (due to failure history or changes in p rogrammed p riority).
Bits (3:0) Currently-selected reference source: this is the channel numb er of the inp ut reference
source w hich is currently inp ut to the DPLL.
N ote that these registers are up dated b y the state machine in resp onse to the contents of the
cnfg_ref_selection_p riority register and the ongoing status of individual channels; channel
numb er '0000', ap p earing in any of these registers, indicates that no channel is availab le for that
p riority.
0A
Bits (7:4)
Bits (3:0)
Highest-p riority valid source (sts_p riority_tab le b its (7:4))
Currently selected reference source (sts_p riority_tab le b its (3:0))
00000000
0B
Bits (7:4)
Bits (3:0)
3rd-highest-p riority valid source (sts_p riority_tab le b its (15:12))
2nd-highest-p riority valid source (sts_p riority_tab le b its (11:8))
00000000
sts_curr_inc_offset
This read-only register contains a signed-integer value rep resenting the 19 significant b its of the
current increment offset of the digital PLL. The register may b e read p eriodically to b uild up a
historical datab ase for later use during holdover p eriods (this w ould only b e necessary if an
external oscillator w hich did not meet the stab ility criteria describ ed in Local Oscillator Clock
section is used). The register w ill read 00000000 immediately after reset.
0C
Bits (7:0)
sts_curr_inc_offset b its (7:0)
00000000
0D
Bits (7:0)
sts_curr_inc_offset b its (15:8)
00000000
07
Bits (7:3)
Unused
Bits (2:0)
sts_curr_inc_offset b its (18:16)
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Table 11. Register Map Description (continued).
A d d r. P ar am et er N am e
( Hex )
sts_sources_valid
0E
0F
sts_reference_sources
D e scr i p t i o n
This register contains a b it to show validity for every reference source.
=1 Valid source
=0 Invalid source (default)
Bits (7:6)
Unused
B it 5
SEC2DIFF
B it 4
SEC1DIFF
B it 3
SEC2
B it 2
SEC1
Bits (1:0)
Unused
Bits (7:1)
Unused
B it 0
SEC3
12
14
cnfg_ref_selection_p riority
XX0000XX
XXXXXXX0
This register holds the status of each of the inp ut reference sources. The status of each reference
source is show n in a 4-b it field. Each b it is active high. To aid status checking, a cop y of each
status b it 3 is p rovided in the sts_sources_valid register. The status is rep or ted as follow s: (Each
b it may b e cleared individually)
Status b it
Status b it
Status b it
Status b it
11
D e f au l t
Val u e ( b i n )
3 = Source valid (no alarms) (b it 3 is comb ination of b its 0-2) (default 0)
2 = Out-of-b and alarm (default 1)
1 = N o activity alarm (default 1)
0 = Phase lock alarm (default 0)
Bits (7:4)
Status of inp ut reference source SEC2
Bits (3:0)
Status of inp ut reference source SEC1
Bits (7:4)
Status of inp ut reference source SEC2DIFF
Bits (3:0)
Status of inp ut reference source SEC1DIFF
Bits (7:4)
Unused
Bits (3:0)
Status of inp ut reference source SEC3
01100110
01100110
XXXX0110
This register holds the p riority of each of the inp ut reference sources. The p riority values are all
relative to each other, w ith low er-valued numb ers taking higher p riorities. Only the values 1 to
15 (dec) are valid - '0' disab les the reference source. Each reference source must b e given a
unique p riority, how ever tw o sources given the same p riority numb er w ill b e assigned on a first in
first out b asis.
It is recommended to reserve the p riority value '1' as this is used w hen forcing reference selection
via the cnfg_ref_selection register. If the user does not intend to use the cnfg_ref_selection
register then p riority value '1' need not b e reserved.
18
Bits (7:0)
Must b e set to '00000000' during initialisation
Bits (7:4)
Programmed p riority of inp ut reference source SEC2
Bits (3:0)
Programmed p riority of inp ut reference source SEC1
Bits (7:4)
Programmed p riority of inp ut reference source SEC2DIFF
Bits (3:0)
Programmed p riority of inp ut reference source SEC1DIFF
Bits (7:0)
Must b e set to '00000000' during initialisation
Bits (7:4)
Must b e set to '0000' during initialisation
Bits (3:0)
Programmed p riority of inp ut reference source SEC3
1D
Bits (7:0)
Must b e set to '00000000' during initialisation
11010001
1E
Bits (7:0)
Must b e set to '00000000' during initialisation
11111110
19
1A
1B
1C
Revision 1.05/December 2002 ãSemtech Corp.
23
00110010
01010100
01110110
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Table 11. Register Map Description (continued).
A d d r. P ar am et er N am e
( Hex )
cnfg_ref_source_frequency
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
This register is used to set up each of the inp ut reference sources.
Bits (7:6) of each b yte define the op eration under taken on the inp ut frequency, in accordance
w ith the follow ing key:
00
01
10
11
The inp ut frequency is fed directly into the DPLL (default).
The inp ut frequency is internally divided dow n to 8 kHz, b efore b eing fed into the
DPLL. (For high jitter tolerance).
Unsup p or ted configuration - do not use
Uses the division coefficient stored in registers 46 & 47 (cnfg_freq_divn) to divide
the inp ut b y this value p rior to b eing fed into the DPLL. The frequency monitors
must b e disab led. The divided dow n frequency should equal 8 kHz. The frequency
(3:0) should b e set to the nearest sp ot frequency just b elow the actual inp ut
frequency. The DivN feature w orks for inp ut frequencies b etw een 1.544 MHz and
100 MHz.
Bits (5:4) together define w hich leaky b ucket settings (0-3) are used, as defined in registers 50
to 5F. (default 00).
Bits (3:0) define the frequency of the reference source in accordance w ith the follow ing key:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
8 kHz (default SEC1, SEC2)
1544 kHz(SON ET)/2048 kHz(SDH) (As defined b y Register 34, b it 2)
6.48 MHz
19.44 MHz (default SEC1DIFF, SEC2DIFF, SEC3)
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
2 kHz
4 kHz
22
Frequency of reference source SEC1
00000000
23
Frequency of reference source SEC2
00000000
24
Frequency of reference source SEC1DIFF
00000011
25
Frequency of reference source SEC2DIFF
00000011
28
Frequency of reference source SEC3
00000011
cnfg_op erating_mode
32
cnfg_ref_selection
This register is used to force the device into a desired op erating state, rep resented b y the b inary
values show n in Figure 10. Value 0 (hex) allow s the control state machine to op erate
automatically.
Bits (7:3)
Unused
Bits (2:0)
Desired op erating state (as p er Figure 10)
This register is used to force the device to select a p ar ticular inp ut reference source, irresp ective
of its p riority. Writing to this register temp orarily raises the selected inp ut to p riority '1'. Provided
no other inp ut is already p rogrammed w ith p riority '1', and rever tive mode is on, this source w ill
b e selected.
Bits (7:4)
33
XXXXX000
Unused
Bits (3:0)
0000
Automatic selection
0011
SEC1
0100
SEC2
0101
SEC1DIFF
0110
SEC2DIFF
1001
SEC3
1111
Automatic selection (default)
Other values should not b e used.
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Table 11. Register Map Description (continued).
A d d r. P ar am e t e r N am e
( Hex )
cnfg_mod e
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
Th is register contains several ind ivid ual configuration field s, as d etailed b elow :
B it 7
=1 A uto 2 kHz Sync Enab le: External 2 kHz Sync w ill b e enab led only w h en th e source is locked
to 6.48 MHz. Oth erw ise it w ill b e d isab led . (d efault).
=0 A uto 2 kHz Sync Disab le: Th e user controls th is function using b it 3 of th is register, as
d escrib ed b elow.
B it 6
=1 Ph ase A larm Timeout enab le: Th e p h ase alarm w ill timeout after 100 second s. (d efault).
=0 Ph ase A larm Timeout d isab le: Th e p h ase alarm w ill not timeout and must b e reset b y
softw are.
B it 5
=1 Rising Clock Ed ge selected : Th e d evice w ill reference to th e rising ed ge of th e external
oscillator signal.
=0 Falling Clock Ed ge selected : Th e d evice w ill reference to th e falling ed ge of th e external
oscillator signal (d efault).
B it 4
34
Unused . Must b e set to '0' d uring initialisation.
B it 3
=1 External 2 kHz Sync Enab le: Th e d evice w ill align th e p h ase of its internally generated
Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) w ith th at of th e signal sup p lied
to th e Sync2k p in. Th is inp ut sh ould b e from th e 2 kHz Multi-Frame Sync of an A CS8510.
=0 External 2 kHz Sync Disab le: Th e d evice w ill ignore th e Sync2k p in (d efault).
110X00X0
(SON SDHB=0)
110X01X0
(SON SDHB=1)
B it 2
=1 SON ET mod e: Th e d evice exp ects th e inp ut freq uency of any inp ut ch annel given th e value
'0001' in th e cnfg_ref_source_freq uency register to b e 1544 kHz.
=0 SDH mod e: Th e d evice exp ects th e inp ut freq uency of any inp ut ch annel given th e value
'0001' in th e cnfg_ref_source_freq uency register to b e 2048 kHz.
A t star t up or reset th e b it value w ill b e d efaulted to th e setting of p in SON SDHB. Th is setting
can sub seq uently b e altered b y ch anging th is b it value.
B it 1
Unused
B it 0
= 1 Rever tive Mod e: Th e d evice w ill sw itch to th e h igh est p riority source sh ow n in
sts_p riority_tab le register, b its (7:4).
= 0 N on-rever tive Mod e: Th e d evice w ill retain th e p resently selected source (d efault).
cnfg_control3
35
cnfg_d ifferential_inp uts
36
Bits (7:6)
Unused
Bits (5:4)
Must b e set to '10' d uring initialisation.
Bits (3:0)
Unused
XX00XXXX
Th is register contains tw o ind ivid ual configuration field s
Bits (7:2)
Unused
B it 1
=1
=0
Inp ut SEC2DIFF is PECL comp atib le (d efault)
Inp ut SEC2DIFF is LV DS comp atib le
B it 0
=1
=0
Inp ut SEC1DIFF is PECL comp atib le
Inp ut SEC1DIFF is LV DS comp atib le (d efault)
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Table 11. Register Map Description (continued).
A d d r. P ar am e t e r N am e
( Hex )
38
cnfg_outp ut_enab le
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
Th is register contains several ind ivid ual configuration field s, as follow s:
B it 7
=1
=0
O1 outp ut freq uency set to 311.04 MHz
O1 outp ut freq uency set b y A d d ress 3A (5:4) (d efault)
B it 6
Unused . Must b e set to '0' d uring initialisation.
B it 5
=1
=0
0X0XX1XX
SON ET mod e selected for Dig1
SDH mod e selected for Dig1 (d efault)
- see register cnfg_O1_outp ut_freq uencies
Bits (4:3)
Unused . Must b e set to '0' d uring initialisation.
B it 2
=1
=0
Outp ut p or t O2 enab led (19.44 MHz) (d efault)
Outp ut p or t O2 d isab led
Bits (1:0)
Unused . Must b e set to '0' d uring initialisation.
N ote: "Disab led " means th e outp ut p or t h old s a static logic value (th e p or t is not Tri-stated ).
39
cnfg_O1_outp ut_freq uencies
Th is register h old s th e freq uency selections for each outp ut p or t, as d etailed b elow.
Bits (7:6)
Unused
Bits (5:4)
00
01
10
11
Dig1
1544 kHz/2048 kHz (d efault)
3088 kHz/4096 kHz
6176 kHz/8192 kHz
12352 kHz/16384 kHz
Bits (3:2)
Unused
Bits (1:0)
Unused
XX00XXXX
For Dig1 th e freq uency values are sh ow n for SON ET/SDH. Th ey are selected via th e SON ET/SDH
b its in register cnfg_outp ut_enab le.
3A
3B
cnfg_d ifferential_outp ut
cnfg_b and w id th
Th is register h old s th e freq uency selections and th e p or t-tech nology typ e for th e d ifferential
outp ut O1, as d etailed b elow.
Bits (7:6)
Unused
Bits (3:2)
Unused
Bits (5:4)
00
01
10
11
O1
38.88 MHz (d efault)
19.44 MHz
155.52 MHz
Dig1
Bits (1:0)
00
01
10
11
O1
Por t d isab led
PECL-comp atib le
LV DS-comp atib le (d efault)
Unused
XX00XX10
Th is register contains information used to control th e op eration of th e d igital PLL. Wh en
b and w id th selection is set to automatic, th e DPLL w ill use th e acq uisition b and w id th setting
w h en out of lock, and th e normal/locked b and w id th setting w h en in lock. Wh en set to manual,
th e DPLL w ill alw ay use th e normal/locked b and w id th setting.
B it 7
=1
=0
A utomatic op eration
Manual op eration (d efault)
Bits (6:4)
000
001
010
011
100
101
110
111
A cq uisition b and w id th
0.1 Hz
0.3 Hz
0.5Hz
1.0 Hz
2.0 Hz
4.0 Hz
8.0 Hz
17 Hz (d efault)
B it 3
Unused
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26
Bit (2:0)
000
001
010
011
100
101
110
111
0111X101
Loop b and w id th
0.1 Hz
0.3 Hz
0.5 Hz
1.0 Hz
2.0 Hz
4.0 Hz (d efault)
8.0 Hz
17 Hz
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Table 11. Register Map Description (continued).
A d d r. P ar am e t e r N am e
( Hex )
cnfg_nomi nal_frequency
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
Thi s regi ster holds a 16 bi t unsi gned i nteger allowi ng compensati on for offset of the crystal
osci llator from the nomi nal 12.8 MHz. See secti on C rystal Frequency C ali brati on. D efault
results i n 0 ppm adjustment.
3C
Bi ts (7:0)
cnfg_nomi nal_frequency bi ts (7:0)
10011001
3D
Bi ts (7:0)
cnfg_nomi nal_frequency bi ts (15:8)
10011001
cnfg_h old over_offset
Th is register h old s 1 b it w h ich must b e set to '0' d uring initialization.
B it 7
40
Bits (6:0)
cnfg_freq _limit
Must b e set to '0' d uring initialization
1XXXXXXX
Unused
Th is register h old s a 10 b it unsigned integer rep resenting th e p ull-in range of th e DPLL. It
sh ould b e set accord ing to th e accuracy of crystal imp lemented in th e ap p lication, using th e
follow ing formula;
Freq uency range +/- (p p m) = (cnfg_freq _limit x 0.0785)+0.01647 or
cnfg_freq _limit = (Freq uency range +/- (p p m) - 0.01647) / 0.0785
Default value w h en SRCSW is left unconnected or tied low is ±9.3 p p m. Default value w h en
SRCSW is h igh is th e full range of around ±80 p p m.
41
42
cnfg_interrup t_mask
Bits (7:0)
cnfg_freq _limit b its (7:0)
Bits (7:2)
Unused
Bits (1:0)
cnfg_freq _limits b its (9:8)
01110110
(SRCSW low )
11111111
(SRCSW h igh )
XXXXXX00
(SRCSW low )
XXXXXX11
(SRCSW h igh )
Each b it, if set '0' w ill d isab le th e ap p rop riate interrup t source in th e interrup t status register.
Bit (7:6) Must b e set to '00' d uring initialisation
43
B it 5
Status SEC2DIFF
B it 4
Status SEC1DIFF
B it 3
Status SEC2
B it 2
Status SEC1
11111111
Bit (1:0) Must b e set to '00' d uring initialisation
44
B it 7
Op er. mod e
B it 6
Main ref
11111111
Bit (5:1) Must b e set to '00000' d uring initialisation
B it 0
Interrup t source
Bit (7:5) Unused
45
XXX11111
Bit (4:0) Must b e set to '00000' d uring initialisation
cnfg_freq _d ivn
Th is 14 b it integer is used as th e d ivisor for any inp ut to get th e p h ase locking freq uency
d esired . Only active for inp uts w ith th e DivN b it set to ‘1’. Th is w ill cause th e inp ut freq uency
to b e d ivid ed b y (n+1) p rior to p h ase comp arison, e.g. p rogram N to:
((inp ut freq )/8kHz)-1
Th e reference_source_freq uency b its sh ould b e set to reflect th e closest sp ot freq uency to th e
inp ut freq uency, b ut must b e low er th an th e inp ut freq uency.
46
47
Bits (7:0)
cnfg_freq _d ivn b its (7:0)
Bits (7:6)
Unused
Bits (5:0)
cnfg_freq _d ivn b its (13:8)
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27
00000000
XX000000
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Table 11. Register Map Description (continued).
A d d r. P ar am e t e r N am e
( Hex )
cnfg_monitors
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
Th is register allow s glob al configuration of monitors and control of p h ase b uild out.
Bit 7 Unused
Bit 6 Unused
B it 5
=1 Enab les ultra fast sw itch ing: A llow s th e DPLL to raise an activity alarm on th e currently
selected source after missing only a few cycles. See section on Ultra Fast Sw itch ing.
=0 N ormal op eration (d efault)
B it 4
=1 Forces locking to SEC1 (p in 29) if p in SRCSW h igh , or SEC2 (p in 30) if p in SRCSW low
=0 Pin SRCSW ignored , and automatic control enab led
48
B it 3
=1 Will freeze th e outp ut p h ase relationsh ip w ith th e current inp ut to outp ut p h ase offset
=0 A llow s ch anges in inp ut to outp ut p h ase offset to take p lace (N ormal p h ase b uild out mod e)
(d efault)
X0000101
(SRCSW low )
X0010101
(SRCSW h igh )
B it 2
=1 Enab les p h ase b uiltd out (d efault)
=0 DPLL w ill allow s lock to 0°
Bits (1:0) are for configuring freq uency monitors- 00 = off, 01 = 15p p m, oth ers are reserved for
future use.
50
cnfg_activ_up p er_th resh old 0 Bits (7:0) set th e value in th e leaky b ucket th at causes th e activity alarm to b e raised .
00000110
51
cnfg_activ_low er_th resh old 0 Bits (7:0) set th e value in th e leaky b ucket th at causes th e activity alarm to b e cleared .
00000100
52
cnfg_b ucket_size 0
Bits (7:0) set th e maximum value th at th e leaky b ucket can reach given an inactive inp ut.
00001000
cnfg_d ecay_rate 0
Bits (7:2)
Unused
Bits (1:0) control th e leak rate of th e leaky b ucket. Th e fill-rate of th e b ucket is +1 for every
128 ms interval th at h as exp erienced some level of inactivity. Th e d ecay rate is p rogrammab le
in ratios of th e fill rate. Th e ratio can b e set to 1:1, 2:1, 4:1, 8:1 b y using values of 00, 01, 10,
11 resp ectively. How ever, th ese b uckets are not ‘true’ leaky b uckets in nature. Th e b ucket
stop s ‘leaking’ w h en it is b eing filled . Th is means th at th e fill and d ecay rates can b e th e same
(00 = 1:1) w ith th e net effect th at an active inp ut can b e recognised at th e same rate as an
inactive one.
53
XXXXXX01
54
cnfg_activ_up p er_th resh old 1 A s for register 50 b ut for b ucket 1.
00000110
55
cnfg_activ_low er_th resh old 1 A s for register 51 b ut for b ucket 1.
00000100
56
cnfg_b ucket_size 1
A s for register 52 b ut for b ucket 1.
00001000
57
cnfg_d ecay_rate 1
A s for register 53 b ut for b ucket 1.
XXXXXX01
58
cnfg_activ_up p er_th resh old 2 A s for register 50 b ut for b ucket 2.
00000110
59
cnfg_activ_low er_th resh old 2 A s for register 51 b ut for b ucket 2.
00000100
5A
cnfg_b ucket_size 2
A s for register 52 b ut for b ucket 2.
00001000
5B
cnfg_d ecay_rate 2
A s for register 53 b ut for b ucket 2.
XXXXXX01
5C
cnfg_activ_up p er_th resh old 3 A s for register 50 b ut for b ucket 3.
00000110
5D
cnfg_activ_low er_th resh old 3 A s for register 51 b ut for b ucket 3.
00000100
5E
cnfg_b ucket_size 3
A s for register 52 b ut for b ucket 3.
00001000
5F
cnfg_d ecay_rate 3
A s for register 53 b ut for b ucket 3.
XXXXXX01
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Selection of Input Reference Clock
Source
Under normal operation, the input reference
sources are selected automatically by an order
of priority, where SEC1 is the highest priority,
SEC2 is the second highest priority and SEC3
is the lowest priority. The priorities can be
re-assigned with external software. The SEC1
reference source has inputs via either a low
speed TTL input port or a high speed PECL/
LVDS input port. Similarly, the SEC2 reference
source has both a low speed TTL or a high
speed PECL/LVDS input port. The SEC3
(standby) reference source only has provision
via a low speed TTL input port. There is provision
for one sync clock input via a TTL port. Whilst
SEC1, SEC2 and SEC3 reference source inputs
can all be active at the same time, only one of
the TTL or PECL/LVDS input ports for the SEC1
and SEC2 reference sources may be used at
any time, the inactive port is ignored, by setting
the priority of that port to zero.
Restoration of repaired reference sources is
handled carefully to avoid inadvertent
disturbance of the output clock. The ACS8515
has two modes of operation; Revertive and
Non-Revertive. In Revertive mode, if a revalidated (or newly validated) source has a
higher priority than the reference source which
is currently selected, a switch over will take
place. Many applications prefer to minimise the
clock switching events and choose NonRevertive mode. In Non-Revertive mode , when
a re-validated (or newly validated) source has a
higher priority then the selected source will be
maintained. The re-validation of the reference
source will be flagged in the sts_sources_valid
register and, if not masked, will generate an
interrupt. Selection of the re-validated source
can only take place under software control the software should briefly enable Revertive
mode to affect a switch-over to the higher
priority source. If the selected source fails under
these conditions the device will still not select
the higher priority source until instructed to do
Revision 1.05/December 2002 ãSemtech Corp.
29
so by the software, by briefly setting the
Revertive mode bit. When there is a reference
available with higher priority than the selected
reference, there will be NO change of reference
source as long as the Non-Revertive mode
remains on. This is the case even if there are
lower priority references available or the
currently selected reference fails. When the
ONLY valid reference sources that are available
have a lower priority than the selected
reference, a failure of the selected reference
will always trigger a switch-over regardless of
whether Revertive or Non-Revertive mode has
been chosen.
Automatic Control Selection
When automatic selection is required, the
cnfg_ref_selection registers must be set to allzero or all-one. The configuration registers,
cnfg_ref_selection_priority, held in the µP port
are organised as 5, 4-bit registers with each
representing an input reference port. Unused
ports should be given the value '0000' in the
relevant register to indicate they are not to be
included in the priority table. On power-up, or
following a reset, the whole of the configuration
file will be defaulted to the values defined by
Table 4. The selection priority values are all
relative to each other, with lower-valued
numbers taking higher priorities. Each reference
source should be given a unique number, the
valid values are 1 to 15 (dec). A value of 0
disables the reference source. However if two
or more inputs are given the same priority
number those inputs will be selected on a first
in, first out basis. If the first of two same priority
number sources goes invalid the second will be
switched in. If the first then becomes valid
again, it becomes the second source on the
first in, first out basis, and there will not be a
switch. If a third source with the same priority
number as the other two becomes valid, it joins
the priority list on the same first in, first out
basis. There is no implied priority based on the
channel numbers.
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Ultra Fast Switching
A reference source is normally disqualified after
the leaky bucket monitor thresholds have been
crossed. An option for a faster disqualification
has been implemented, whereby if register 48H,
bit 5 (Ultra Fast Switching), is set then a loss of
activity of just a few reference clock cycles will
set the ‘no activity alarm’ and cause a
reference switch. This can be chosen to cause
an interrupt to occur instead of, or as well as,
causing the reference switch.
Any of these registers can be subsequently set
by external s/w if required.
When external protection switching is enabled,
the device will operate as a simple switch. All
clock monitoring is disabled and the DPLL will
simply be forced to try to lock on to the
indicated reference source. The operating state
(sts_operating_mode register) will always
indicate ‘locked’ in the mode.
External Protection Switching
Activity Monitoring
Fast external switching between inputs SEC1
and SEC2 can also be triggered directly from a
dedicated pin (SRCSW). This mode can be
activated either by holding this pin high during
reset, or by writing to bit 4 of register address
48Hex.
The ACS8515 has a combined inactivity and
irregularity monitor. The ACS8515 uses a ‘leaky
bucket’ accumulator, which is a digital circuit
which mimics the operation of an analog
integrator, in which input pulses increase the
output amplitude but die away over time. Such
integrators are used when alarms have to be
triggered either by fairly regular defect events,
which occur sufficiently close together, or by
defect events which occur in bursts. Events
which are sufficiently spread out should not
trigger the alarm. By controlling the alarmsetting threshold, the point at which the alarm
is triggered can be controlled. The point at which
Once external protection switching is enabled,
then the value of this pin directly selects either
SEC1 (SRCSW high) or SEC2 (SRCSW low). If
this mode is activated at reset by pulling the
SRCSW pin high, then it configures the default
frequency tolerance of SEC1 and SEC2 to +/80 ppm (register address 41Hex and 42Hex).
Figure 9. Inactivity and Irregularity Monitoring
inactivities/irregularities
reference
source
bucket_size
leaky bucket
response
upper_threshold
lower_threshold
programmable fall slopes
(all programmable)
alarm
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the alarm is cleared depends upon the decay
rate and the alarm-clearing threshold. On the
alarm-setting side, if several events occur close
together, each event adds to the amplitude
and the alarm will be triggered quickly; if events
occur a little more spread out, but still
sufficiently close together to overcome the
decay, the alarm will be triggered eventually. If
events occur at a rate which is not sufficient to
overcome the decay, the alarm will not be
triggered. On the alarm-clearing side, if no defect
events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared
when the amplitude falls below the alarmclearing threshold. The ability to decay the
amplitude over time allows the importance of
defect events to be reduced as time passes
by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once
the alarm becomes set, it will be held on until
normal operation has persisted for a suitable
time (but if the operation is still erratic, the
alarm will remain set). See Figure 9.
The ‘leaky bucket’ accumulators are
programmable for size, alarm set & reset
thresholds and decay rate. Each source is
monitored over a 128 ms period. If, within a
128 ms period, an irregularity occurs that is
not deemed to be due to allowable jitter/wander,
then the accumulator is incremented. The
accumulator will continue to increment up to
the point that it reaches the programmed
bucket size. The ‘fill rate’ of the leaky bucket
is, therefore, 8 units/second. The "leak rate"
of the leaky bucket is programmable to be in
multiples of the fill rate (x1, x0.5, x0.25 and
x0.125) to give a programmable leak rate from
8 units/sec down to 1 unit/sec. A conflict
between trying to ‘leak’ at the same time as a
‘fill’ is avoided by preventing a ‘leak’ when a
‘fill’ event occurs.
Disqualification of a non-selected reference
source is based on inactivity, or on an out of
band result from the frequency monitors. The
currently selected reference source can be
Leaky bucket timing
The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky
bucket empty) will be:
(cnfg_activ_upper_threshold N)
secs
8
where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then
this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is
0.75 s.
The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated
as:
(cnfg_decay_rate N)
2
x ((cnfg_bucket_size N) - (cnfg_activ_lower_threshold N))
secs
8
where N is the number of the relevent leaky bucket configuration in each case. The default settings are shown
in the following:
1
2
x (8-4)
= 1.0 s
8
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disqualified for phase, frequency, inactivity or if
the source is outside the DPLL lock range. If
the currently selected reference source is
disqualified, the next highest priority, active
reference source is selected.
Restoration of repaired reference sources is
handled carefully to avoid inadvertant disruption
of the output clock. The ACS8515 operates in
a Non-Revertive mode by default. In this mode,
if the restored reference source has a higher
priority than the reference source which is
currently selected, a switch-over to the restored
source will not tale place automatically. A
restored reference source will assume its
correct place in the priority table but a switchover will only take place automatically upon
failure of the currently selected source. It is
possible to invoke a switch-over by external
control or by enabling Revertive mode.
Modes of Operation
The transition from Free-run to Pre-locked
occurs when the ACS8515 selects a reference
source.
Pre-Locked Mode
The ACS8515 will enter the Locked state in a
maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected
reference source is of good quality. If the device
cannot achieve lock within 100 seconds, it
reverts to Free-run mode and another reference
source is selected.
Locked Mode
The ACS8515 has three primary modes of
operation (Free-run, Locked and Holdover)
supported by three secondary, temporary
modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State
Transition Diagram, Figure 10.
The ACS8515 can operate in Forced or
Automatic control. On reset, the ACS8515
reverts to Automatic Control, where transitions
between states are controlled completely
automatically. Forced Control can be invoked
by configuration, allowing transitions to be
performed under external control. This is not
the normal mode of operation, but is provided
for special occasions such as testing, or where
a high degree of hands-on control is required.
Free-run Mode
The Free-run mode is typically used following a
power-on-reset or a device reset before
network synchronization has been achieved. In
Revision 1.05/December 2002 ãSemtech Corp.
the Free-run mode, the timing and
synchronization signals generated from the
ACS8515 are based on the Master clock
frequency provided from the external oscillator
and are not synchronized to an input reference
source. The frequency of the output clock is a
fixed multiple of the frequency of the external
oscillator, and the accuracy of the output clock
is equal to the accuracy of the Master clock.
32
The Locked mode is used when an input
reference source has been selected and the
PLL has had time to lock. When the Locked
mode is achieved, the output signal is in phase
and locked to the selected input reference
source. The selected input reference source is
determined by the priority table. When the
ACS8515 is in Locked mode, the output
frequency and phase follows that of the
selected input reference source. Variations of
the external crystal frequency have a minimal
effect on the output frequency. Only the
minimum to maximum frequency range is
affected. Note that the term, 'in phase', is not
applied in the conventional sense when the
ACS8515 is used as a frequency translator (e.g.,
when the input frequency is 2.048 MHz and
the output frequency is 19.44 MHz) as the input
and output cycles will be constantly moving past
each other; however, this variation will itself be
cyclical over time unless the input and output
are not locked.
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Lost-Phase Mode
Pre-Locked(2) Mode
Lost-phase mode is entered when the current
phase error, as measured within the DPLL, is
larger than a preset limit (see register 04, bits
5:3), as a result of a frequency or phase transient on the selected reference source. This
mode is similar in behavior to the Pre-locked or
Pre-locked(2) modes, although in this mode the
DPLL is attempting to regain lock to the same
reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100
s, the source is disqualified, and one of the following transitions takes place:
This state is very similar to the Pre-Locked state.
It is entered from the Holdover state when a
reference source has been selected and applied
to the phase locked loop. It is also entered if
the device is operating in Revertive mode and
a higher-priority reference source is restored.
1. Go to Pre-Locked(2);
- If a known-good standby source is available.
2. Go to Holdover;
- If no standby sources are available.
Holdover Mode
The Holdover mode is used when the circuit
was in Locked mode but the selected reference
source has become unavailable and a
replacement has not yet been selected.
Power On Reset - PORB
The Power On Reset (PORB) pin resets the
device if forced Low for a power-on-reset to be
initiated. The reset is asynchronous, the
minimum low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset (POR) is required
at power on, and may be re-asserted at any
time to restore defaults. This is implemented
most simplistically by an external capacitor to
GND along with the internal pull-up resistor.
The ACS8515 is held in a reset state for 250
ms after the PORB pin has been pulled High. In
normal operation PORB should be held High.
Holdover freezes the DPLL at the current
frequency
(as
reported
by
the
sts_curr_inc_offset register). The proportional
DPLL path is ignored so that recent signal
disturbances do not affect the Holdover
frequency value.
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Figure 10. Automatic Mode Control State Diagram
(1)Reset
free-run
select ref
(state 001)
(2) all refs evaluated
&
at least one ref valid
(3) no valid standby ref
&
(main ref invalid
or out of lock >100s)
Reference sources are flagged as ’valid’ when
active, ’in-band’ and have no phase alarm set.
(4) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
pre-locked
w ait for up to 100s
(state 110)
(5) selected ref
phase locked
All sources are continuously checked for
activity and frequency.
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has been continuously in phase lock
for between 1 and 2 seconds
locked
keep ref
(state 100)
(10) selected source phase
locked
(9) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) ]
pre-locked2
w ait for up to 100s
(state 101)
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(15) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
Revision 1.05/December 2002 ãSemtech Corp.
(8) phase
regained within
100s
(6) no valid standby ref
&
main ref invalid
(7) phase lost
on main ref
Lost phase
w ait for up to 100s
(state 111)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
holdover
select ref
(state 010)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(14) all refs evaluated
&
at least one ref valid
34
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Electrical Specification
Important Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation
of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of
this specification are not implied. Exposure to the absolute maximum ratings for an extended
period may reduce the reliability or useful lifetime of the product.
Table 12. Absolute Maximum Ratings
PA RA MET ER
SYM B OL
MIN
MA X
U N IT S
Sup p ly Voltage
V DD, V D+, V A1+,V A2+
V DD
-0.5
3.6
V
Inp ut Voltage
(non-sup p ly p ins)
V in
-
5.5
V
Outp ut Voltage
(non-sup p ly p ins)
Vout
-
5.5
V
TA
-40
85
°C
Tstor
-50
150
°C
A mb ient Op erating Temp erature
Range
Storage Temp erature
Table 13. Operating Conditions
PA RA MET ER
SYM B OL
MIN
T YP
MA X
U N IT S
Pow er Sup p ly (d c voltage)
V DD, V D+,VA 1+, VA 2+, V DD_DIFF
V DD
3.0
3.3
3.6
V
Pow er Sup p ly (d c voltage)
V DD5
V DD5
3.0
3.3/5.0
5.5
V
TA
-40
-
85
°C
Typ ical - one 19 MHz outp ut
Maximum - 190 mA b efore s/w
initialisation, 150 mA after s/w intialisation
IDD
-
110
190/150
mA
Total p ow er d issip ation
PTOT
-
360
685
mW
A mb ient Temp erature Range
Sup p ly Current
Table 14. DC Characteristics: TTL Input Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Inp ut Current
Ii n
-
-
10
µA
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Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up
Across all operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-up Resistor
PU
30
-
80
kW
Inp ut Current
Ii n
-
-
120
µA
Table 16. DC Characteristics: TTL Input Pad with Internal Pull-down
Across all operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-d ow n Resistor
PD
30
-
80
kW
Inp ut Current
Ii n
-
-
120
µA
Table 17. DC Characteristics: TTL Output Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
Vout Low
Iol = 4mA
Vol
0
-
0.4
V
Vout High
Ioh = 4mA
Voh
2.4
-
Drive Current
ID
-
-
Revision 1.05/December 2002 ãSemtech Corp.
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V
4
mA
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Table 18. DC Characteristics: PECL Input/Output Pad
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V ILPECL
V DD-2.5
-
V DD-0.5
V
Differential inp uts (N ote 1)
V IHPECL
V DD-2.4
-
V DD-0.4
V
Inp ut Differential voltage
V IDPECL
0.1
-
1.4
V
V ILPECL_S
V DD-2.4
-
V DD-1.5
V
V IHPECL_S
V DD-1.3
-
V DD-0.5
V
IIHPECL
-10
-
+10
µA
IILPECL
-10
-
+10
µA
V OLPECL
V DD-2.10
-
V DD-1.62
V
V OHPECL
V DD-1.25
-
V DD-0.88
V
V ODPECL
580
-
900
mV
PECL Inp ut Low voltage
Differential inp uts (N ote 1)
PECL Inp ut High voltage
PECL Inp ut Low voltage
Single end ed inp ut (N ote 2)
PECL Inp ut High voltage
Single end ed inp ut (N ote 2)
Inp ut High current
Inp ut d ifferential voltage
V ID = 1.4v
Inp ut Low current
Inp ut d ifferential voltage
V ID = 1.4v
PECL Outp ut Low voltage
(N ote 3)
PECL Outp ut High voltage
(N ote 3)
PECL Outp ut Differential voltage
(N ote 1)
Notes for Table 18
Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to
VDD and GND respectively.
Note 1. Assuming a differential input voltage of at least 100 mV.
Note 2. Unused differential input terminated to VDD-1.4 V.
Note 3. With 50 W load on each pin to VDD-2 V . i.e. 82 W to GND and 130 W to VDD.
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Figure 11. Recommended Line Termination for PECL Input/Output Ports
V DD
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
130R
SEC1_POS
130R
82R
ZO=50Ω
V DD
SEC1_NEG
82R
ZO=50Ω
130R
O1POS
GND
ZO=50Ω
130R
82R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
O1NEG
V DD
82R
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
130R
SEC2_POS
ZO=50Ω
GND
130R
82R
SEC2_NEG
VDD = +3.3 V
82R
GND
Table 19. DC Characteristics: LVDS Input/Output Pad
Across all operating conditions, unless otherwise stated
PA R A M E T E R
LV DS Inp ut voltage range
Differential inp ut voltage = 100 mV
LV DS Differential inp ut th resh old
LV DS Inp ut Differential voltage
SYM B OL
MIN
T YP
MA X
U N IT S
V VRLVDS
0
-
2.40
V
VDITH
-100
-
+100
mV
VIDLVDS
0.1
-
1.4
V
R T E RM
95
100
105
W
V OHLVDS
-
-
1.585
V
V OLLVDS
0.885
-
-
V
V ODLVDS
250
-
450
mV
V DOSLVDS
-
-
25
mV
V OSLVDS
1.125
-
1.275
V
LV DS Inp ut termination resistance
Must b e p laced externally across th e
LV DS+/- inp ut p ins of A CS8515.
Resistor sh ould b e 100 oh m w ith 5%
tolerance
LV DS Outp ut h igh voltage
(N ote 1)
LV DS Outp ut low voltage
(N ote 1)
LV DS Differential outp ut voltage
(N ote 1)
LV DS Ch arge in magnitud e of
d ifferential outp ut voltage for
comp limentary states
(N ote 1)
LV DS outp ut offset voltage
Temp erature = 25°C
(N ote 1)
Note 1. With 100 W load between the differential outputs.
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Figure 12. Recommended Line Termination for LVDS Input/Output Ports
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
SEC1_POS
ZO=50Ω
100R
SEC1_NEG
ZO=50Ω
O1POS
ZO=50Ω
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
100R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
O1NEG
ZO=50Ω
SEC2_POS
ZO=50Ω
100R
SEC2_NEG
Table 20. DC Characteristics: Output Jitter Generation (Test definition G.813)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
TE S T D E F I N I T I O N
FI L T E R U SE D
G.813 for 155.52 MHz op tion 1
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 2)
G.813 for 155.52 MHz op tion 1
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 3)
0.048 (N ote 2)
0.053 (N ote 4)
0.053 (N ote 5)
0.058 (N ote 6)
0.053 (N ote 7)
G.813 for 155.52 MHz op tion 2
12 kHz to 1.3 MHz
UIpp = 0.1
0.053 (N ote 2)
0.058 (N ote 3)
0.057 (N ote 8)
0.055 (N ote 9)
0.057 (N ote 10)
0.057 (N ote 11)
0.057 (N ote 12)
0.053 (N ote 13)
G.813 & G.812 for 2.048 MHz
op tion 1
UIpp = 0.05
20 Hz to 100 kHz
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0.046 (N ote 14)
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Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
G.812 for 1.544 MHz
10 Hz to 40 kHz
UIpp = 0.05
0.036 (N ote 14)
G.812 for 155.52 MHz electrical
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 3)
G.812 for 2.048 MHz electrical
65 kHz to 1.3 MHz
U Ip p =
0.075
0.048 (N ote 3)
Table 22. DC Characteristics: Output Jitter Generation (Test definition ETS-300-462-3)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
ETS-300-462-3 for 2.048 MHz
SEC
20 Hz to 100 kHz
UIpp = 0.5
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SEC
(Filter sp ec 49 Hz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.2
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SSU
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
ETS-300-462-3 for 155.52 MHz
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 3)
ETS-300-462-3 for 155.52 MHz
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 3)
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Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
GR-253-CORE net i/f, 51.84
MHz
100 Hz to 400 kHz
UIpp = 1.5
0.022 (N ote 3)
GR-253-CORE net i/f, 51.84
MHz
(Filter sp ec 20 kHz to 400 kHz)
18 kHz to 400 kHz
UIpp = 0.15
0.019 (N ote 3)
GR-253-CORE net i/f, 155.52
MHz
500 Hz to 1.3 MHz
UIpp = 1.5
0.058 (N ote 3)
GR-253-CORE net i/f, 155.52
MHz
65 kHz to 1.3 MHz
UIpp = 0.15
0.048 (N ote 3)
UIpp = 0.1
0.058 (N ote 3)
UIrms = 0.01
0.006 (N ote 3)
UIpp = 0.1
0.017 (N ote 3)
UIrms = 0.01
0.003 (N ote 3)
UIpp = 0.1
0.036 (N ote 14)
UIrms = 0.01
0.0055 (N ote 14)
GR-253-CORE cat II elect i/f,
155.52 MHz
12 kHz to 1.3 MHz
GR-253-CORE cat II elect i/f,
51.84 MHz
12 kHz to 400 kHz
GR-253-CORE DS1 i/f, 1.544
MHz
10 Hz to 40 kHz
Table 24. DC Characteristics: Output Jitter Generation (Test definition AT&T 62411)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
AT&T 62411 for 1.544 MHz
(Filter sp ec 10 Hz to 8 kHz)
10 Hz to 40 kHz
UIrms = 0.02
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
Broad b and
UIrms = 0.05
0.0055 (N ote 14)
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Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
G.742 for 2.048 MHz
DC to 100 kHz
UIpp = 0.25
0.047 (N ote 14)
G.742 for 2.048 MHz
(Filter sp ec 18 kHz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
G.742 for 2.048 MHz
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
Table 26. DC Characteristics: Output Jitter Generation (Test definition TR-NWT-000499)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
FI L T E R U SE D
U I SP E C
U I M E A S U R E M E N T O N A C S 8515
REV 2
TR-N WT-000499 & G.824 for
1.544 MHz
10 Hz to 40 kHz
UIpp = 5.0
0.036 (N ote 14)
TR-N WT-000499 & G.824 for
1.544 MHz
(Filter sp ec 8 kHz to 40 kHz)
10 Hz to 40 kHz
UIpp = 0.1
0.036 (N ote 14)
Table 27. DC Characteristics: Output Jitter Generation (Test definition GR-1244-CORE)
Across all operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz
TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.
TE S T D E F I N I T I O N
GR-1244-CORE for 1.544 MHz
FI L T E R U SE D
U I SP E C
>10 Hz
Revision 1.05/December 2002 ãSemtech Corp.
UIpp = 0.05
42
U I M E A S U R E M E N T O N A C S 8515
REV 2
0.036 (N ote 14)
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Notes for tables 20 - 227
Note 1.
Filter used is that defined by test definition unless otherwise stated
Note 2.
5 Hz bandwidth, 19.44 MHz input, direct lock
Note 3.
5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 4.
20 Hz bandwidth, 19.44 MHz input, direct lock
Note 5.
20 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 6.
10 Hz bandwidth, 19.44 MHz input, direct lock
Note 7.
10 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 8.
2.5 Hz bandwidth, 19.44 MHz input, direct lock
Note 9.
2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 10.
1.2 Hz bandwidth, 19.44 MHz input, direct lock
Note 11.
1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 12.
0.6 Hz bandwidth, 19.44 MHz input, direct lock
Note 13.
0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 14.
5 Hz bandwidth, 2.048 MHz input, 8 kHz lock
Figure 13. Input/Output Timing
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Revision 1.05/December 2002 ãSemtech Corp.
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ACS8515 Rev2.1 LC/P
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Microprocessor Interface Timing
The device has a Serial microprocessor interface. The combined minimum High and Low times for SCLK define
the maximum clock rate.
For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is
affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us).
This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read
mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final
address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With
CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock
out the SDO.
A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking
it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has
a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz.
SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing
diagrams for Write and Read access for this mode.
Figure 14. Read Access Timing
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
tsu2
tpw2
th2
SCLK
th1
tsu1
_
SDI
R/W
tpw1
A0 A1 A2 A3 A4 A5 A6
td1
SDO
Output not driven, pulled low by internal resistor
td2
D0 D1 D2 D3 D4 D5 D6 D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
th2
SCLK
_
SDI
R/W
A0 A1 A2 A3 A4 A5 A6
td1
SDO
Output not driven, pulled low by internal resistor
td2
D0 D1 D2 D3 D4 D5 D6 D7
F8525D_013ReadAccSerial_01
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Table 28. Read Access Timing
S y m b ol
P ar am e t e r
MIN
T YP
MA X
0 ns
-
-
160 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
td 1
Delay SCLKrising edge ( SCLKfalling edge for CLKE = 1) to SDO valid
-
-
17 ns
td 2
Delay CSBrising edge to SDO h igh -Z
-
-
10 ns
tp w 1
SCLK low time
CLKE = 0
CLKE = 1
250 ns
500 ns
-
-
tp w 2
SCLK h igh time
CLKE = 0
CLKE = 1
250 ns
500 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge, for CLKE = 0
Hold CSB low after SCLKfalling edge, for CLKE = 1
5 ns
-
-
tp
Time b etw een consecutive accesses ( CSBrising edge to CSBfalling edge)
160 ns
-
-
Figure 15. Write Access Timing
CSB
tsu2
tpw2
th2
SCLK
th1
tsu1
_
SDI
SDO
R/W
tpw1
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Output not driven, pulled low by internal resistor
F8525D_014WriteAccSerial_01
Table 29. Write Access Timing
S y m b ol
P ar am e t e r
MIN
T YP
MA X
0 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
160 ns
-
-
tp w 1
SCLK low time
180 ns
-
-
tp w 2
SCLK high time
180 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge
5 ns
-
-
tp
Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
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Package Information
Figure 16. LQFP Package
D
2
D1 1
3
AN2
AN3
1
Section A-A
R1
S
E
2
R2
B
AN1
E1
1
A
A
B
3
AN4
L
4
L1
5
1 2 3
b
Section B-B
7
e
A
A2
c
c1
7
7
Seating plane
A1 6
b1 7
b
8
Notes
1
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
2
To be determined at seating plane.
3
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
4
Details of pin 1 identifier are optional but will be located within the zone indicated.
5
Exact shape of corners can vary.
6
A1 is defined as the distance from the seating plane to the lowest point of the package body.
7
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
8
Shows plating.
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Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16)
64 L Q F P
P ac k ag e
D i m e n si o n s
in mm
D/E
D 1/ E 1
Mi n
N om
Max
12.00
10.00
A
A1
A2
1.40
0.05
1.35
1.50
0.10
1.40
1.60
0.15
1.45
e
0.50
AN1
AN2
AN3
AN4
R1
R2
L
11°
11°
0°
0°
0.08
0.08
0.45
12°
12°
-
3.5°
-
-
0.60
13°
13°
-
7°
-
0.20
0.75
L1
1.00
(ref)
S
b
b1
c
c1
0.20
0.17
0.17
0.09
0.09
-
0.22
0.20
-
-
-
0.27
0.23
0.20
0.16
Thermal Conditions
The device is rated for full temperature range when this package is used with a 4 layer or more
PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum
operating temperature must be reduced when the device is used with a PCB with less than these
requirements.
Figure 17. Typical 64 Pin LQFP Footprint
14.3 mm
13.0 mm (1)
10.6 mm
1.85 mm
Pitch 0.5 mm
Width 0.3 mm
Notes
(1) Solderable to this limit.
Square package - dimensions apply in both X and Y directions.
Typical example - the user is responsible for ensuring compatibility with PCB manufacturing process, etc.
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ACS8515 Rev2.1 LC/P
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ADVANCED COMMUNICATIONS
Application Information
Figure 18. Simplified Application Schematic
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ACS8515 Rev2.1 LC/P
FINAL
ADVANCED COMMUNICATIONS
Appendix A Rev2.1 Changes Described
Summary
This section summarizes the minor changes and improvements made to the ACS8515 from Rev2.0 to Rev2.1.
The bulk of these changes are designed to remove the need for software work arounds associated with Phase
Build Out.
Two new features have been added, necessitating changes to the control software. These are described in detail
below.
Input Edge Alignment for 8k locking mode
An additional bit in the register cnfg_control1 (Bit 2) has been allocated to select which edge of the input
reference to lock to when the device is configured in 8k locking mode.
This bit, when set to one ensures that the rising edge of the output clock phase locks to the rising edge of the
input clock, when 8k locking mode is used on the input.
Low Jitter n x E1/DS1 Mode
A second bit of the cnfg_control1 register has been allocated to controlling what frequency is fed into the APLL.
This allows the user to switch from the normal 77.76MHz to twice the dig2 output frequency.
This has the effect of replacing the normal OC/STM outputs with multiples of the E1 or DS1 rate. The E1/DS1
choice is controlled by the SONET/SDH bit in the cnfg_mode register.
Revision History
Table 31. Changes from Revision 1.04 to 1.05 December 2002.
I t em
S e ct i o n
P ag e
D e scr i p t i o n
1
Serial Mode
44
Up d ated Serial mod e d escrip tion
2
8k Ed ge Polarity
18,
49
Up d ated Register 03 b it 2 and Summary section
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ACS8515 Rev2.1 LC/P
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Ordering Information
PA R T N U M B E R
DE SCR I P T I O N
A CS8515 Rev2.1
SON ET/SDH Line Card Protection, 64 p in LQFP
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or
other critical applications. This product is not authorized or warranted by Semtech Corporation for such use.
Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product.
Customers are advised to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design
practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards.
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail:
sales@semtech.com
acsupport@semtech.com
Internet:
http://www.semtech.com
USA:
Mailing Address:
P.O. Box 6097, Camarillo, CA 93011-6097
Street Address:
200 Flynn Road, Camarillo, CA 93012-8790
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST:
11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE:
Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate,
Romsey, Hampshire, SO51 9DN, UK
Tel: +44 1794 527 600, Fax: +44 1794 527 601
ISO9001
CERTIFIED
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