PRELIMINARY TECHNICAL DATA Low Cost, Low Power Stereo Audio Codec AD74122 a Preliminary Technical Data FEATURES 2.5V Stereo Audio Codec with 3.3 V Tolerant Digital Interface Supports 8kHz to 48 kHz Sample Rates Supports 16/20/24-Bit Word Lengths Multibit Sigma Delta Modulators with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs - Least Sensitive to Jitter Performance (20 Hz to 20 kHz) 85 dB ADC Dynamic Range 93 dB DAC Dynamic Range Digitally Programmable Input/Output Gain On-chip Volume Controls Per Output Channel Software Controllable Clickless Mute Supports 256xFs, 512xFs and 768xFs Master Mode Clocks Master Clock Pre-Scaler for use with DSP master clocks On-Chip Reference 20-Lead TSSOP Package APPLICATIONS Digital Video Camcorders (DVC) Portable Audio Devices (Walkman, PDAs etc.) Audio Processing Voice Processing Telematic Systems General Purpose Analog I/O GENERAL DESCRIPTION The AD74122 is a front-end processor for general purpose audio and voice applications. It features two multi-bit Σ∆ A/D conversion channels and two multi-bit Σ∆ D/A conversion channels. The ADC channels provide >70 dB SNR and the DAC channels provide >80dB SNR both over an audio signal bandwidth. The AD74122 is particularly suitable for a variety of applications where stereo input and output channels are required, including audio sections of Digital Video Camcorders, portable personal audio devices and telematic applications. Its high quality performance also make it suitable for speech and telephony applications such as speech recognition and synthesis and modern feature phones. An on-chip reference voltage is included but can be overdriven by an external reference source if required. The AD74122 offers sampling rates which, depending on MCLK selection and MCLK divider ratio, range from 8 kHz in the voiceband range to 48 kHz in the audio range. The AD74122 is available in 20 lead TSSOP package option and is specified for the automotive temperature range of -40°C to +105°C. FUNCTIONAL BLOCK DIAGRAM RESET MCLK DOUT DCLK DVDD2 AVDD LEFT ADC DIN DFS DVDD1 SERIAL DATA PORT DIGITAL FILTER Σ−∆ ADC MODULATOR CAPPL Gain Stage VINL CAPNL RIGHT ADC DIGITAL FILTER Σ−∆ ADC MODULATOR CAPPR Gain Stage VINR CAPNR LEFT DAC DIGITAL FILTER VOLUME CONTROL Σ−∆ DAC MODULATOR VOUTL Σ−∆ DAC MODULATOR VOUTR RIGHT DAC REFERENCE REFCAP DIGITAL FILTER DGND VOLUME CONTROL AGND REV. PrG 1/03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2003 PRELIMINARY TECHNICAL DATA AD74122–SPECIFICATIONS PARAMETER ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Signal to Noise Ratio (SNR) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter (AVDD =2.5V ±5%, DVDD2 = 2.5V ±5%, DVDD1 = 2.5V ±5%, fCLKIN = 12.288 MHz, fSAMP = 48 kHz, TA = TMIN to TMAX, unless otherwise noted) Min AD74122 Typ 70 24 77 Bits dB 85 85 92 -67 -75 12 dB dB dB dB dB dB dB mV dB Vrms 78 With A-Weighted Filter Total Harmonic Distortion + Noise Programmable Input Gain Gain Step Size Offset Error Gain Error Full Scale Input Voltage Input Resistance Input Capacitance Common Mode Input Volts Crosstalk DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Signal to Noise Ratio (SNR) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter -55 30 -1.5 0.5 10 3 80 80 With A-Weighted Filter Total Harmonic Distortion + Noise -75 -1.0 REFERENCE (Internal) Absolute Voltage, VREF VREF TC –2– Units Test Conditions fS=48kHz fS=16kHz fS=48kHz fS=48kHz fS=16kHz kΩ 15 84 DC Accuracy Offset Error Gain Error Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-emphasis Gain Error Full Scale Output Voltage Output Resistance Common Mode Output Volts Crosstalk Max 1.125 100 pF V dB 24 89 Bits dB 93 93 95 -88 -88 -81 dB dB dB dB dB 10 0.2 50 1.0 mV dB 0.098 60 -100 +/- 0.1 0.5 145 1.125 95 % dB dB dB Vrms Ω V dB 1.125 TBD V ppm/°C ADC Input Signal=1.0kHz, 0dB; DAC Output=DC fS=48kHz fS=16kHz fS=48kHz fS=48kHz fS=16kHz ADC Input Signal=AGND; DAC Output Level=1.0kHz, 0dB REV.PrG PRELIMINARY TECHNICAL DATA AD74122 PARAMETER Min ADC DECIMATION FILTER Pass Band Pass Band Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Low Group Delay Mode AD74122 Typ Max Units 21.5 0.2 kHz mdB kHz kHz dB µs µs 21.5 10 kHz mdB kHz kHz dB µs µs DVDD1 0.8 µA 10 V V pF DVDD1 - 0.4 0 -10 DVDD1 0.4 +10 V V µA 2.375 2.25 2.25 2.75 2.75 3.36 V V V 1 Test Conditions fS=48kHz 5 26.5 120 910 87 DAC INTERPOLATION FILTER1 Pass Band Pass Band Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Low Group Delay Mode fS=48kHz 5 26.5 75 505 55 LOGIC INPUT VINH, Input High Voltage VINL, Input Low Voltage Input Current -10 Input Capacitance DVDD1 - 0.8 0 +10 LOGIC OUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWER SUPPLIES AVDD DVDD2 DVDD1 Power Supply Rejection Ratio 1kHz, 300mV p-p Signal at Analog Supply Pins 50/60Hz, 300mV p-p Signal at Analog Supply Pins 72 dB 73 dB NOTES 1 Guaranteed by Design Specifications subject to change without notice. Table I. Current Summary (AVDD= 2.5V; DVDD1=2.5V; DVDD2=2.5V) Conditions AVDD Current DVDD1 Current DVDD2 Current Total Current (Max) ADC, Reference, Ref-Amp On DAC, Reference, Ref-Amp On Reference, Ref-Amp On All Sections On Powerdown Mode TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD NOTES All Values are typical unless otherwise noted. Max values are quoted with DVDD1=3.6V Sample Rates quoted are for 16kHz and (48kHz) REV. PrG –3– PRELIMINARY TECHNICAL DATA AD74122–SPECIFICATIONS Parameter Min MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low RESET Low tRES tRS DIN Setup Time tRH DIN Hold Time 25 25 20 5 5 SERIAL PORT tFD DFS Delay tFS DFS Setup Time tFH DFS Hold Time tDD DOUT Delay DIN Setup Time tDS tDH DIN Hold Time tDT DOUT Three-State (AVDD =2.5V ±5%, DVDD2 = 2.5V ±5%, DVDD1 = 2.5V ±5%, fCLKIN = 12.288 MHz, fSAMP = 48 kHz, TA = TMIN to TMAX, unless otherwise noted) Max 5 5 5 5 10 10 25 Unit Comments ns ns ns MCLKs MCLKs To RESET Rising Edge1 To RESET Rising Edge1 ns ns ns ns ns ns ns From DCLK Rising Edge2 To DCLK FallingEdge From DCLK Falling Edge From DCLK Rising Edge To DCLK Falling Edge From DCLK Falling Edge From DCLK Rising Edge tMH MCLK tML 4-5-6 tRES DIN tRS tRH Figure <reset.eps> MCLK and RESET Timing tFS 100µA IOL DFS tFH tCH DCLK tCL tFD MSB DIN MSB-1 MSB-2 tDS tDH MSB DOUT MSB-1 MSB-2 TO OUTPUT PIN DVDD1 2 CL 50 pF 100µA IOH tDD Figure <sporttiming.eps>. Serial Port Timing –4– Figure <loadcircuit.eps>. Load Circuit for Digital Output Timing Specification REV.PrG PRELIMINARY TECHNICAL DATA AD74122 TEMPERATURE RANGE Parameter Min Max Unit Specifications Guaranteed Storage -40 -65 +105 +150 ºC ºC ABSOLUTE MAXIMUM RATINGS* 20 Lead TSSOP, θJA Thermal Impedance Lead Temperature, Soldering Vapour Phase (60 sec) Infrared (15 sec) (TA = 25°C, unless otherwise noted.) AVDD, DVDD2 to AGND, DGND DVDD1 to AGND, DGND AGND to DGND Digital I/O Voltage to DGND Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature –0.3 V to +3.0 V -0.3 V to +4.5 V –0.3 V to +0.3 V –0.3 V to DVDD1 + 0.3 V ORDERING GUIDE AD74122YRU Range Package -40ºC to +105ºC RU-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD74122 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrG 215°C 220°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. –40°C to +105°C -65°C to +150°C 150°C Model 150.4°C/W –5– PRELIMINARY TECHNICAL DATA AD74122 PIN FUNCTION DESCRIPTION Pin No. Mnemonic I/O Description 1 2 DCLK DIN I/O I 3 4 5 6 7 8 9 10 11 12 13 14 15 DFS DOUT RESET AVDD CAPN2 CAPP2 VOUTL VINR VINL VOUTL CAPP1 CAPN1 REFCAP I/O O I I/O 16 17 19 19 20 AGND DGND DVDD2 DVDD1 MCLK I Data Port Serial Clock Data Port Serial Data Input. The state of DIN on the rising edge of RESET determines the operating mode of the interface, see Data Port Interface section for more information Data Port Frame Synchronisation signal Data Port Serial Data Output Powerdown/Reset Input Analog Power Supply Connection Filter Capacitor for Channel 2 (Right Channel) Negative Filter Capacitor for Channel 2 (Right Channel) Positive Analog Output - Left Channel Analog Input - Right Channel Analog Input - Left Channel Analog Output - Right Channel Filter Capacitor for Left Channel (Positive) Filter Capacitor for Left Channel (Negative) Internal Reference Decoupling Capacitor - Can also be used for connection of an external reference Analog Ground Connection Digital Ground Connection Digital Power Supply Connection (Core) Digital Power Supply Connection (Interface) External Master Clock Input O I I O PIN CONFIGURATION 20-Lead TSSOP (RU-20) DCLK 1 20 MCLK DIN 2 19 DVDD1 DFS 3 18 DVDD2 4 17 DGND 16 AGND 15 REFCAP DOUT AD74122 4-5-6 5 AVDD 6 CAPNR 7 14 CAPPR CAPPL CAPNL TOP VIEW (Not to Scale) 8 13 VOUTL 9 12 VOUTR VINR 10 11 VINL –6– REV.PrG PRELIMINARY TECHNICAL DATA AD74122 FUNCTIONAL DESCRIPTION master or slave device. The AD74122 can also be set to operate with sample rates of 8KHz to 48KHz depending on the values of MCLK and the MCLK prescalers. On chip digital filtering is provided for the DAC and ADC channels with a low group delay option to reduce the delays through the filters when operating at lower sample rates. Figure <modulators.eps> shows a block diagram of a DAC and ADC channel in the AD74122. Figure <filter.eps> shows a block diagram of the filter arrangement of the ADC and DAC filters. General Description The AD74122 is a 2.5V stereo codec. It comprises two ADC and two DAC channels with single ended inputs and outputs. Signal conditioning and programmable gain stages are also provided. Each of these sections are described in further detail below. The AD74122 is controlled by means of a flexible serial interface port (SPORT) which can be programmed to accomodate many industry standard DSPs and Microcontrollers. The AD74122 can be set to operate as a ADC INPUT MCLK PRESCALERS (/1 to /12) SINC FILTER (/8) Σ−∆ ADC MODULATOR /4 DECIMATOR (/8) ADC Modulator Clock DAC O/P Σ−∆ DAC MODULATOR 5 BITS ADC DATA 16/20/24 BITS /2 DAC Modulator Clock INTERPOLATOR ( X 16) DAC DATA INTERPOLATOR ( X 8) 16/20/24 BITS Figure <modulators.eps>. ADC and DAC Engine REV. PrG –7– PRELIMINARY TECHNICAL DATA AD74122 ADC Modulator 64 × fS 5th Order Comb Filter 8 × fS Halfband Filter 4 × fS Comb Compensation Filter 2 × fS Halfband Filter fS ADC Result Low Group Delay Ouput Figure <ADC Filter.eps>. ADC Filter Section DAC Modulator 128 × fS 16 X Zero Order Hold 8 × fS 4 × fS Halfband Filter Zero Order Hold Sinc Compensation Filter 2 × fS Halfband Filter fS DAC Input Low Group Delay Input Figure <dac filter.eps>. DAC Filter Section ADC Section There are two ADC channels in the AD74122, configured as a stereo pair. Each ADC channel can be independently muted under software control. Each ADC has single input pin with additional pins for decoupling/filter capacitors. Each ADC channel has an independent input amplifier gain stage which can be programmed in steps of +3dB, from 0dB to +12dB. The input amplifier gain settings are set by programming the appropriate bits in Control Register E for the left ADC and Control Register H for the right ADC. The AD74122 input channels employ a multi-bit sigma-delta conversion technique, which provides a high resolution output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over-sampling, where the sampling rate is many times the highest frequency of interest. The oversampling ratio for the ADC is 64 and a decimation filter is used to reduce the output to standard sample rates. The maximum sample rate is 48kHz. Input Signal swing Each ADC input has an input range of 0.5 VRMS / 1.414 VP-P about a bias point equal to VREFCAP (See Figure <ADC_cct>). The analog input can also be AC coupled to the AD74122 as shown which will automatically bias the signal to the VREFCAP value internally. This allows signals biased around a voltage other than VREFCAP to be connected directly to the AD74122. 1.414 V P-P + VAGND 47µF 51⍀ VINx 10nF NPO Figure <ADC_cct.eps>.Input Swing ADC CAPP and CAPN Pins The ADC channel requires two external capacitors to act as charge resevoirs for the switched capacitor inputs of the sigmadelta modulator. These capacitors isolate the outputs of the PGA stage from glitches generated by the sigma-delta modulator. The capacitor also forms a low pass filter with the output impedance of the PGA (approximately 124Ω) which helps to isolate noise from the modulator engine. The capacitors should be of good quality such as NPO or polyproplene film and values from 100pF to 1nF are suitable. Peak Readback The AD74122 can store the highest ADC value from each channel in order to facilatate level adjustment of the input signal. Programming the Peak Enable bit in Control Register H with a 1 will enable ADC Peak Level Reading. The Peak values are stored as a 6 bit number from 0dB to -63dB in 1dB steps. Reading Control Register F and I will give the highest ADC values for the left ADC and right ADC respectively, since the bit was set. The ADC Peak registers are automatically cleared after reading. Decimator Section The digital decimation filter has a passband ripple of ±0.002dB and a stopband attenuation of 120dB. The filter is an FIR type with a linear phase response. The group delay at 48kHz is 910us. Output sample rates up to 48 kHz are supported. –8– DAC Section The AD74122 has two DAC channels arranged as a stereo pair, with two, single-ended, analog outputs. Each channel has it’s own independently programmable attenuator. Control Register G controls the attenuation factor for the left DAC while Control Register J controls the attenuation factor for the right DAC. Each of these registers is 10 bits wide giving 1024 steps of attenuation. AD74122 output channels employ a multi-bit sigma-delta conversion technique, which provides a high quality output with system filtering being implemented on-chip. Output Signal swing Each DAC input has an output range of 0.5 VRMS / 1.414 VP-P (Single-Ended) about a bias point equal to VREFCAP (See Figure <DAC_cct>) VOUT VREFCAP 820⍀ 1.414 V P-P 2n2F NPO Figure <DAC_cct> REV.PrG PRELIMINARY TECHNICAL DATA AD74122 Programmable MCLK Divider Low Group Delay It is possible to bypass much of the digital filtering by enabling the Low Group Delay function in Control Register C. By reducing the amount of filtering the AD74122 applies to input and output samples the time delay between the sampling interval and when the sample is available is greatly reduced. This can be of benefit in applications such as telematics where minimal time delays are important. When the Low Group Delay function is enabled the sample rate becomes IMCLK/128. MCLK Pre-Scaler 1 Pre-Scaler 2 /1 /1 Pre-Scaler 3 /1 /2 /2 /2 /3 /3 /4 IMCLK Control Reg Figure <MCLK_Divider> Reference The AD74122 features an on-chip reference whose nominal value is 1.125 V. A 10 nF capacitor applied at the REFCAP pin is necessary to stabilise the referrence. (See Figure <REFCAP_Int>) The divider ratios will allow more convenient sample rate selection from a common MCLK which may be required in many voice related applications. Control Register B should be programmed to achieve the desired divider ratios. Selecting Sample Rates 10µF + The sample rate at which the convertor runs is always 256 times the IMCLK rate. IMCLK is the Internal Master Clock and is the output from the Master Clock Prescaler. The default sample rate is 48kHz (based on an external MCLK of 12.288MHz). In this mode the ADC modulator is clocked at 3.072MHz and the DAC modulator is clocked at 6.144MHz.. Sample rates which are lower than 256 X MCLK can be acheived by using the MCLK prescaler. REFCAP 0.1µF Example 1: fSAMP = 48 kHz and 8 kHz required Figure <REFCAP_Int.eps> MCLK = 48*103 * 256 = 12.288 MHz to cater for 48 kHz fSAMP If it is required an external reference can be used as the reference source of the ADC and DAC sections. This may be desirable in situations where multiple devices are required to use the same value of reference or because of a better temperature coefficient specifications. The internal reference can be disabled via Control Register A and the external reference applied at the REFCAP pin (See Figure <REFCAP_Ext>). External references should be of a suitable value such that the voltage swing of the inputs or outputs is not effected by being too close to the power supply rails. 1.125 V For fSAMP = 8 kHz, it is necessary to use the /3 setting in PreScaler 1, the /2 setting in Pre-Scaler 2 and pass through in PreScaler 3. This results in an IMCLK = 8*103 * 256 = 2.048 MHz (= 12.288 MHz/6). Example 2: fSAMP = 44.1 kHz and 11.025 kHz required MCLK = 44.1*103 * 256 = 11.2896 MHz to cater for 44.1 kHz fSAMP For fSAMP = 11.025 kHz, it is necessary to use the /1 setting in Pre-Scaler 1 and the /4 setting in Pre-Scaler 2 and pass through in Pre-Scaler 3. This results in an IMCLK = 11.025*103 * 256 = 2.8224 MHz (= 11.2896 MHz/4). REFCAP Reseting the AD74122 The AD74122 can be reset by bringing the RESET pin low. Following a reset the internal circuitry of the AD74122 ensures that the internal registers are reset to their default settings and the on-chip RAM is purged of previous data samples. The DIN pin is sampled to determine if the AD74122 is required to operate in Master or Slave mode. The reset process takes 3072 MCLK periods and the user should not attempt to program the AD74122 during this time. EXTERNAL REFERENCE Figure <REFCAP_Ext.eps> Master Clocking Scheme The update rate of the AD74122’s ADC and DAC channels require an internal master clock (IMCLK) which is 256 times that sample update rate (IMCLK = 256 * FS). In order to provide some flexibility in selecting sample rates, the device has a series of three master clock pre-scalers which are programmable and allow the user to choose a range of convenient sample rates from a single external master clock. The master clock signal to the AD74122 is applied at the MCLK pin. The MCLK signal is passed through a series of three programmable MCLK pre-scalers (divider) circuits which can be selected to reduce the resulting Internal MCLK (IMCLK) frequency if required. The first and second MCLK pre-scalers provides divider ratios of /1 (pass through), /2, /3 while the third prescaler provides divider ratios of /1 (pass through), /2, /4. REV. PrG –9– PRELIMINARY TECHNICAL DATA AD74122 Power Supplies and Grounds Data Mode The AD74122 features three separate supplies: AVDD, DVDD1 and DVDD2. Data Mode can be used when programming or reading the control registers is no longer required. Data Mode will provide a frame synchronisation (DFS) pulse for each channel of data. Once the part has been programmed into Data Mode the only way to change the control registers is to perform a hardware reset to put the codec back into Mixed Mode. Figure <DSP16DM16.eps> shows the default setting for Data Mode. AVDD is the supply to the analog section of the device and must therefore be of sufficient quality to preserve the AD74122’s performance characteristics. It is nominally a 2.5 V supply. DVDD1 is the supply for the digital interface section of the device. It is fed from the digital supply voltage of the DSP or controller to which the device is interfaced and allows the AD74122 to interface with devices operating at supplies of between 2.5 V -5% to 3.3 V + 10%. DVDD2 is the supply for the digital core of the AD74122. It is nominally a 2.5 V supply. Data Word Length The AD74122 can be programmed to send ADC audio data and receive DAC audio data in different word length formats of 16, 20 or 24 bits. The default mode is 16 bits but this can be changed by programming Control Register C for the appropriate word length. Selecting Master or Slave Mode Accessing the Internal Registers The AD74122 has 10 registers which can be programmed to control the functions of the AD74122. Each register is 10 bits wide and is writen to or read from using a 16 bit write or read operation with the exception of Control Registers F and I which are read-only. Table <CWordDescription> shows the format of the data transfer operation. The Control Word is made up of a Read/Write bit, the register address and the data to be written to the device. Note that in a read operation the data field is ignored by the device. Access to the control registers is via the serial port through one of the operating modes described below. Serial Port The AD74122 contains a flexible serial interface port which is used to program and read the control registers of the codec and to send and receive DAC and ADC audio data. The serial port is compatible with many popular DSPs and can be programmed to operate in a variety of modes depending on which one best suits the DSP being used. The serial port can be set to operate as a Master or Slave device which is discussed below. Figure <SportTiming.eps> shows a timing diagram of the serial port. Serial Port Operating Modes The serial port of the codec can be programmed to operate in a variety of modes depending on the requirements and flexibility of the DSP to which it is connected. The two principal modes or operation are Mixed Mode and Data Mode. Mixed Mode Mixed Mode allows for the control registers of the codec to be programmed and read back. It also allows data to be sent to the DACs and data to be read from the ADCs. In Mixed Mode there are seperate data slots each with its own frame syncronisation signal (DFS) for Control, Left Channel and Right Channel information. The Codec powers up in Mixed Mode by default to allow the control registers to be programmed. Figure <DSP16MM16.eps> shows the default setting for Mixed Mode. –10– The initial operating mode of the codec is determined by the state of the DIN pin during the first five MCLKs following a reset. If the DIN pin is high during this time Slave Mode is selected. In Slave Mode the DFS and DCLK pins are inputs and the control signals for these pins must be provided by the DSP or other controller. If the DIN pin is low immediately following a reset the codec will operate in Master Mode. Master Mode Operation In Master Mode the DFS and DCLK pins are outputs from the codec. This is the easiest mode to use the codec in as the correct timing relationship between sample rate, DCLK and DFS is controlled by the codec. Slave Mode Operation In Slave Mode the DFS and DCLK pins are inputs to the codec. Care need to be exercised when designing a system to operate the codec in this mode as the relationship between the sample rate, DCLK and DFS needs to be controlled by the DSP or other controller and must be compatible with the internal DAC/ADC engine of the codec. Figure <engine.eps> shows a block diagram of the DAC engine and the codecs serial port. The sample rate for the DAC engine is determined by the MCLK and MCLK prescalers. The DAC engine will read data from the DAC Left Data and DAC Right Data at this rate. It is therefore important that the serial port is updated at the rate as any error between the two will accumulate and eventually cause the DAC engine to resynchronise with the serial port which will cause erroneous values on the DAC output pins. In most cases it is easy to keep a DSP in synchronisation with the codec if they are both run from the same clock or the DSP clock is a multiple of the codecs MCLK. In this case there will be a fixed relationship between the instruction cycle time of the DSP program and the codec so a timer could be used to accurately control the DAC updates. If a timer is not available the Multi-Frame-Sync (MFS) mode could be used to generate a DFS pulse every 16 or 32 DCLKs allowing the DSP to accurately control the number of DCLKs between updates using an Auto Buffering or DMA type technique. In all cases for Slave Mode operation there should be 128 DCLKs (Normal Mode) or 256 DCLKs (Fast Mode) between DAC updates.The ADC operates in a similar manner, however, if the DSP does not read an ADC result this will only appear as a missed sample and will not be audible. REV.PrG PRELIMINARY TECHNICAL DATA AD74122 t2 DFS t3 DCLK t1 MSB DIN MSB-1 MSB-2 t5 MSB DOUT t6 MSB-2 MSB-1 t4 Figure <Sport Timing> Serial Port (SPORT) Timing OUTL *RESYNC DAC ENGINE LOAD DATA OUTR LEFT DAC DATA DFS DIN RIGHT DAC DATA SERIAL PORT *RESYNC is only used when the DAC becomes unsynchronised with the Serial Port Figure <engine.eps> DAC Engine Table <Op Mode>Serial Mode Selection REV. PrG CRD:3 DM/MM CRD:2 DSP Mode CRC:5,4 Word Width Operating Mode Figure 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 16 16 16 >16 >16 >16 >16 16 Bit Data Mode 32 Bit Data Mode 16 Bit Mixed Mode 32 Bit Mixed Mode 16 Bit Data Mode 32 Bit Data Mode 16 Bit Mixed Mode 32 Bit Mixed Mode Figure Figure Figure Figure Figure Figure Figure Figure –11– <dsp16dm16.eps> <dsp32dm16.eps> <dsp16mm16.eps> <dsp32mm16.eps> <dsp16dm24.eps> <dsp32dm24.eps> <dsp16mm24.eps> <dsp32mm24.eps> PRELIMINARY TECHNICAL DATA AD74122 1/f S DIN DOUT CONTROL DAC LEFT DAC RIGHT (16 BITS) (16 BITS) (16 BITS) CONTROL DAC LEFT DAC RIGHT (16 BITS) (16 BITS) (16 BITS) STATUS (16 BITS) STATUS (16 BITS) ADC LEFT (16 BITS) ADC RIGHT (16 BITS) ADC LEFT (16 BITS) ADC RIGHT (16 BITS) DFS (MM16) 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp16mm16.eps> 16 Bit Mixed Mode :Word Length = 16 Bits 1/f S DIN CONTROL (16 BITS) LEFT DAC DATA (24 BITS) DOUT STATUS (16 BITS) LEFT ADC DATA (24 BITS) CONTROL (16 BITS) RIGHT DAC DATA (24 BITS) STATUS (16 BITS) RIGHT ADC DATA (24 BITS) DFS (MM16) 16 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp16mm24.eps>16 Bit Mixed Mode: Word Length = 24 Bits 1/f S DIN DOUT DAC LEFT (16 BITS) DAC RIGHT (16 BITS) DAC LEFT DAC RIGHT (16 BITS) (16 BITS) ADC LEFT ADC RIGHT (16 BITS) (16 BITS) ADC LEFT ADC RIGHT (16 BITS) (16 BITS) DFS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp16dm16.eps> 16 Bit Data Mode : Word Length = 16 Bits 1/f S DIN LEFT DAC DATA (24 BITS) DOUT LEFT ADC DATA (24 BITS) RIGHT DAC DATA (24 BITS) RIGHT ADC DATA (24 BITS) LEFT DAC DATA (24 BITS) LEFT ADC DATA (24 BITS) DFS (MM16) 16 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp16dm24.eps> 16 Bit Data Mode : Word Length = 24 Bits –12– REV.PrG PRELIMINARY TECHNICAL DATA AD74122 1/f S DIN DOUT CONTROL (16 BITS) LEFT DAC (16 BITS) RIGHT DAC (16 BITS) CONTROL (16 BITS) STATUS (16 BITS) LEFT ADC (16 BITS) RIGHT ADC (16 BITS) STATUS (16 BITS) DFS 32 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp32mm16.eps> 32 Bit Mixed Mode : Word Length = 16 Bits 1/f S DIN DOUT CONTROL (16 BITS) LEFT DAC (24 BITS) RIGHT DAC (24 BITS) CONTROL (16 BITS) STATUS (16 BITS) LEFT ADC (24 BITS) RIGHT ADC (24 BITS) STATUS (16 BITS) DFS 32 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp32mm24.eps> 32 Bit Mixed Mode : Word Length = 24 Bits 1/f S DIN LEFT DAC (16 BITS) RIGHT DAC (16 BITS) LEFT DAC DATA (24 BITS) DOUT LEFT ADC (16 BITS) RIGHT ADC (16 BITS) LEFT ADC DATA (24 BITS) DFS 32 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp32dm16.eps> 32 Bit Data Mode : Word Length = 16 Bits 1/f S DIN LEFT DAC DATA (24 BITS) RIGHT DAC DATA (24 BITS) LEFT DAC DATA (24 BITS) DOUT LEFT ADC DATA (24 BITS) RIGHT ADC DATA (24 BITS) LEFT ADC DATA (24 BITS) DFS 32 DCLKS 128 DCLKs (Normal Mode) 256 DCLKs (Fast Mode) Figure <dsp32dm24.eps> 32 Bit Data Mode : Word Length = 24 Bits REV. PrG –13– PRELIMINARY TECHNICAL DATA AD74122 1/f S 32 DCLKS DFS DIN DOUT C L R C L R S L R S L R Figure <mfs32mm.eps>. Mutli Frame Sync 32 Bit Mixed Mode 1/f S 32 DCLKS DFS DIN DOUT L R L R L R L R Figure <mfs32dm.eps>. Mutli Frame Sync 32 Bit Data Mode 16 DCLKS 1/f S DFS DIN DOUT C L R C L R S L R S L R Figure <mfs16mm.eps> . Mutli Frame Sync 16 Bit Mixed Mode 16 DCLKS 1/f S DFS DIN DOUT L R L R L R L R Figure <mfs16mm.eps> . Mutli Frame Sync 16 Bit Data Mode Table <MFS Mode>Multi Frame Sync Selection CRD:9 MFS CRD:3 DM/MM CRC:2 DSP Mode Operating Mode Figure 1 1 1 1 0 0 1 1 0 1 0 1 16 Bit Data Mode 32 Bit Data Mode 16 Bit Mixed Mode 32 Bit Mixed Mode Figure Figure Figure Figure –14– <mfs16dm.eps> <mfs32dm.eps> <mfs16mm.eps> <mfs32mm.eps> REV.PrG PRELIMINARY TECHNICAL DATA AD74122 Table <ContRegMap>. Control Register Map Address(Binary) Name Description 0 0 0 0 0 0 0 0 1 1 CRA CRB CRC CRD CRE CRF CRG CRH CRI CRJ Control Register A Control Register B Control Register C Control Register D Control Register E Control Register F Control Register G Control Register H Control Register I Control Register J 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Type Width R/W R/W R/W R/W R/W R R/W R/W R R/W 10 10 10 10 10 10 10 10 10 10 Reset Setting TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Table <>Control Word Description R/W Address Res Data Field 15 10 9, 8, 7, 6 , 5 ,4, 3, 2, 1, 0 14,13,12,11 Bit Field Description 15 R/W 14-11 10 9-0 Register Address Reserved Data Field When this bit is high the contents of the data field will be written to the register specified by the Address Field. When this bit is low a read of the register specified by the Address Field will occur at the next sample interval. The contents of the Data Field are ignored. This 4-bit field is used to select one of the 12 Control Registers of the AD74122. This bit is reserved and should always be programmed with zero. This 10-bit field holds the data the is to be written to or read from the register specified in the Address Field. Table <cra.eps>. Control Register A R/ W ADDRESS RES 15 14,13,12,11 10 1 0000 0 REV. PrG FUNCTION ADCR Input Amplifier ADCR DACR ADCL Input Amplifier ADCL DACL Reference Reference Amplifier RESET Reserved 9 8 7 6 5 4 3 2 1 0 0=Off 1=On 0=Off 1=On 0=Off 1=On 0=Off 1=On 0=Off 1=On 0=Off 1=On 0=Off 1=On 0=Off 1=On –15– 0=Default 1=Reset 0 PRELIMINARY TECHNICAL DATA AD74122 Table <crb.eps>. Control Register B R /W ADDRESS RES FUNCTION ADC M odulator DAC M odulator Clock Clock 15 14,13,12,11 10 1 0001 0 9 8 0=64 ⴛ fS 1=32 ⴛ fS Re s Third M CLK Divide r Se cond M CLK Divide r Firs t M CLK Divide r 7, 6 5,4 3,2 1,0 0 00=Divide by 1 01=Divide by 2 10=Divide by 4 11=Divide by 1 0=128 ⴛ fS 1=64 ⴛ fS 00=Divide by 1 01=Divide by 2 10=Divide by 3 11=Divide by 1 00=Divide by 1 01=Divide by 2 10=Divide by 3 11=Divide by 1 Table <crc.eps>. Control Register C R/ W ADDRESS RES Function Reserved DAC & ADC Word Width Low Group Delay DAC De-Emphasis ADC High Pass Filter 5,4 3 2,1 0 15 14,13,12,11 10 9,8,7,6 1 0010 0 0 00=16 Bits 01=20 Bits 10=24 Bits 11=24 Bits 0=Disabled 1=Enabled 00=None 01=44.1kHz 10=32kHz 11=48kHz 0=Disabled 1=Enabled Table <crd.eps>. Control Register D R/ W ADDRESS RES FUNCTION Multi Frame Sync Reserved DM/MM DSP Mode Fast DCLK Master/ Slave 3 2 1 0 15 14,13,12,11 10 9 8,7,6,5,4 1 0011 0 0 = Normal Mode 1= MFS Mode 0 0 = Data Mode 1 = Mixed Mode 0=16 Bits 1= 32 Bits 0=128 ⴛ fS 1= 256 ⴛ fS 0=Slave 1=Master Table <cre.eps>. Control Register E R /W ADDRESS RES FUNCTION Re s e rve d ADCL Pe ak Enable ADCL Gain ADCL M ute DACL M ute 5 4,3,2 1 0 15 14,13,12,11 10 9,8,7,6 1 0100 0 0 0=Disabled 1=Peak Enable –16– 000=0dB 001=3dB 010=6dB 011=9dB 1XX=12dB 0=Normal 1=Mute 0=Normal 1=Mute REV.PrG PRELIMINARY TECHNICAL DATA AD74122 Table <crf.eps>. Control Register F FUNCTION R/ W ADDRESS 15 RES 14,13,12,11 0 10 0101 0 Reserved ADCL Input Peak Level 9,8,7,6 5,4,3,2,1,0 000000 = 0dBFS 000001 = -1dBFS 000010 = -2dBFS 111110 = -62dBFS 111111 = -63dBFS 0 Table <crg.eps>. Control Register G Function R/ W ADDRESS RES DACL Volume 15 14,13,12,11 0 10 0110 0 9,8,7,6,5,4,3,2,1,0 0000000000 = 0dBFS 0000000001 = (1023/1024)dBFS 0000000010 =(1022/1024)dBFS 1111111110 = (2/1024)dBFS 1111111111 = (1/1024)dBFS Table <crh.eps>. Control Register H R/ W ADDRESS RES FUNCTION Reserved ADCR Peak Enable ADCR Gain ADCR Mute DACR Mute 3 4,3,2 1 0 15 14,13,12,11 10 9,8,7,6 1 0111 0 0 0=Disabled 1=Peak Enable 000=0dB 001=3dB 010=6dB 011=9dB 1XX=12dB 0=Normal 1=Mute Table <cri.eps>. Control Register I FUNCTION R/ W 15 0 REV. PrG ADDRESS 14,13,12,11 0101 RES 10 0 Reserved ADCR Input Peak Level 9,8,7,6 5,4,3,2,1,0 0 –17– 000000 = 0dBFS 000001 = -1dBFS 000010 = -2dBFS 111110 = -62dBFS 111111 = -63dBFS 0=Normal 1=Mute PRELIMINARY TECHNICAL DATA AD74122 Table <crj.eps>. Control Register J Function R/ W ADDRESS RES DACR Volume 1001 10 9,8,7,6,5,4,3,2,1,0 0000000000 = 0dBFS 0000000001 = (1023/1024)dBFS 0000000010 =(1022/1024)dBFS 1111111110 = (2/1024)dBFS 1111111111 = (1/1024)dBFS 0 Shrink Small Outline IC (TSSOP) (RU-20) 0.260 (6.60) 0.252 (6.40) 20 0.006 (0.15) 0.002 (0.05) SEATING PLANE 11 0.256 (6.50) 0.246 (6.25) 1 14,13,12,11 0.177 (4.50) 0.169 (4.30) 15 1 10 PIN 1 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) –18– 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 8¡ 0¡ 0.028 (0.70) 0.020 (0.50) REV.PrG