ETC PI74ALVTC16821

PI74ALVTC16821
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2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
Product Features
Description
• PI74ALVTC16821 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A56)
– 56-pin 173-mil wide plastic TVSOP (K56)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16821is a 20-bit bus interface flip-flop designed for
1.65V to 3.6V VCC operation. It can be used as two 10-bit flip-flops
or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a highimpedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data
input’s last state preventing “floating” inputs and eliminating the
need for pullup/down resistors.
Logic Block Diagram
1OE
1
2OE
1CLK 56
2CLK 29
One of Ten
Channels
1D1 55
28
C1
1D
2
One of Ten
Channels
2D1 42
1Q1
TO 9 OTHER CHANNELS
C1
15
1D
2Q1
TO 9 OTHER CHANNELS
1
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Truth Table(1)
Pin Description
Pin Name
OE
CLK
Dx
Qx
GND
VCC
Description
Output Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
OEn
L
L
L
H
Note:
1. H
L
X
Z
↑
n
Pin Configuration
1QE
1
56
1Q1
2
55
1D1
1Q2
3
54
1D2
GND
4
53
GND
1Q3
5
52
1D3
1Q4
6
7
8
51
1D4
50
49
VCC
1D5
48
1D6
1Q7
9
10
47
1D7
GND
11
46
GND
1Q8
12
1Q9
13
1Q10
2Q2
14
15
16
56-Pin
44
A, K
VCC
1Q5
1Q6
45
1D8
2D2
2Q3
40
2D3
GND
18
39
GND
2Q4
19
20
21
38
37
36
2D4
35
34
33
2Q6
2Q7
22
23
2Q8
24
GND
25
26
32
27
28
30
29
VCC
2Q9
2Q10
2OE
31
High Signal Level
Low Signal Level
Irrelevant
High Impedance
LOW-to-HIGH Transition
1,2
1D9
17
2Q5
=
=
=
=
=
=
D
H
L
X
X
Outputs
Qn
H
L
Q0
Z
1CLK
43
42
41
2Q1
Inputs
CLK
↑
↑
H OR L
X
1D10
2D1
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
2
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................. -0.5V to 4.6V
Output Voltage Range, VO (3-Stated) ............................... -0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ........................................ –50mA
DC Output Diode Current (IOK)
VO < 0V .................................................................................... -50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) .......................... -64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
O perating
1.65
3.6
Data Retention O nly
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
O utput voltage
O utput current in IOH/IOL
∆t/∆v
TA
0.8
–0.3
3.6
Active State
0
VDD
O ff State
0
3.6
VDD =
VDD =
VDD =
VDD =
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
O perating free- air temperature
Units
V
–32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VOH
Input Clamp Diode
HIGH Level Output Voltage
Conditions
VDD
IIK = −18mA
3.0
2.7 - 3.6
VDD – 0.2
IOH = −12mA
2.7
2.2
IOH = −18mA
M ax.
3.0
2.2
2.0
IOL = 100µA
2.7 - 3.6
0.2
IOL = 12mA
2.7
0.4
IOL = 18mA
IOL = 24mA
0.45
3.0
0.5
IOL = 64mA
0.55
II
Input Leakage Current
VI = VDD, or GND
3.6
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.7
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
IDD
∆IDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 32mA
IHOLD
Units
2.4
IOH = −32mA
LOW Level Output Voltage
Typ.
–1.2
IOH = −100µA
IOH = −24mA
VOL
M in.
3.6
VI = VDD or GND
75
–75
µA
±500
50
VDD ≤ (VI,VO) ≤ 3.6V
VIH = VDD –0.6V,
Other inputs at VDD or Gnd
4
2.7 - 3.6
±50
400
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100µA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100µA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
0.5
2.3
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
2.5
VI = 1.7V
90
–90
VI = VDD or GND
40
VDD ≤ (VI,VO) ≤ 3.6V
±40
VIH = VDD –0.6V,
Inputs at VDD or Gnd
2.3 - 2.7
µA
µA
400
Note:
1. Not Guaranteed
5
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (1.65V ≤ VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
IIK = –18mA
VDD
M in.
Typ.
1.65
IOH = –100µA
1.65- 1.95
IOH = –6mA
M ax.
–1.2
VDD –0.2
V
1.4
IOL = 100µA
1.65
0.2
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
Units
1.65
VI = 1.3
VI = VDD or GND
50
µA
–50
20
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
6
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
VCC = 1.8V ±0.15V
M in
VCC = 2.5V ±0.2V
M ax
fclock Clock Frequency
M in
VCC = 3.3V ±0.3V
M ax
150
M in
180
180
tw Pulse duration, CLK high or low
3
3
3
tsu Setup time, data before CLK↑
3.5
3.4
3.0
0
0
0
th Hold time, data after CLK↑
M ax
Units
MHz
ns
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
VCC = 1.8V ±0.15V
To
(Output)
M in.
M ax.
fmax
150
VCC = 2.5V ±0.2V
M in.
M ax.
180
VCC = 3.3V ±0.3V
M in.
M ax.
180
MHz
tpd
CLK
Q
5.2
1.5
4.5
1.5
3.2
ten
OE
Q
5.0
1.6
5.0
1.6
4.0
tdis
OE
Q
6.5
2.2
6.5
2.2
5.0
7
Units
ns
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Open
30pF
CL
RL
500Ω
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
1.8V VDD
2 x VDD
VDD
High-Low-High
Pulse
R1
1kΩ
From Output
Under Test
VDD/2
0V
Open
30pF
CL
RL
1kΩ
GND
Propagation Delay
(See Note A)
VDD
VDD/2
0V
Input
tPLH
Setup, Hold, and Release Timing
Data
Input
tSU
Timing
Input
tH
tPHL
VDD
VDD/2
VOL
Output
tPHL
VDD
VDD/2
0V
tPLH
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
Enable Disable Timing
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions
such that the output is LOW except when disabled by
the output control.
Waveform 2 is for an output with internal conditions
such that the output is HIGH except when disabled by
the output control.
C. All input pulses are supplied by generators having the
following characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one
transition per measurement.
VDD
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
-0.15V
VOH
VDD/2
0V
(see Note B)
8
VOL
tPHZ
PS8618
06/05/02
PI74ALVTC16821
2.5V 20-Bit Bus Interface
Flip-Flop with 3-State Outputs
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56-Pin TSSOP Package (A)
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
56-Pin TVSOP Package (K)
56
.169
.177
4.30
4.50
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Orde ring Code
Package Type
PI74ALVTC16821A
56- Pin 240- mil TSSO P
PI74ALVTC16821K
56- Pin 173- mil TVSO P
Orde ring Range
–40°C to 85°C
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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