10BIT 30MSPS ADC 10BIT 30MSPS ADC ADC1342X ADC1342X GENERAL DESCRIPTION FEATURES The ADC1342X is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A converters (DACs), and subranging flash ADCs. The maximum conversion rate of ADC1342X is 30MSPS and supply voltage is 2.5V single. - Resolution : 10Bit Differential Linearity Error : ±1.0 LSB Integral Linearity Error : ±2.0 LSB Maximum Conversion Rate : 30MSPS Sample & Hold Function Implemented Low Power Consumption : 75mW(Typ) Power Supply : 2.5V Single Operation Temperature Range : -40~85ºC TYPICAL APPLICATIONS - CCD imaging processors Camcorders, scanners, and security cameras. - Read channel LSI HDD, DVD, and CD-ROM drives - IF and baseband signal digitizers - Portable equipments for low-power applications AVSS25D AVBB25D AVDD25D AVBB25A AVSS25A AVDD25A FUNCTIONAL BLOCK DIAGRAM AINT SHA MDAC1 MDAC2 MDAC3 Flash1 Flash2 Flash3 AINC REFTOP REFBOT STC ITEST PD Flash4 EOC Digital Correction Logic (DCL) Bias Current Generator DO[9:0] Clock Generator CML Level Generator CML CKIN SPEEDUP Ver 1.0 (Apr. 2002) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD SEC ASIC Analog Core ADC1342X 10BIT 30MSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION AINT AI pmiar10_abb Analog Input + (0.95V ~ 1.55V) AINC AI pmiar10_abb Analog Input - (1.55V ~ 0.95V) REFTOP AI pmia_abb Reference Top (1.55V) REFBOT AI pmia_abb Reference Bottom (0.95V) AVDD25A AP AVSS25A AG vsstm_abb Analog Ground AVBB25A AG vbbm_abb Analog Sub Bias ITEST AB pmia_abb Test pin (normally, open) PD DI pmicc_abb Power down mode (normally, gnd) STC DI pmicc_abb Start of conversion signal (normally, high) SPEEDUP DI pmicc_abb Speed test pin (normally, gnd) CKIN DI pmicc_abb Sampling Clock Input CML AB pmoa_abb Test Pin (normally, open) DO[9:0] DO pmot8_abb Digital Output EOC DO pmot8_abb End of conversion signal AVBB25D DG vbbm_abb Digital Sub Bias AVSS25D DG vsstm_abb Digital Ground AVDD25D DP vdd25tm_abb Analog Power (2.5V) I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional - AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground vdd25tm_abb Digital Power AVBB25D AVSS25D AVDD25D AVBB25A AVSS25A AVDD25A CORE CONFIGURATION EOC AINT adc1342x DO[9:0] AINC 2 / 13 SPEEDUP STC PD ITEST CML REFTOP SEC ASIC REFBOT CKIN Analog Core ADC1342X 10BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 3.6 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage CLK VSS to VDD V VOH, VOL VSS to VDD V -45 to 150 ºC Digital Output Voltage Storage Temperature Range Tstg NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5KΩ resistor (Human body model). RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage AVDD25A - AVSS25A AVDD25D - AVSS25D 2.38 2.5 2.63 V Supply Voltage Difference AVDD25A - AVDD25D -0.1 0.0 0.1 V REFTOP REFBOT - 1.55 0.95 - V Analog Input Voltage (+) AINT 0.95 - 1.55 V Analog Input Voltage (-) AINC 1.55 - 0.95 V Operating Temperature Topr -40 - 85 ºC Characteristics Reference Input Voltage(Externally) NOTES 1. It is strongly recommended that all the supply pins (AVDD25A, AVDD25D) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit - - 10 - Bits Reference Current IREF - 2 3 mA Differential Linearity Error DLE - - ±1.0 LSB Integral Linearity Error ILE - - ±2.0 LSB Bottom Offset Voltage Error EOB - - 20 LSB Top Offset Voltage Error EOT - - 20 LSB Resolution Conditions NOTES 1. Converter Specifications (unless otherwise specified) AVDD25A=2.5V AVDD25D=2.5V AVSS25A=GND AVSS25D=GND Ta=25ºC 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Maximum Conversion Rate fc - - 30 MSPS Dynamic Supply Current Ivdd - 30 - mA fc=30MHz (without system load) Digital Output Data Delay td - 1.8 - ns See "TIMING DIAGRAM" Signal - to - Noise Ratio SNR 48 52 - dB AINT = 1MHz fc = 30MHz SEC ASIC 4 / 13 Conditions Analog Core ADC1342X 10BIT 30MSPS ADC I/O CHART Index AINT Input (V) AINC Input (V) Digital Output 0 0.950000 ~ 0.950587 1.549413 ~ 1.550000 0000000000 1 0.950587 ~ 0.951174 1.548826 ~ 1.549413 0000000001 2 0.951174 ~ 0.951761 1.548239 ~ 1.548826 0000000010 ••• ••• ••• ••• 1LSB=1.1730mV 511 1.249413 ~ 1.250000 1.250578 ~ 1.251174 0111111111 for differential input 512 1.250000 ~ 1.250578 1.250000 ~ 1.250578 1000000000 513 1.250578 ~ 1.251174 1.249413 ~ 1.250000 1000000001 REFTOP=1.55V ••• ••• ••• ••• REFBOT=0.95V 1021 1.548239 ~ 1.548826 0.951174 ~ 0.951761 1111111101 1022 1.548826 ~ 1.549413 0.950587 ~ 0.951174 1111111110 1023 1.549413 ~ 1.550000 0.950000 ~ 0.950587 1111111111 SEC ASIC 5 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC TIMING DIAGRAM 1. Main Waveform A1 Analog Input A2 A6 A4 CKIN STC Pipeline Delay EOC td DO[9:0] D1 D2 D4 D6 Output code of DO[9:0] is generated during STC (Start of Conversion) signal is just "HIGH". Otherwise, it keeps the current states. After STC goes "HIGH", the A/D converter requires the pipeline delay of 3 clock period to generate EOC signal and DO[9:0]. 2. STC and CKIN 8ns Tsafe 4ns 8ns Tsafe 4ns CKIN STC The STC signal is rising-edge triggered, and it should be changed during "Tsafe" region on CKIN . SEC ASIC 6 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC CORE EVALUATION GUIDE 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased internally through resistor devider. Analog Input Clock Input CKIN AINT AINC GND AVBB25A AVDD25D PD AVSS25D AVBB25D GND SPEEDUP EOC DO[9:0] STC GND STC Input or 2.5V GND 2.5V ITEST AVSS25A GND CML 2.5V AVDD25A adc1401x REFBOT GND 1.55V 0.95V Reference Reference Top Bottom REFTOP HOST : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 10uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED DIGITAL MUX DSP CORE 7 / 13 NOTES 10-bit Digital Output BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcin g SEC ASIC Analog Core ADC1342X 10BIT 30MSPS ADC PACKAGE CONFIGURATION 1.55V 10u 0.1u 10u 0.1u 0.95V 0.1u 2.5V 10u 0.1u 0.1u Analog input 50 1K 0.1u 0.1u 2.5V 10u 0.1u Clock in 50 1 REFTOP AVDD25D 48 2 REFTOP AVDD25D 47 3 REFBOT AVSS25D 46 4 REFBOT AVSS25D 45 5 CML AVBB25D 44 6 AVDD25A STC 43 STC in 7 AVDD25A EOC 42 EOC out 8 AVBB25A NC 41 9 AVSS25A NC 40 10 AVSS25A NC 39 11 AINT NC 38 12 NC NC 37 13 AINC DO[9] 36 adc1401x_top 14 NC DO[8] 35 15 SPEEDUP DO[7] 34 16 ITEST DO[6] 33 17 PD DO[5] 32 18 AVDD25R DO[4] 31 19 AVSS25R DO[3] 30 20 CKIN DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 NC NC 26 24 NC NC 25 2.5V 0.1u 10u 10-b ADC output : Test Pin No bias forcing, Remain floating NOTES 1. This information is for testing the provided test-chips of ADC1342X. SEC ASIC 8 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC PACKAGE PIN DESCRIPTION NAME PIN NO. I/O TYPE PIN DESCRIPTION REFTOP 1,2 AI External Reference Top Bias (1.55V) REFBOT 3,4 AI External Reference Bottom Bias (0.95V) CML 5 AB Internal Bias Point (Test Pin) AVDD25A 6,7 AP Analog Power (2.5V) AVBB25A 8 AG Analog Sub Bias AVSS25A 9,10 AG Analog Ground AINT 11 AI Analog Input + (Input Range : 0.95~1.55V Differential) AINC 13 AI Analog Input. - (Input Range : 1.55~0.95V Differential) SPEEDUP 15 DI Speed test pin. Tie to analog gnd ITEST 16 AB open=use internal bias point PD 17 DI Power down mode (normally gnd) AVDD25R 18 PP Ouput Driver Power (2.5V) AVSS25R 19 PG Output Driver Ground CKIN 20 DI Sampling Clock Input DO[9:0] 27~36 DO 10bit Digitized Output EOC 42 DO End of conversion signal STC 43 DI Start of conversion signal AVBB25D 44 DG Digital Substrate Bias AVSS25D 45,46 DG Digital Ground AVDD25D 47,48 DP Digital Power (2.5V) NOTES 1. This information is for testing the provided test-chips of ADC1342X. 2.. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. SEC ASIC 9 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC USER GUIDE 1. Input signal range The ADC was designed to use both single and differential mode input, but the differential mode is recommended to guarantee the operating margin in the low voltage condition. - Differential mode input condition Pin Input range AINT 0.95V~1.55V AINC 1.55V~0.95V Conditions 180º phase shifted input with the same DC level with AINT - Single mode input condition Pin Input range AINT 0.65V~1.85V AINC 1.25V Conditions forced from the clean DC source or CML pin of ADC1342X 2. Input signal speed Normal speed range of ADC1342X is 1~6MHz input quantized by 30MHz clock, which is fixed by a normal video signal format. To use the input of ADC1342X on near or over nyquist ranges such as the direct IF processing, consult about the additional performance issues with SEC. SEC ASIC 10 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC PHANTOM CELL INFORMATION - Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user. AVDD25D AVDD25D CKIN DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] AVSS25D STC EOC AVBB25D AVBB25D AVSS25D PD Pin Name Pin Usage Pin Layout Guide AVDD25A External - Maintain the large width of lines AVSS25A External AVBB25A External AVDD25A External AVSS25D External as far as the pads. - place the port positions to minimize the length of power lines. SPEEDUP ITEST - Do not merge the analog powers with anoter power from other AVBB25D REFBOT External blocks. - Use good power and ground CML source on board. REFTOP AINT External/Internal - Do not overlap with digtal lines. AINT AINC External/Internal - Maintain the shotest path to pads. CKIN External/Internal AINC - Separate from all other analog signals ADC1342X REFTOP External/Internal - Maintain the larger width and the 10bit 30MSPS ADC REFBOT External/Internal CML External/Internal ITEST External/Internal shorter length as far as the pads. - Separate from all other digital AVDD25A AVDD25A AVBB25A AVSS25A AVBB25A AVSS25A SEC ASIC PD External/Internal STC External/Internal SPEEDUP External/Internal EOC External/Internal DO[9] External/Internal DO[8] External/Internal DO[7] External/Internal DO[6] External/Internal DO[5] External/Internal DO[4] External/Internal DO[3] External/Internal DO[2] External/Internal DO[1] External/Internal DO[0] External/Internal 11 / 13 lines. - Separated from the analog clean signals if possible. - Do not exceed the length by 1,000um. Analog Core ADC1342X 10BIT 30MSPS ADC FEEDBACK REQUEST It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Bit Resolution Bit Reference Input Voltage V Analog Input Voltage Vpp Operating Temperature ºC Integral Non-linearity Error LSB Differential Non-linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Maximum Conversion Rate Remarks MSPS Dynamic Supply Current mA Power Dissipation mW Signal-to-noise Ratio dB Pipeline Delay CLK Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 12 / 13 Analog Core ADC1342X 10BIT 30MSPS ADC HISTORY CARD Version Date ver 1.0 02.4.01 Modified Items Comments Original version published (preliminary) Change the reference range from "0.6V~1.2V" to "0.5V~1.3V" SEC ASIC 13 / 13 Analog Core