Rev 0; 11/03 3.3V Spread-Spectrum EconOscillator The DS1086L EconOscillator™ is a 3.3V programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The selectable dithered output reduces radiated-emission peaks by dithering the frequency 0.5%,1%, 2%, 4%, or 8% below the programmed frequency. The DS1086L has a power-down mode and an output-enable control for power-sensitive applications. All the device settings are stored in nonvolatile (NV) EEPROM memory allowing it to operate in stand-alone applications. Applications Features ♦ User-Programmable Square-Wave Generator ♦ Frequencies Programmable from 130kHz to 66.6MHz ♦ 0.5%, 1%, 2%, 4%, or 8% Selectable Dithered Output ♦ Adjustable Dither Rate ♦ Glitchless Output-Enable Control ♦ 2-Wire Serial Interface ♦ Nonvolatile Settings Printers ♦ 2.7V to 3.6V Supply Copiers ♦ No External Timing Components Required PCs ♦ Power-Down Mode Computer Peripherals ♦ 5kHz Master Frequency Step Size Cell Phones ♦ EMI Reduction Cable Modems ♦ Industrial Temperature Range: -40°C to +85°C Ordering Information PART DS1086LU TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 µSOP (118 mil) Pin Configuration Typical Operating Circuit µP XTL1/OSC1 XTL2/OSC2 VCC DITHERED 130kHz TO 66.6MHz OUTPUT VCC N.C. OUT SCL* SPRD SDA* DS1086L VCC PDN GND OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. TOP VIEW OUT 1 8 SCL 7 SDA 3 6 PDN GND 4 5 OE SPRD 2 DS1086L VCC µSOP EconOscillator is a trademark of Dallas Semiconductor. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1086L General Description DS1086L 3.3V Spread-Spectrum EconOscillator ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Relative to Ground ..........-0.5V to +6.0V Voltage Range on SPRD, PDN, OE, SDA, and SCL Relative to Ground* ..................................-0.5 to (VCC + 0.5V) Operating Temperature Range ...........................-40°C to +85°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature ..................See IPC/JEDEC J-STD-020A *This voltage must not exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) Low-Level Input Voltage (SDA, SCL SPRD, PDN, OE) SYMBOL VCC CONDITIONS (Note 1) MIN TYP 2.7 3.3 MAX UNITS 3.6 V VIH 0.7 x VCC VCC + 0.3 V VIL -0.3 0.3 x VCC V MAX UNITS DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER SYMBOL High-Level Output Voltage (OUT) VOH IOH = -4mA, VCC = min Low-Level Output Voltage (OUT) VOL IOL = 4mA 0 0.4 VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 Low-Level Output Voltage (SDA) CONDITIONS MIN TYP 2.4 V V High-Level Input Current IIH VCC = 3.6V Low-Level Input Current IIL VIL = 0 ICC CL = 15pF (output at default frequency) 10 mA Power-down mode 10 µA Supply Current (Active) Standby Current (Power-Down) 2 ICCQ _____________________________________________________________________ 1 V -1 µA µA 3.3V Spread-Spectrum EconOscillator DS1086L MASTER OSCILLATOR CHARACTERISTICS (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER Master Oscillator Frequency Default Master Oscillator Frequency SYMBOL fOSC f0 CONDITIONS (Note 2) MIN TYP 33.3 Factory-programmed default MAX 66.6 48.65 ∆f0 f0 VCC = 3.3V, TA = +25°C (Notes 3,17) Default frequency (f0) -0.5 +0.5 DAC step size -0.5 +0.5 Voltage Frequency Variation ∆fV f0 Over voltage range, TA = +25°C (Note 4) Default frequency -0.75 +0.75 DAC step size -0.75 +0.75 ∆fT f0 Over temperature range, VCC = 3.3V (Note 5) Default frequency -2.0 +0.75 Temperature Frequency Variation 66.6MHz -2.0 +0.75 33.3MHz -2.5 Dither Frequency Range (Note 6) Integral Nonlinearity of Frequency INL MHz MHz Master Oscillator Frequency Tolerance ∆f f0 UNITS % 0.5 Prescaler bits JS2, JS1, JS0 = 001 1 Prescaler bits JS2, JS1, JS0 = 010 2 Prescaler bits JS2, JS1, JS0 = 100 4 Prescaler bits JS2, JS1, JS0 = 111 8 DAC Step Size ∆ between two consecutive DAC values (Note 8) DAC Span % +0.75 Prescaler bits JS2, JS1, JS0 = 000 Entire range (Note 7) % -0.6 % +0.3 % 5 kHz Frequency range for one offset setting (Table 2) 5.12 MHz DAC Default Factory default register setting 500 decimal Offset Step Size ∆ between two consecutive offset values (Table 2) 2.56 MHz Offset Default OS Factory default OFFSET register setting (5 LSBs) (Table 2) Prescaler bits JS4, JS3 = 00 Dither Rate RANGE (5 LSBs of RANGE register) hex f0/8192 Prescaler bits JS4, JS3 = 01 f0/4096 Prescaler bits JS4, JS3 = 10 f0/2048 Hz _____________________________________________________________________ 3 DS1086L 3.3V Spread-Spectrum EconOscillator AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 period 0.1 1 ms 0.1 0.5 ms 200 µs 100 µs 50 pF Frequency Stable After Prescaler Change Frequency Stable After DAC or Offset Change Power-Up Time tDACstab tpor + tstab (Note 10) Enable of OUT After Exiting Power-Down Mode tstab OUT High-Z After Entering Power-Down Mode tpdn Load Capacitance (Note 9) CL Output Duty Cycle (OUT) (Note 18) (Note 11) 15 Default frequency 45 Rise and Fall Time (OE, PDN) 55 % 1 µs MAX UNITS 400 100 kHz AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition tBUF Hold Time (Repeated) START Condition tHD:STA LOW Period of SCL tLOW HIGH Period of SCL tHIGH Setup Time for a Repeated START tSU:STA Data Hold Time tHD:DAT Data Setup Time tSU:DAT Rise Time of Both SDA and SCL Signals tR Fall Time of Both SDA and SCL Signals tF 4 CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode MIN (Note 12) (Note 12) (Notes 12, 13) (Note 12) (Note 12) (Note 12) (Notes 12, 14, 15) (Note 12) (Note 16) (Note 16) _____________________________________________________________________ TYP 1.3 µs 4.7 0.6 µs 4.0 1.3 4.7 0.6 4.0 0.6 µs µs µs 4.7 0 0.9 100 250 20 + 0.1CB 300 20 + 0.1CB 1000 µs ns 20 + 0.1CB 300 20 + 0.1CB 1000 ns ns 3.3V Spread-Spectrum EconOscillator (VCC = 2.7V to 3.6V, TA = -40°C to +85°C.) PARAMETER Setup Time for STOP SYMBOL tSU:STO Capacitive Load for Each Bus Line CB EEPROM Write Cycle Time tWR Input Capacitance CONDITIONS MIN Fast mode 0.6 Standard mode 4.0 TYP UNITS µs (Note 16) CI MAX 400 pF 10 ms 5 pF NONVOLATILE MEMORY CHARACTERISTICS (VCC = 2.7V to 3.6V) PARAMETER EEPROM Writes Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: SYMBOL CONDITIONS +70°C MIN 10,000 TYP MAX UNITS All voltages are referenced to ground. DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range. Correct operation of the device is not guaranteed if these limits are exceeded. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25°C. This is the percentage frequency change from the +25°C frequency due to temperature at VCC = 3.3V. The maximum temperature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequency (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz). The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two endpoints (fosc(MIN) to fosc(MAX)) of the range. The error is in percentage of the span. This is true when the prescaler = 1. Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original value to the new value. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. Output voltage swings can be impaired at high frequencies combined with high output loading. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr max VCC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr 121°C/2 ATM Steam/Unbiased Autoclave. tstab is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of tDACstab is required before the frequency will be within its specified tolerance. _____________________________________________________________________ 5 DS1086L AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued) Typical Operating Characteristics (VCC = 3.3V, TA = 25°C, unless otherwise noted.) SUPPLY CURRENT vs. MASTER OSCILLATOR FREQUENCY 5 4 4.7pF LOAD 3 8 fO = 50MHz 7 6 fO = 33.3MHz 5 PRESCALER = 1 3 2 0 -40 33 36 39 42 45 48 51 54 57 60 63 66 -15 10 35 85 60 MASTER FREQUENCY (MHz) TEMPERATURE (°C) MASTER OSCILLATOR FREQUENCY PERCENT CHANGE vs. SUPPLY VOLTAGE MASTER OSCILLATOR FREQUENCY PERCENT CHANGE vs. TEMPERATURE fO = 66MHz 0.1 0 -0.1 fO = 50MHz -0.2 fO = 33.3MHz 54 -0.25 fO = 50MHz -0.75 fO = 66MHz 52 fO = 50MHz -0.5 51 PRESCALER = 1 15pF LOAD -1.25 PRESCALER = 1 3.0 3.3 3.6 50 -40 -15 SUPPLY VOLTAGE (V) 10 35 85 60 -40 TEMPERATURE (°C) DUTY CYCLE vs. SUPPLY VOLTAGE DUTY CYCLE (%) DS1086L toc07 54 fO = 66MHz 53 52 fO = 50MHz 51 fO = 33.3MHz PRESCALER = 1 2.7 3.0 -15 10 35 TEMPERATURE (°C) 55 3.3 SUPPLY VOLTAGE (V) 6 fO = 33.3MHz PRESCALER = 1 -1.50 2.7 fO = 66MHz 53 -1.00 -0.3 -0.4 fO = 33.3MHz 0 -0.50 1000 100 DUTY CYCLE vs. TEMPERATURE DUTY CYCLE (%) 0.2 0.25 PERCENT CHANGE (%) 0.3 10 55 DS1086L toc05 0.4 1 PRESCALER 0.50 DS1086L toc04 0.5 fO = 50MHz 15pF LOAD 1 3 1 DS1086L toc03 4 PRESCALER = 1 15pF LOAD 4 2 5 DS1086L toc06 6 6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 15pF LOAD 7 fO = 66MHz 9 SUPPLY CURRENT vs. PRESCALER 7 DS1086L toc02 8 SUPPLY CURRENT (mA) SUPPLY CURRENT vs. TEMPERATURE 10 DS1086L toc01 9 PERCENT CHANGET (%) DS1086L 3.3V Spread-Spectrum EconOscillator _____________________________________________________________________ 3.6 60 85 3.3V Spread-Spectrum EconOscillator POWER-DOWN CURRENT vs. SUPPLY VOLTAGE POWER-DOWN CURRENT vs. TEMPERATURE 1.6 1.5 1.4 1.3 1.2 DS1086L toc09 POWER-DOWN CURRENT (µA) 1.7 1.64 1.62 POWER-DOWN CURRENT (µA) DS1086L toc08 1.8 1.60 1.58 1.56 1.54 1.52 1.50 1.48 1.46 1.1 1.44 1.0 2.7 3.0 3.3 -40 3.6 -15 SUPPLY VOLTAGE (V) SUPPLY CURRENT WITH OUTPUT DISABLED vs. SUPPLY VOLTAGE 60 85 3.0 2.5 2.0 1.5 1.0 DS1086L toc11 2.7 2.6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 3.5 35 SUPPLY CURRENT WITH OUTPUT DISABLED vs. TEMPERATURE DS1086L toc10 4.0 10 TEMPERATURE (°C) 2.5 2.4 2.3 0.5 fO = 66MHz fO = 66MHz 0 2.2 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) ______________________________________________________________________ 7 DS1086L Typical Operating Characteristics (continued) (VCC = 3.3V, TA = 25°C, unless otherwise noted.) 3.3V Spread-Spectrum EconOscillator PIN NAME 1 OUT 2 SPRD 3 VCC 4 GND FUNCTION Oscillator Output. The output frequency is determined by the OFFSET, DAC, and prescaler registers. Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. Power Supply Ground 5 OE Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the master oscillator is still on. 6 PDN Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator is disabled (power-down mode). 7 SDA 2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and can be wire-ORed with other open-drain or open-collector interfaces. 8 SCL 2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on falling edges. SPECTRUM COMPARISON (12OkHz BW, SAMPLE DETECT) MAXIMUM THERMAL VARIATION vs. MASTER OSCILLATOR FREQUENCY -10 NO SPREAD 2% -20 3% 2% SUPPLY CURRENT (mA) POWER SPECTRUM (dBm) 0.5% 8% DS1086L fig01 0 DS1086L fig02 DS1086L Pin Description -30 -40 -50 -60 1% 0 -1% -2% -3% -70 fo = 50MHz DITHER RATE = fo/4096 -80 -4% -5% -90 43 45 47 49 51 33 36 39 42 45 48 51 54 57 60 63 66 53 MASTER FREQUENCY (MHz) FREQUENCY (MHz) Figure 2. Temperature Variation Over Frequency Figure 1. Clock Spectrum Dither Comparison Stand-Alone Mode Processor-Controlled Mode VCC µP XTL1/OSC1 4.7kΩ DITHERED 260kHz TO 133MHz OUTPUT VCC SDA DS1086 VCC PDN GND OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) 8 SCL OUT SPRD 4.7kΩ VCC XTL2/OSC2 VCC DITHERED 130kHz TO 66.6MHz OUTPUT VCC N.C. 2-WIRE INTERFACE OUT SCL* SPRD SDA* DS1086L VCC PDN GND OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. _____________________________________________________________________ 3.3V Spread-Spectrum EconOscillator DS1086L VCC VCC SDA SCL 2-WIRE INTERFACE EEPROM CONTROL REGISTERS DS1086L DAC DAC OFFSET ADDR RANGE FREQUENCY CONTROL VOLTAGE PRESCALER VOLTAGE-CONTROLLED OSCILLATOR PDN MASTER OSCILLATOR OUTPUT DITHER CONTROL PRESCALER BY 1, 2, 4...256 OUT OE SPRD GND TRIANGLE WAVE GENERATOR DITHER SIGNAL Figure 3. Block Diagram Detailed Description A block diagram of the DS1086L is shown in Figure 3. The internal master oscillator generates a square wave with a 33.3MHz to 66.6MHz frequency range. The frequency of the master oscillator can be programmed with the DAC register over a two-to-one range in 5kHz steps. The master oscillator range is larger than the range possible with the DAC step size, so the OFFSET register is used to select a smaller range of frequencies over which the DAC spans. The prescaler can then be set to divide the master oscillator frequency by 2 x (where x equals 0 to 8) before routing the signal to the output (OUT) pin. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output 0.5%, 1%, 2%, 4%, or 8%. The dither magnitude is controlled by the JS2, JS1, and JS0 bits in the PRESCALER word and enabled with the SPRD pin. Futhermore, the dither rate is controlled by the JS4 and JS3 bits in the PRESCALER word and determines the frequency of the dither. The maximum spectral attenuation occurs when the prescaler is set to 1 and is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This hap- pens because the prescaler’s divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. The external control input, OE, gates the clock output buffer. The PDN pin disables the master oscillator and turns off the clock output for power-sensitive applications*. On power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled. The control registers are programmed through a 2-wire interface and are used to determine the output frequency and settings. Once programmed into EEPROM, since the register settings are NV, the settings only need to be reprogrammed if it is desired to reconfigure the device. *The power-down command must persist for at least two output frequency cycles plus 10µs for deglitching purposes. _____________________________________________________________________ 9 DS1086L 3.3V Spread-Spectrum EconOscillator Table 1. Register Summary REGISTER ADDR MSB PRESCALER PRESCALER DAC (MSB) DAC (LSB) OFFSET ADDR RANGE WRITE EE 02h — 08h — 0Eh 0Dh 37h 3Fh JS4 P1 b9 b1 X1 X1 XX BINARY JS3 P0 b8 b0 X1 X1 XX JS2 XX b7 X0 X1 X1 XX JS1 JS0 XX XX b6 b5 X0 X0 b4 b3 X1 WC b4 b3 NO DATA LO/HiZ XX b4 X0 b2 A2 b2 P3 XX b3 X0 b1 A1 b1 LSB FACTORY DEFAULT ACCESS P2 XX b2 X0 b0 A0 b0 0110000 0 00XXXXX 01111101b 00000000b 111- ----b 11110000b xxx- - - - - b R/W R/W R/W R/W R/W R/W R — — X0 = Don’t care, reads as zero. X1 = Don’t care, reads as one. XX = Don’t care, reads indeterminate. X = Don’t care. See the Example Frequency Calculations section for a more in-depth look at using the registers. Table 2. Offset Settings OFFSET FREQUENCY RANGE (MHz) ________________Register Definitions OS - 6 30.7 to 35.8 OS - 5 33.3 to 38.4 OS - 4 35.8 to 41.0 OS - 3 38.4 to 43.5 The DS1086L registers are used to program the output frequency, dither percent, dither rate, and 2-wire address. Table 1 shows a summary of the registers and detailed descriptions follow below. OS - 2 41.0 to 46.1 PRESCALER (02h) OS - 1 43.5 to 48.6 OS* 46.1 to 51.2 OS + 1 48.6 to 53.8 OS + 2 51.2 to 56.3 OS + 3 53.8 to 58.9 OS + 4 56.3 to 61.4 OS + 5 58.9 to 64.0 OS + 6 61.4 to 66.6 The PRESCALER word is a two-byte value containing control bits for the prescaler (P3 to P0), output control (Lo/HiZ), the jitter rate (JS4 to JS3), as well as control bits for the jitter percentage (JS2 to JS0). The PRESCALER word is read and written using two-byte reads and writes beginning at address 02h. JS4 to JS3: Jitter Rate. This is the frequency of the triangle wave generator and the modulation frequency that the output is dithered. It can be programmed to the master oscillator frequency, fOSC, divided by either 8192, 4096, or 2048. *Factory default setting. OS is the integer value of the five LSBs of the RANGE register. The output frequency is determined by the following equation: fOUTPUT = JS4 JS3 JITTER RATE 0 0 fOSC/8192 0 1 fOSC/4096 (default) 1 0 fOSC/2048 (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE × 5 kHz STEP SIZE) PRESCALER where: min frequency of selected OFFSET range is the lowest frequency (shown in Table 2 for the corresponding offset). DAC value is the value of the DAC register (0 to 1023). Prescaler is the value of 2x where x = 0 to 8. 10 ____________________________________________________________________ 3.3V Spread-Spectrum EconOscillator JS2 JS1 JS0 JITTER % 0 0 0 0.5 0 0 1 1 0 1 0 2 1 0 0 4 1 1 1 8 required to program new master oscillator frequencies shown in Table 2. The read-only backup is important because the offset register is EEPROM and is likely to be overwritten. ADDR (0Dh) Lo/HiZ: Output Low or High-Z. This bit determines the state of the output pin when the device is in powerdown mode or when the output is disabled. If Lo/HiZ = 0, the output is HiZ when in power-down or disabled. If Lo/HiZ = 1, the output is held low when in power-down or disabled. P3 to P0: Prescaler Divider. These bits divide the master oscillator frequency by 2x, where x is P3 to P0 and can be from 0 to 8. Any prescaler value entered greater than 8 decodes as 8. DAC (08h) B9 to B0: DAC Setting. The DAC word sets the master oscillator frequency to a specific value within the current offset range. Each step of the DAC changes the master oscillator frequency by 5kHz. The DAC word is read and written using two-byte reads and writes beginning at address 08h. WC: EEPROM Write Control Bit. The WC bit enables/disables the automatic writing of registers to EEPROM. This prevents EEPROM wear out and eliminates the EEPROM write cycle time. If WC = 0 (default), register writes are automatically written to EEPROM. If WC = 1, register writes are stored in SRAM and only written into EEPROM when the user sends a WRITE EE command. If power is cycled to the device, then the last value stored in EEPROM is recalled. WC = 1 is ideal for applications that frequently modify the frequency/registers. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. A2 to A0: Device Address Bits. These bits determine the 2-wire slave address of the device. They allow up to eight devices to be attached to the same 2-wire bus and to be addressed individually. WRITE EE Command (3Fh) This command can be used when WC = 1 (see the WC bit in ADDR register) to transfer all registers from SRAM into EEPROM. The time required to store the values is one EEPROM write cycle time. This command is not needed if WC = 0. OFFSET (0Eh) B4 to B0: Offset. This value selects the master oscillator frequency range that can be generated by varying the DAC word. Valid frequency ranges are shown in Table 2. Correct operation of the device is not guaranteed for values of OFFSET not shown in the table. The default offset value (OS) is factory trimmed and can vary from device to device. Therefore, to change frequency range, OS must be read so the new offset value can be calculated relative to the default. For example, to generate a master oscillator frequency within the largest range (61.4MHz to 66.6MHz), Table 2 indicates that the OFFSET must be programmed to OS + 6. This is done by reading the RANGE register and adding 6 to the value of bits B4 to B0. The result is then written into bits B4 to B0 of the OFFSET register. Additional examples are provided in the Example Frequency Calculations section. RANGE (37h) B4 to B0: Range: This read-only, factory programmed value is a copy of the factory default offset (OS). OS is ____________________________________________________________________ 11 DS1086L JS2 to JS0: Jitter Percentage. These three bits select the amount of jitter in percent. The SPRD pin must be a logic high for the jitter to be enabled. Bit combinations not shown are reserved. DS1086L 3.3V Spread-Spectrum EconOscillator Example Frequency Calculations Example #1: Calculate the register values needed to generate a desired output frequency of 11.0592MHz. Since the desired frequency is not within the valid master oscillator range of 33.3MHz to 66.6MHz, the prescaler must be used. Valid prescaler values are 2x where x equals 0 to 8 (and x is the value that is programmed into the P3 to P0 bits of the PRESCALER register). Equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler. f fDESIRED = MASTER OSCILLATOR prescaler fMASTER OSCILLATOR = (1) 2X By trial and error, x is incremented from 0 to 8 in Equation 2, finding values of x that yield master oscillator frequencies within the range of 33.3MHz to 66.6MHz. Equation 2 shows that a prescaler of 4 (x = 2) and a master oscillator frequency of 44.2368MHz generates our desired frequency. Writing 0080h to the PRESCALER register sets the PRESCALER to 4. Be aware that other settings also reside in the PRESCALER register. fMASTER OSCILLATOR = fDESIRED x prescaler = fDESIRED x 2X fMASTER OSCILLATOR = 11.0592MHz x 22 = 44.2368MHz (2) Once the target master oscillator frequency has been calculated, the value of offset can be determined. Using Table 2, 44.2368MHz falls within both OS - 1 and OS - 2. However, choosing OS - 1 would be a poor choice since 44.2368MHz is so close to OS - 1’s minimum frequency. On the other hand, OS - 2 is ideal since 44.2368MHz is close to the center of OS - 2’s frequency span. Before the OFFSET register can be programmed, the default value of offset (OS) must be read from the RANGE register (last five bits). In this example, 12h (18 decimal) was read from the RANGE register. OS - 2 for this case is 10h (16 decimal). This is the value that is written to the OFFSET register. Finally, the two-byte DAC value needs to be determined. Since OS - 2 only sets the range of frequencies, the DAC selects one frequency within that range as shown in Equation 3. Valid values of DAC are 0 to 1023 (decimal) and 5kHz is the step size. Equation 4 is derived from rearranging Equation 3 and solving for the DAC value. DAC VALUE = 12 (4) 5kHz STEP SIZE (44.2368MHz − 41.0MHz) 5kHz STEP SIZE = 647.36 ≈ 647 (decimal) DAC VALUE = Since the two-byte DAC register is left justified, 647 is converted to hex (0287h) and bit-wise shifted left six places. The value to be programmed into the DAC register is A1C0h. In summary, the DS1086L is programmed as follows: PRESCALER = 0080h OFFSET = OS - 2 or 10h (if range was read as 12h) DAC = A1C0h Notice that the DAC value was rounded. Unfortunately, this means that some error is introduced. To calculate how much error, a combination of Equation 1 and Equation 3 is used to calculate the expected output frequency. See Equation 5. (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 5kHz STEP SIZE) fOUTPUT = prescaler (41.0MHz) + (647 x 5kHz) fOUTPUT = = 4 44.235MHz = 11.05875MHz 4 fMASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC value x 5kHz) (fMASTER OSCILLATOR − MIN FREQUENCY OF SELECTED OFFSET RANGE) (3) ____________________________________________________________________ (5) 3.3V Spread-Spectrum EconOscillator DS1086L SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK START CONDITION 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED STOP CONDITION OR REPEATED START CONDITION Figure 4. 2-Wire Data Transfer Protocol The expected output frequency is not exactly equal to the desired frequency of 11.0592MHz. The difference is 450Hz. In terms of percentage, Equation 6 shows that the expected error is 0.004%. The expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables. %ERROREXPECTED = %ERROREXPECTED = fDESIRED − fEXPECTED × 100 fDESIRED (6) 11.0592MHz − 11.05875MHz × 100 11.0592MHz 450Hz = × 100 = 0.004% 11.0592MHz Example #2: Calculate the register values needed to generate a desired output frequency of 50MHz. Since the desired frequency is already within the valid master oscillator frequency range, the prescaler is set to divide by 1, and hence, PRESCALER = 0000h (currently ignoring the other setting). (7) fMASTER OSCILLATOR = 50.0MHz x 20 = 50.0MHz Finally, the DAC value is calculated as shown in Equation 8. (8) DAC VALUE = (50.0MHz − 48.6MHz) = 280.00 (decimal) 5kHz STEP SIZE The result is then converted to hex (0118h) and then left-shifted, resulting in 4600h to be programmed into the DAC register. In summary, the DS1086L is programmed as follows: PRESCALER = 0000h OFFSET = OS + 1 or 13h (if RANGE was read as 12h) DAC = 4600h fOUTPUT = (48.6MHz) + (280 × 5kHz) = 20 50.0MHz = 50.0MHz 1 (9) Since the expected output frequency is equal to the desired frequency, the calculated error is 0%. Next, looking at Table 2, OS + 1 provides a range of frequencies centered around the desired frequency. To determine what value to write to the OFFSET register, the RANGE register must first be read. Assuming 12h was read in this example, 13h (OS + 1) is written to the OFFSET register. ____________________________________________________________________ 13 DS1086L 3.3V Spread-Spectrum EconOscillator MSB LSB 1 1 A1 A0 R/W DEVICE ADDRESS REA D/W DEVICE IDENTIFIER A2 IT 0 RIT EB 1 Figure 5. Slave Address SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 6. 2-Wire AC Characteristics _______2-Wire Serial Port Operation 2-Wire Serial Data Bus The DS1086L communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1086L operates as a slave on the 2wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figures 4 and 6): • Data transfer can be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes 14 in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP con- ____________________________________________________________________ 3.3V Spread-Spectrum EconOscillator 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1086L can operate in the following two modes: Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1086L while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Slave Address Figure 5 shows the first byte sent to the device. It includes the device identifier, device address, and the R/W bit. The device address is determined by the ADDR register. Registers/Commands See Table 1 for the complete list of registers/commands and Figure 7 for an example of using them. __________Applications Information Power-Supply Decoupling To achieve the best results when using the DS1086L, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to pins 3 and 4 as possible. Stand-Alone Mode SCL and SDA cannot be left floating when they are not used. If the DS1086L never needs to be programmed in-circuit, including during production testing, SDA and SCL can be tied high. The SPRD pin must be tied either high or low. ____________________________________________________________________ 15 DS1086L ditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1086L works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1086L EEPROM is being written to, it is not able to perform additional responses. In this case, the slave DS1086L sends a not acknowledge to any data transfer request made by the master. It resumes normal operation when the EEPROM operation is complete. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. DS1086L 3.3V Spread-Spectrum EconOscillator TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 LSB 0 1 1 A2* A1* A0* R/W DEVICE IDENTIFIER DEVICE ADDRESS MSB SLAVE ACK READ/ WRITE b7 b5 b4 b3 b2 b1 b0 SLAVE ACK b7 LSB b6 COMMAND/REGISTER ADDRESS EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 0Eh SLAVE SLAVE A) SINGLE BYTE WRITE START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 1 1 1 0 ACK -WRITE OFFSET REGISTER B0h B) SINGLE BYTE READ -READ OFFSET REGISTER MSB LSB b6 START 1 0 1 1 0 0 0 0 0Eh SLAVE SLAVE 00001110 ACK ACK C) TWO BYTE WRITE -WRITE DAC REGISTER B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK D) TWO BYTE READ -READ DAC REGISTER B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK b5 b4 b3 b2 b1 b0 SLAVE ACK STOP DATA DATA OFFSET SLAVE ACK STOP DATA B1h REPEATED START 10110001 SLAVE ACK DAC LSB B1h REPEATED START OFFSET MASTER NACK STOP DATA DATA DAC MSB SLAVE ACK 10110001 SLAVE ACK STOP DATA SLAVE ACK DAC MSB DATA MASTER ACK DAC LSB MASTER NACK STOP *THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER. Figure 7. 2-Wire Transactions Chip Topology TRANSISTOR COUNT: 9052 SUBSTRATE CONNECTED TO GROUND Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.