19-5331; Rev 0; 6/10 Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers The MAX5974_ provide control for wide-input-voltage, active-clamped, current-mode PWM, forward converters in Power-over-Ethernet (PoE) powered device (PD) applications. The MAX5974A/MAX5974C are well-suited for universal or telecom input range, while the MAX5974B/ MAX5974D also accommodate low input voltage down to 10.5V. The devices include several features to enhance supply efficiency. The AUX driver recycles magnetizing current instead of wasting it in a dissipative clamp circuit. Programmable dead time between the AUX and main driver allows for zero-voltage switching (ZVS). Under lightload conditions, the devices reduce the switching frequency (frequency foldback) to reduce switching losses. The MAX5974A/MAX5974B feature unique circuitry to achieve output regulation without using an optocoupler, while the MAX5974C/MAX5974D utilize the traditional optocoupler feedback method. An internal error amplifier with a 1% reference is very useful in nonisolated design, eliminating the need for an external shunt regulator. The devices feature a unique feed-forward maximum duty-cycle clamp that makes the maximum clamp voltage during transient conditions independent of the line voltage, allowing the use of a power MOSFET with lower breakdown voltage. The programmable frequency dithering feature provides low-EMI, spread-spectrum operation. The MAX5974_ are available in 16-pin TQFN-EP packages and are rated for operation over the -40°C to +85°C temperature range. Features S Peak Current-Mode Control, Active-Clamped Forward PWM Controller S Regulation Without Optocoupler (MAX5974A/ MAX5974B) S Internal 1% Error Amplifier S 100kHz to 600kHz Programmable Q8% Switching Frequency, Synchronization Up to 1.2MHz S Programmable Frequency Dithering for Low-EMI, Spread-Spectrum Operation S Programmable Dead Time, PWM Soft-Start, Current Slope Compensation S Programmable Feed-Forward Maximum DutyCycle Clamp, 80% Maximum Limit S Frequency Foldback for High-Efficiency LightLoad Operation S Internal Bootstrap UVLO with Large Hysteresis S 100µA (typ) Startup Supply Current S Fast Cycle-by-Cycle Peak Current-Limit, 35ns Typical Propagation Delay S 115ns Current-Sense Internal Leading-Edge Blanking S Output Short-Circuit Protection with Hiccup Mode S Reverse Current Limit to Prevent Transformer Saturation Due to Reverse Current S 3mm x 3mm, Lead-Free, 16-Pin TQFN-EP Applications PoE IEEE® 802.3af/at Powered Devices High-Power PD (Beyond the 802.3af/at Standard) Active-Clamped Forward DC-DC Converters IP Phones Wireless Access Nodes Security Cameras Ordering Information UVLO THRESHOLD (V) FEEDBACK MODE MAX5974AETE+ PART TOP MARK +AHY 16 TQFN-EP* PIN-PACKAGE 20 Sample/Hold MAX5974BETE+** +AHZ 16 TQFN-EP* 10 Sample/Hold MAX5974CETE+ +AIA 16 TQFN-EP* 20 Continuously Connected MAX5974DETE+** +AIB 16 TQFN-EP* 10 Continuously Connected Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product—Contact factory for availability. IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5974A/MAX5974B/MAX5974C/MAX5974D General Description MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers ABSOLUTE MAXIMUM RATINGS IN to GND...............................................................-0.3V to +24V EN, NDRV, AUXDRV to GND......................-0.3V to (VIN + 0.3V) RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC to GND..................................................................-0.3V to +6V FB to GND (MAX5974A/MAX5974B only)...................-6V to +6V FB to GND (MAX5974C/MAX5974D only)...............-0.3V to +6V CS, CSSC to GND....................................................-0.8V to +6V PGND to GND.......................................................-0.3V to +0.3V Maximum Input/Output Current (continuous) NDRV, AUXDRV.............................................................100mA NDRV, AUXDRV (pulsed for less than 100ns)................... Q1A Continuous Power Dissipation (TA = +70NC) (Note 1) 16-Pin TQFN (derate 20.8mW/NC above +70NC)........1666mW Junction-to-Case Thermal Resistance (BJC) (Note 1) 16-Pin TQFN....................................................................7NC/W Junction-to-Ambient Thermal Resistance (BJA) (Note 1) 16-Pin TQFN..................................................................48NC/W Operating Temperature Range........................... -40NC to +85NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX5974A/ MAX5974C 19.1 19.8 20.4 MAX5974B/ MAX5974D 9.4 9.8 10.25 6.65 7 7.35 V UNDERVOLTAGE LOCKOUT/STARTUP (IN) Bootstrap UVLO Wakeup Level Bootstrap UVLO Shutdown Level IN Supply Current in Undervoltage Lockout IN Supply Current After Startup VINUVR VIN rising V VINUVF VIN falling ISTART VIN = +18V (for MAX5974A/ MAX5974C); VIN = +9V (for MAX5974B/MAX5974D), when in bootstrap UVLO 100 150 FA VIN = +12V 1.8 3 mA IC ENABLE (EN) Enable Threshold Input Current VENR VEN rising 1.17 1.215 1.26 VENF VEN falling 1.09 1.14 1.19 IEN 1 V FA OSCILLATOR (RT) RT Bias Voltage VRT NDRV Switching Frequency Range fSW 1.23 NDRV Switching Frequency Accuracy Maximum Duty Cycle 2 DMAX fSW = 250kHz V 100 600 kHz -8 +8 % 82 % 79 80 Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYNCHRONIZATION (SYNC) Synchronization Logic-High Input VIH-SYNC 2.91 Synchronization Pulse Width Synchronization Frequency Range V 50 1.1 x fSW fSYNCIN Maximum Duty Cycle During Synchronization ns 2x fSW DMAX x fSYNC/ fSW kHz % DITHERING RAMP GENERATOR (DITHER) Charging Current VDITHER = 0V 45 50 55 FA Discharging Current VDITHER = 2.2V 43 50 57 FA Ramp’s High Trip Point 2 V Ramp’s Low Trip Point 0.4 V SOFT-START AND RESTART (SS) Charging Current ISS-CH ISS-D Discharging Current Discharge Threshold to Disable Hiccup and Restart Minimum Restart Time During Hiccup Mode Normal Operating High Voltage Duty-Cycle Control Range ISS-DH 9.5 10 10.5 FA VSS = 2V, normal shutdown 0.65 1.34 2 mA (VEN < VENF or VIN < VINUVF), VSS = 2V, hiccup mode discharge for tRESTART (Note 3) 1.6 2 2.4 FA VSS-DTH 0.15 V tRSTRT-MIN 1024 Clock Cycles VSS-HI VSS-DMAX 5 DMAX (typ) = (VSS-DMAX/2.46V) 0 V 2 V nA DUTY-CYCLE CLAMP (DCLMP) DCLMP Input Current Duty-Cycle Control Range IDCLMP VDCLMP-R VDCLMP = 0 to 5V DMAX (typ) = 1 - (VDCLMP/2.43V) -100 0 +100 VDCLMP = 0.5V 73 75.4 77.5 VDCLMP = 1V 54 56 58 VDCLMP = 2V 14.7 16.5 18.3 % NDRV DRIVER Pulldown Impedance RNDRV-N INDRV (sinking) = 100mA 1.9 3.4 I Pullup Impedance RNDRV-P INDRV (sourcing) = 50mA 4.7 8.3 I Peak Sink Current Peak Source Current 1 A 0.65 A Fall Time tNDRV-F CNDRV = 1nF 14 ns Rise Time tNDRV-R CNDRV = 1nF 27 ns 3 MAX5974A/MAX5974B/MAX5974C/MAX5974D ELECTRICAL CHARACTERISTICS (continued) MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers ELECTRICAL CHARACTERISTICS (continued) (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AUXDRV DRIVER Pulldown Impedance RAUX-N IAUXDRV (sinking) = 50mA 4.3 7.7 I Pullup Impedance RAUX-P IAUXDRV (sourcing) = 25mA 10.6 18.9 I Peak Sink Current 0.5 Peak Source Current 0.3 A A Fall Time tAUX-F CAUXDRV = 1nF 24 ns Rise Time tAUX-R CAUXDRV = 1nF 45 ns 1.215 V DEAD-TIME PROGRAMMING (DT) DT Bias Voltage VDT NDRV to AUXDRV Delay (Dead Time) tDT From NDRV falling to AUXDRV falling RDT = 10kI AUXDRV rising to NDRV rising RDT = 10kI RDT = 100kI RDT = 100kI 40 410 ns 300 350 310 360 420 375 393 410 mV -118 -100 -88 mV 40 ns CURRENT-LIMIT COMPARATORS (CS) Cycle-by-Cycle Peak Current-Limit Threshold VCS-PEAK Cycle-by-Cycle Reverse Current-Limit Threshold VCS-REV Current-Sense Blanking Time for Reverse Current Limit tCS-BLANKREV Number of Consecutive Peak Current-Limit Events to Hiccup NHICCUP Current-Sense Leading-Edge Blanking Time tCS-BLANK Propagation Delay from Comparator Input to NDRV tPDCS Minimum On-Time Turns AUXDRV off for the remaining cycle if reverse current limit is exceeded From AUXDRV falling edge 115 ns 8 Events From NDRV rising edge 115 ns From CS rising (10mV overdrive) to NDRV falling (excluding leading-edge blanking) 35 ns tON-MIN 100 150 200 ns 47 52 58 FA SLOPE COMPENSATION (CSSC) Slope Compensation Current Ramp Height Current ramp’s peak added to CSSC input per switching cycle PWM COMPARATOR Comparator Offset Voltage VPWM-OS VCOMP - VCSSC 1.35 1.7 2 V Current-Sense Gain ACS-PWM DVCOMP/DVCSSC (Note 4) 3.1 3.33 3.6 V/V Current-Sense Leading-Edge Blanking Time Comparator Propagation Delay 4 tCSSC-BLANK tPWM From NDRV rising edge 115 ns Change in VCSSC = 10mV (including internal leading-edge blanking) 150 ns Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX5974A/ MAX5974B 1.5 1.52 1.54 MAX5974C/ MAX5974D 1.202 MAX5974A/ MAX5974B -250 +250 MAX5974C/ MAX5974D -500 +100 UNITS ERROR AMPLIFIER FB Reference Voltage FB Input Bias Current Voltage Gain Transconductance Transconductance Bandwidth VREF IFB VFB when ICOMP = 0, VCOMP = 2.5V VFB = 0 to 1.75V AEAMP Source Current Sink Current Open loop (typical gain = 1) -3dB frequency 1.215 80 MAX5974A/ MAX5974B 1.8 MAX5974C/ MAX5974D 1.8 2.55 dB 3.2 mS 2.66 MAX5974A/ MAX5974B 2 MAX5974C/ MAX5974D 30 VFB = 1V, VCOMP = 2.5V VFB = 1.75V, VCOMP = 1V 1.227 nA gM BW V 3.5 MHz 300 375 455 FA 300 375 455 FA FREQUENCY FOLDBACK (FFB) VCSAVG-to-FFB Comparator Gain FFB Bias Current NDRV Switching Frequency During Foldback IFFB fSW-FB 10 VFFB = 0V, VCS = 0V (not in FFB mode) 26 30 V/V 33 fSW/2 FA kHz Note 2: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. Note 3: See the Output Short-Circuit Protection with Hiccup Mode section. Note 4: The parameter is measured at the trip point of latch with VFB = 0V. Gain is defined as DVCOMP/DVCSSC for 0.15V < DVCSSC < 0.25V. 5 MAX5974A/MAX5974B/MAX5974C/MAX5974D ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.) 19.8 19.7 19.6 9.9 9.8 9.7 9.6 19.5 9.5 -15 10 35 60 85 7.2 7.1 7.0 6.9 6.8 -15 -40 10 35 60 85 -40 -15 60 TEMPERATURE (°C) EN RISING THRESHOLD vs. TEMPERATURE EN FALLING THRESHOLD vs. TEMEPRATURE UVLO SHUTDOWN CURRENT vs. TEMPERATURE 1.214 1.148 1.147 1.146 1.145 120 MAX5974A/MAX5974C 100 80 1.144 MAX5974B/MAX5974D 1.143 1.210 60 1.142 -15 10 35 60 85 -15 -40 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5974A/MAX5974C) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5974B/MAX5974D) SUPPLY CURRENT vs. SWITCHING FREQUENCY 1000 TA = -40°C 100 2 4 6 8 10 12 14 16 18 20 22 SUPPLY VOLTAGE (V) 1.6 1.2 0.8 0 10 0 2.0 0.4 TA = -40°C 10 2.4 85 MAX5974A/B/C/D toc09 TA = +85°C SUPPLY CURRENT (mA) 100 MAX5974A/B/C/D toc08 1000 10,000 SUPPLY CURRENT (µA) TA = +85°C MAX5974A/B/C/D toc07 TEMPERATURE (°C) 10,000 85 MAX5974A/B/C/D toc06 1.149 140 UVLO CURRENT (µA) 1.216 1.150 MAX5974A/B/C/D toc05 MAX5974A/B/C/D toc04 1.218 1.212 6 35 TEMPERATURE (°C) 1.220 -40 10 TEMPERATURE (°C) EN FALLING THRESHOLD (V) -40 EN RISING THRESHOLD (V) 10.0 7.3 MAX5974A/B/C/D toc03 19.9 MAX5974B/MAX5974D IN UVLO SHUTDOWN LEVEL 20.0 10.1 IN UVLO SHUTDOWN LEVEL vs. TEMPERATURE MAX5974A/B/C/D toc02 MAX5974A/MAX5974C IN UVLO WAKE-UP LEVEL (V) IN UVLO WAKE-UP LEVEL (V) 20.1 IN UVLO WAKE-UP LEVEL vs. TEMPERATURE MAX5974A/B/C/D toc01 IN UVLO WAKE-UP LEVEL vs. TEMPERATURE SUPPLY CURRENT (µA) MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers 0 2 4 6 8 10 12 14 16 18 20 22 SUPPLY VOLTAGE (V) 0 100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers SWITCHING FREQUENCY vs. RRT VALUE 10.03 10.02 10.01 10.00 9.99 -15 10 35 60 248 247 246 10 85 244 100 -40 35 60 FREQUENCY DITHERING vs. RDITHER MAXIMUM DUTY CYCLE vs. SWITCHING FREQUENCY MAXIMUM DUTY CYCLE vs. TEMPERATURE 4 2 81 80 79 78 77 80.9 76 400 500 600 700 800 900 80.7 80.6 80.5 80.4 80.2 0 1000 80.8 80.3 75 0 100 200 300 400 500 600 700 800 -40 -15 10 35 60 SWITCHING FREQUENCY (kHz) TEMPERATURE (°C) MAXIMUM DUTY CYCLE vs. SYNC FREQUENCY MAXIMUM DUTY CYCLE vs. VSS MAXIMUM DUTY CYCLE vs. VDCLMP 25 20 15 10 80 70 60 50 40 30 20 5 10 0 0 300 350 400 SYNC FREQUENCY (kHz) 450 500 100 85 MAX5974A/B/C/D toc18 90 90 MAXIMUM DUTY CYCLE (%) 30 MAX5974A/B/C/D toc17 35 100 MAXIMUM DUTY CYCLE (%) MAX5974A/B/C/D toc16 RDITHER (kΩ) VSS = 0.5V 85 MAX5974A/B/C/D toc15 MAX5974A/B/C/D toc14 82 81.0 MAXIMUM DUTY CYCLE (%) 6 83 MAXIMUM DUTY CYCLE (%) MAX5974A/B/C/D toc13 8 250 10 TEMPERATURE (°C) 10 300 -15 RRT VALUE (kΩ) 12 40 249 TEMPERATURE (°C) 14 45 250 245 10 -40 FREQUENCY DITHERING (%) 251 9.98 9.97 MAXIMUM DUTY CYCLE (%) 100 252 MAX5974A/B/C/D toc12 10.04 MAX5974A/B/C/D toc11 10.05 1000 SWITCHING FREQUENCY (kHz) MAX5974A/B/C/D toc10 SOFT-START CHARGING CURRENT (µA) 10.06 SWITCHING FREQUENCY vs. TEMPERATURE SWITCHING FREQUENCY (kHz) SOFT-START CHARGING CURRENT vs. TEMPERATURE 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 VSS (V) 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 VDCLMP (V) 7 MAX5974A/MAX5974B/MAX5974C/MAX5974D Typical Operating Characteristics (continued) (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.) 250 200 150 94 92 100 50 90 0 88 10 20 30 40 50 60 70 80 396 395 394 393 392 391 390 389 388 -40 90 100 397 -15 10 35 60 85 -40 110 -15 10 35 60 RDT VALUE (kΩ) TEMPERATURE (°C) TEMPERATURE (°C) REVERSE CURRENT-LIMIT THRESHOLD vs. TEMPERATURE SLOPE COMPENSATION CURRENT vs. TEMPERATURE NDRV MINIMUM ON-TIME vs. TEMPERATURE -101 -102 -103 -104 -105 -106 -107 -15 10 35 60 52.5 52.0 51.5 51.0 160 155 150 140 -40 -15 10 35 60 85 -40 -15 10 35 TEMPERATURE (°C) TEMPERATURE (°C) CURRENT-SENSE GAIN vs. TEMPERATURE FEEDBACK VOLTAGE vs. TEMPERATURE FEEDBACK VOLTAGE vs. TEMPERATURE 3.37 3.36 3.35 3.34 3.33 1.219 1.218 1.217 1.216 1.215 1.214 1.213 3.32 1.212 3.31 1.211 3.30 MAX5974C/MAX5974D 10 35 TEMPERATURE (°C) 60 85 85 60 85 1.522 1.521 1.520 1.519 1.518 1.517 1.210 -15 60 MAX5974A/B/C/D toc27 3.38 1.220 FEEDBACK VOLTAGE (V) MAX5974A/B/C/D toc25 3.39 MAX5974A/B/C/D toc26 TEMPERATURE (°C) 3.40 -40 165 145 50.5 50.0 85 FEEDBACK VOLTAGE (V) -40 53.0 85 MAX5974A/B/C/D toc24 -100 53.5 170 NDRV MINIMUM ON-TIME (ns) -99 54.0 MAX5974A/B/C/D toc23 -98 SLOPE COMPENSATION CURRENT (mA) MAX5974A/B/C/D toc22 -97 REVERSE CURRENT-LIMIT THRESHOLD (mV) 96 MAX5974A/B/C/D toc21 98 398 PEAK CURRENT-LIMIT THRESHOLD (mV) 100 DEAD TIME (ns) 300 MAX5974A/B/C/D toc20 350 DEAD TIME (ns) 102 MAX5974A/B/C/D toc19 400 8 PEAK CURRENT-LIMIT THRESHOLD vs. TEMPERATURE DEAD TIME vs. TEMPERATURE DEAD TIME vs. RDT VALUE CURRENT-SENSE GAIN (V/V) MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers -40 -15 10 35 TEMPERATURE (°C) 60 85 1.516 -40 -15 10 35 TEMPERATURE (°C) Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers TRANSCONDUCTANCE HISTOGRAM (MAX5974A/MAX5974B) 2.6 20 2.5 2.4 MAX5974A/MAX5974B 15 20 N (%) 2.7 25 MAX5974A/B/C/D toc29 MAX5974C/MAX5974D N (%) TRANSCONDUCTANCE (mS) 2.9 2.8 25 MAX5974A/B/C/D toc28 3.0 TRANSCONDUCTANCE HISTOGRAM (MAX5974C/MAX5974D) MAX5974A/B/C/D toc30 TRANSCONDUCTANCE vs. TEMPERATURE 15 10 10 5 5 2.3 2.2 2.1 2.0 -40 -15 10 35 60 0 85 0 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64 2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76 TRANSCONDUCTANCE (mS) TRANSCONDUCTANCE (mS) TEMPERATURE (°C) ENABLE RESPONSE SHUTDOWN RESPONSE MAX5974A/B/C/D toc31 MAX5974C MAX5974A/B/C/D toc32 VEN 2V/div VEN 2V/div VNDRV 20V/div VNDRV 10V/div VAUXDRV 20V/div VAUXDRV 10V/div VOUT 5V/div VOUT 5V/div 1ms/div 4µs/div SHUTDOWN RESPONSE VSS RAMP RESPONSE MAX5974A/B/C/D toc33 MAX5974A/B/C/D toc34 VEN 2V/div VSS 2V/div VNDRV 10V/div VNDRV 10V/div VAUXDRV 10V/div VAUXDRV 10V/div VOUT 5V/div 100µs/div 10µs/div 9 MAX5974A/MAX5974B/MAX5974C/MAX5974D Typical Operating Characteristics (continued) (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.) MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Typical Operating Characteristics (continued) (VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.) VDCLMP RAMP RESPONSE NDRV 10% TO 90% RISE TIME MAX5974A/B/C/D toc35 NDRV 90% TO 10% FALL TIME MAX5974A/B/C/D toc36 VDCLMP 2V/div MAX5974A/B/C/D toc37 0ns 27.6ns VNDRV 2V/div VNDRV 10V/div VAUXDRV 10V/div VNDRV 2V/div 13.8ns 0ns 10µs/div 10ns/div AUXDRV 10% TO 90% RISE TIME 10ns/div AUXDRV 90% TO 10% FALL TIME MAX5974A/B/C/D toc38 PEAK NDRV CURRENT MAX5974A/B/C/D toc39 MAX5974A/B/C/D toc40 PEAK SOURCE CURRENT 0ns 45.6ns VAUXDRV 2V/div VAUXDRV 2V/div INDRV 0.5A/div 21ns 0ns PEAK SINK CURRENT 10ns/div 10ns/div PEAK AUXDRV CURRENT 200ns/div SHORT-CIRCUIT BEHAVIOR MAX5974A/B/C/D toc41 MAX5974A/B/C/D toc42 VIN PEAK SOURCE CURRENT IAUXDRV 0.2A/div VNDRV ILX PEAK SINK CURRENT 400ns/div 10 40ms/div Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers AUXDRV NDRV PGND CS TOP VIEW 12 11 10 9 IN 13 MAX5974A MAX5974B MAX5974C MAX5974D EN 14 DCLMP 15 EP 2 3 4 FFB DT 1 RT + DITHER/ SYNC SS 16 8 CSSC 7 GND 6 FB 5 COMP THIN QFN Pin Description PIN NAME FUNCTION 1 DT 2 DITHER/ SYNC Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency operation, connect a capacitor from DITHER to GND and a resistor from DITHER to RT. To synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to the synchronization pulse. 3 RT Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to GND to set the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the resistor value for the desired oscillator frequency. 4 FFB Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the output average current threshold below which the converter folds back the switching frequency to 1/2 of its original value. Connect to GND to disable frequency foldback. 5 COMP Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and connected to the inverting input of the PWM comparator. Dead-Time Programming Resistor Connection. Connect resistor RDT from DT to GND to set the desired dead time between the NDRV and AUXDRV signals. See the Dead Time section to calculate the resistor value for a particular dead time. 11 MAX5974A/MAX5974B/MAX5974C/MAX5974D Pin Configuration Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D Pin Description (continued) 12 PIN NAME FUNCTION 6 FB 7 GND Signal Ground 8 CSSC Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs the amount of slope compensation. See the Programmable Slope Compensation section. 9 CS 10 PGND Power Ground. PGND is the return path for gate-driver switching currents. 11 NDRV Main Switch Gate-Driver Output 12 AUXDRV Transconductance Amplifier Inverting Input Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle current limit. Peak current-limit trip voltage is 400mV and reverse current-limit trip voltage is -100mV. pMOS Active Clamp Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse transformer for synchronous flyback application. 13 IN Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power supplies. When the enable input EN is used to program a UVLO level for the power source, connect a zener diode between IN and PGND to ensure that VIN is always clamped below its absolute maximum rating of 24V. 14 EN Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode when the voltage on EN is below VENF. When the voltage on EN is above VENR, the device checks for other enable conditions. See the Enable Input section for more information about interfacing to EN. 15 DCLMP Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistive divider between the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum duty cycle (DMAX) of the converter inversely proportional to the input supply voltage, so that the MOSFET remains protected during line transients. 16 SS Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program the soft-start period. This capacitor also determines hiccup mode current-limit restart time. A resistor from SS to GND can also be used to set the DMAX below 75%. — EP Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. 1 3 DT RT SYNC PGND DRIVER 0.5A/-0.3A VC PGND DRIVER 1A/-0.65A 4 2 7 10 FFB DITHER/ SYNC GND PGND VB VB AUXDRV NDRV OSCILLATOR -50µA 50µA/ 90µA 30µA/ 15 20% < DMAX < 80% 12 AUXDRV DCLMP 11 NDRV FFB COMP SS DEAD TIME DEAD-TIME CONTROL 2V/400mV VCSAVG 10X POK NDRV BLANKING PULSE REVERSE ILIM LIMIT TURNS OFF AUX IMMEDIATELY DRIVER LOGIC VB POK VSS < 150mV R S 5V REGULATOR MAX5974A MAX5974B QCLR QSET ENABLE COUNT 8 EVENTS THERMAL SHUTDOWN PWM COMP PEAK ILIM COMP 1.23V R1 VB 115ns BLANKING 115ns BLANKING 2 x R1 400mV -100mV UVLO 2µA 1.52V SLOPE COMPENSATION LOW-POWER UVLO VINUVR = 20V (MAX5974A) VINUVR = 10V (MAX5974B) VINUVF = 7V gM VB VB POK S/H 2mA 10µA 14 EN 13 IN 6 FB 5 COMP 8 CSSC 9 CS 16 SS Block Diagrams 13 MAX5974A/MAX5974B/MAX5974C/MAX5974D VC HICCUP LATCH REVERSE ILIM COMP VB Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers 14 1 3 DT RT SYNC PGND DRIVER 0.5A/-0.3A VC PGND DRIVER 1A/-0.65A 4 2 7 10 FFB DITHER/ SYNC GND PGND VB VB AUXDRV NDRV OSCILLATOR -50µA 50µA/ 90µA 30µA/ 15 20% < DMAX < 80% 12 AUXDRV DCLMP 11 NDRV VC FFB COMP SS DEAD TIME DEAD-TIME CONTROL 2V/400mV VCSAVG 10X POK NDRV BLANKING PULSE REVERSE ILIM LIMIT TURNS OFF AUX IMMEDIATELY DRIVER LOGIC VB POK VSS < 150mV R S 5V REGULATOR MAX5974C MAX5974D QCLR QSET ENABLE COUNT 8 EVENTS REVERSE ILIM COMP HICCUP LATCH THERMAL SHUTDOWN PWM COMP PEAK ILIM COMP 1.23V R1 VB 115ns BLANKING 115ns BLANKING 2 x R1 400mV -100mV UVLO 2µA 1.275V SLOPE COMPENSATION LOW-POWER UVLO VINUVR = 20V (MAX5974C) VINUVR = 10V (MAX5974D) VINUVF = 7V gM VB VB POK VB 2mA 10µA 14 EN 13 IN 6 FB 5 COMP 8 CSSC 9 CS 16 SS MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Block Diagrams (continued) Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers The MAX5974A/MAX5974B/MAX5974C/MAX5974D are optimized for controlling a 25W to 50W active-clamped, self-driven synchronous rectification forward converter in continuous-conduction mode. The main switch gate driver (NDRV) and the active-clamped switch driver (AUXDRV) are sized to optimize efficiency for 25W design. The features-rich devices are ideal for PoE IEEE 802.3af/at-powered devices. The MAX5974A/MAX5974C offer a 20V bootstrap UVLO wake-up level with a 13V wide hysteresis. The low startup and operating currents allow the use of a smaller storage capacitor at the input without compromising startup and hold times. The MAX5974A/MAX5974C are well-suited for universal input (rectified 85V AC to 265V AC) or telecom (-36V DC to -72V DC) power supplies. The MAX5974B/MAX5974D have a UVLO rising threshold of 10V and can accomodate for low-input voltage (12V DC to 24V DC) power sources such as wall adapters. Power supplies designed with the MAX5974A/MAX5974C use a high-value startup resistor, RIN, that charges a reservoir capacitor, CIN (see the Typical Application Circuits). During this initial period, while the voltage is less than the internal bootstrap UVLO threshold, the device typically consumes only 100FA of quiescent current. This low startup current and the large bootstrap UVLO hysteresis help to minimize the power dissipation across RIN even at the high end of the universal AC input voltage (265V AC). Feed-forward maximum duty-cycle clamping detects changes in line conditions and adjusts the maximum duty cycle accordingly to eliminate the clamp voltage’s (i.e., the main power FET’s drain voltage) dependence on the input voltage. For EMI-sensitive applications, the programmable frequency dithering feature allows up to Q10% variation in the switching frequency. This spread-spectrum modulation technique spreads the energy of switching harmonics over a wider band while reducing their peaks, helping to meet stringent EMI goals. The devices include a cycle-by-cycle current limit that turns off the main and AUX drivers whenever the internally set threshold of 400mV is exceeded. Eight consecutive occurrences of current-limit events trigger hiccup mode, which protects external components by halting switching for a period of time (tRSTRT) and allowing the overload current to dissipate in the load and body diode of the synchronous rectifier before soft-start is reattempted. The reverse current-limit feature of the devices turns the AUX driver off for the remaining off period when VCS exceeds the -100mV threshold. This protects the transformer core from saturation due to excess reverse current under some extreme transient conditions. Current-Mode Control Loop The advantages of current-mode control over voltagemode control are twofold. First, there is the feed-forward characteristic brought on by the controller’s ability to adjust for variations in the input voltage on a cycle-by-cycle basis. Second, the stability requirements of the current-mode controller are reduced to that of a single-pole system, unlike the double pole in voltage-mode control. The devices use a current-mode control loop where the scaled output of the error amplifier (COMP) is compared to a slope-compensated current-sense signal at CSSC. Enable Input The enable input EN is used to enable or disable the device. Connect EN to IN for always enabled applications. Connecting EN to ground disables the device and reduces current consumption to 100FA. The enable input has an accurate threshold of 1.26V (max). For applications that require a UVLO on the power source, connect a resistive divider from the power source to EN to GND as shown in Figure 1. A zener diode between IN and PGND is required to prevent IN from exceeding its absolute maximum rating of 24V when the device is disabled. The zener diode should be inactive below the maximum UVLO rising threshold voltage VINUVR(MAX) (21V for the MAX5974A/MAX5974C and 10.5V for the MAX5974B/MAX5974D). Design the resistive divider by first selecting the value of REN1 to be on the order of 100kI. Then calculate REN2 as follows: R EN2 = REN1 VEN(MAX) VS(UVLO) − VEN(MAX) where VEN(MAX) is the maximum enable threshold voltage and is equal to 1.26V and VS(UVLO) is the desired UVLO threshold for the power source, below which the devices are disabled. In the case where EN is externally controlled and UVLO for the power source is unnecessary, connect EN to IN and an open-drain or open-collector output as shown in Figure 2. The digital output connected to EN should be capable of withstanding IN’s absolute maximum voltage of 24V. 15 MAX5974A/MAX5974B/MAX5974C/MAX5974D Detailed Description MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Bootstrap Undervoltage Lockout VS The devices have an internal bootstrap UVLO that is very useful when designing high-voltage power supplies (see the Block Diagrams). This allows the device to bootstrap itself during initial power-up. The MAX5974A/MAX5974C soft-start when VIN exceeds the bootstrap UVLO threshold of VINUVR (20V typ). RIN IN CIN MAX5974 REN1 Because the MAX5974B/MAX5974D are designed for use with low-voltage power sources such as wall adapters outputting 12V to 24V, they have a lower UVLO wake-up threshold of 10V. Startup Operation DIGITAL CONTROL EN N REN2 Figure 1. Programmable UVLO for the Power Source VS RIN IN CIN MAX5974 DIGITAL CONTROL EN N The device starts up when the voltage at IN exceeds 20V (MAX5974A/MAX5974C) or 10V (MAX5974B/ MAX5974D) and the enable input voltage is greater than 1.26V. During normal operation, the voltage at IN is normally derived from a tertiary winding of the transformer (MAX5974C/MAX5974D). However, at startup there is no energy being delivered through the transformer; hence, a special bootstrap sequence is required. In the Typical Application Circuits, CIN charges through the startup resistor, RIN, to an intermediate voltage. Only 100FA of the current supplied through RIN is used by the ICs, the remaining input current charges CIN until VIN reaches the bootstrap UVLO wake-up level. Once VIN exceeds this level, NDRV begins switching the n-channel MOSFET and transfers energy to the secondary and tertiary outputs. If the voltage on the tertiary output builds to higher than 7V (the bootstrap UVLO shutdown level), then startup has been accomplished and sustained operation commences. If VIN drops below 7V before startup is complete, the device goes back to low-current UVLO. In this case, increase the value of CIN in order to store enough energy to allow for the voltage at the tertiary winding to build up. While the MAX5974A/MAX5974B derive their input voltage from the coupled inductor output during normal operation, the startup behavior is similar to that of the MAX5974C/MAX5974D. Soft-Start Figure 2. External Control of the Enable Input 16 A capacitor from SS to GND, CSS, programs the softstart time. VSS controls the oscillator duty cycle during Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers I ×t C SS = SS-CH ss 2V where ISS-CH (10FA typ) is the current charging CSS during soft-start and tSS is the programmed soft-start time. A resistor can also be added from the SS pin to GND to clamp VSS < 2V and, hence, program the maximum duty cycle to be less than 80% (see the Duty-Cycle Clamping section). n-Channel MOSFET Gate Driver The NDRV output drives an external n-channel MOSFET. NDRV can source/sink in excess of 650mA/1000mA peak current; therefore, select a MOSFET that yields acceptable conduction and switching losses. The external MOSFET used must be able to withstand the maximum clamp voltage. p-Channel MOSFET Gate Driver The AUXDRV output drives an external p-channel MOSFET with the aid of a level shifter. The level shifter consists of CAUX, RAUX, and D5 as shown in the Typical Application Circuits. When AUXDRV is high, CAUX is recharged through D5. When AUXDRV is low, the gate of the p-channel MOSFET is pulled below the source by the voltage stored on CAUX, turning on the pFET. Dead Time Dead time between the main and AUX output edges allow ZVS to occur, minimizing conduction losses and improving efficiency. The dead time (tDT) is applied to both leading and trailing edges of the main and AUX outputs as shown in Figure 3. Connect a resistor between DT and GND to set tDT to any value between 40ns and 400ns: R DT = 10kΩ × t DT 40ns BLANKING, tBLK NDRV AUXDRV DEAD TIME, tDT Figure 3. Dead Time Between AUXDRV and NDRV 17 MAX5974A/MAX5974B/MAX5974C/MAX5974D startup to provide a slow and smooth increase of the duty cycle to its steady-state value. Calculate the value of CSS as follows: MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Oscillator/Switching Frequency The ICs’ switching frequency is programmable between 100kHz and 600kHz with a resistor RRT connected between RT and GND. Use the following formula to determine the appropriate value of RRT needed to generate the desired output-switching frequency (fSW): R RT = 8.7 × 10 9 fSW where fSW is the desired switching frequency. Peak Current Limit The current-sense resistor (RCS in the Typical Application Circuits), connected between the source of the n-channel MOSFET and PGND, sets the current limit. The current-limit comparator has a voltage trip level (VCS-PEAK) of 400mV. Use the following equation to calculate the value of RCS: R CS = 400mV IPRI where IPRI is the peak current in the primary side of the transformer, which also flows through the MOSFET. When the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator threshold, the MOSFET driver (NDRV) terminates the current on-cycle, within 35ns (typ). The devices implement 115ns of leading-edge blanking to ignore leading-edge current spikes. These spikes are caused by reflected secondary currents, current- VCSBL (BLANKED CS VOLTAGE) discharging capacitance at the FET’s drain, and gatecharging current. Use a small RC network for additional filtering of the leading-edge spike on the sense waveform when needed. Set the corner frequency between 10MHz and 20MHz. After the leading-edge blanking time, the device monitors VCS for any breaches of the peak current limit of 400mV. The duty cycle is terminated immediately when VCS exceeds 400mV. Reverse Current Limit The devices protect the transformer against saturation due to reverse current by monitoring the voltage across RCS while the AUX output is low and the p-channel FET is on. Output Short-Circuit Protection with Hiccup Mode When the device detects eight consecutive peak currentlimit events, both NDRV and AUXDRV driver outputs are turned off for a restart period, tRSTRT. After tRSTRT, the device undergoes soft-start. The duration of the restart period depends on the value of the capacitor at SS (CSS). During this period, CSS is discharged with a pulldown current of ISS-DH (2FA typ). Once its voltage reaches 0.15V, the restart period ends and the device initiates a soft-start sequence. An internal counter ensures that the minimum restart period (tRSTRT-MIN) is 1024 clock cycles when the time required for CSS to discharge to 0.15V is less than 1024 clock cycles. Figure 4 shows the behavior of the device prior and during hiccup mode. VCS-PEAK (400mV) HICCUP DISCHARGE WITH ISS-DH VSS-HI SOFT-START VOLTAGE, VSS VSS-DTH tSS Figure 4. Hiccup Mode Timing Diagram 18 tRSTRT Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers The frequency foldback threshold can be programmed from 0 to 20% of the full load current using a resistor from FFB to GND. The CS voltage is sampled during the NDRV on-time, averaged using an internal RC filter, and gained up by 10 to generate a voltage, VCSAVG. When VCSAVG falls below VFFB, the device folds back the switching frequency to 1/2 the original value to reduce switching losses and increase the converter efficiency. The new switching frequency starts at the beginning of a new cycle as shown in Figure 5. Calculate the value of RFFB as follows: R FFB = 10 × ILOAD(LIGHT) × R CS IFFB where RFFB is the resistor between FFB and GND, ILOAD(LIGHT) is the current at light-load conditions that triggers frequency foldback, RCS is the value of the sense resistor connected between CS and PGND, and IFFB is the current sourced from FFB to RFFB (30FA typ). Duty-Cycle Clamping The maximum duty cycle is determined by the lowest of three voltages: 2V, the voltage at SS (VSS), and the voltage (2.43V - VDCLMP). The maximum duty cycle is calculated as: V D MAX = MIN 2.43V SS By connecting a resistor between SS and ground, the voltage at SS can be made to be lower than 2V. VSS is calculated as follows: VSS = R SS × I SS-CH where RSS is the resistor connected between SS and GND, and ISS-CH is the current sourced from SS to RSS (10FA typ). DCLMP To set DMAX using supply voltage feed-forward, connect a resistive divider between the supply voltage, DCLMP, and GND as shown in the Typical Application Circuits. This feed-forward duty-cycle clamp ensures that the external n-channel MOSFET is not stressed during supply transients. VDCLMP is calculated as follows: VDCLMP = R DCLMP2 × VS R DCLMP1 + R DCLMP2 where RDCLMP1 and RDCLMP2 are the resistive divider values shown in the Typical Application Circuits and VS is the input supply voltage. Oscillator Synchronization The internal oscillator can be synchronized to an external clock by applying the clock to DITHER/SYNC directly. The external clock frequency can be set anywhere between 1.1x to 2x the internal clock frequency. where VMIN = minimum (2V, VSS, 2.43V - VDCLMP). VCSAVG VFFB NDRV tSW tSW x 2 tSW x 2 AUXDRV COMP Figure 5. Entering Frequency Foldback 19 MAX5974A/MAX5974B/MAX5974C/MAX5974D Frequency Foldback for High-Efficiency Light-Load Operation MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Using an external clock increases the maximum duty cycle by a factor equal to fSYNC/fSW. This factor should be accounted for in setting the maximum duty cycle using any of the methods described in the Duty-Cycle Clamping section. The formula below shows how the maximum duty cycle is affected by the external clock frequency: D MAX = VMIN fSYNC × 2.43V fSW where VMIN is described in the Duty-Cycle Clamping section, fSW is the switching frequency as set by the resistor connected between RT and GND, and fSYNC is the external clock frequency. Frequency Dithering for SpreadSpectrum Applications (Low EMI) The switching frequency of the converter can be dithered in a range of Q10% by connecting a capacitor from DITHER/SYNC to GND, and a resistor from DITHER to RT as shown in the Typical Application Circuits. This results in lower EMI. A current source at DITHER/SYNC charges the capacitor CDITHER to 2V at 50FA. Upon reaching this trip point, it discharges CDITHER to 0.4V at 50FA. The charging and discharging of the capacitor generates a triangular waveform on DITHER/SYNC with peak levels at 0.4V and 2V and a frequency that is equal to: fTRI = 50µA C DITHER × 3.2V Typically, fTRI should be set close to 1kHz. The resistor RDITHER connected from DITHER/SYNC to RT determines the amount of dither as follows: R RT 4 %DITHER = × 3 RDITHER where %DITHER is the amount of dither expressed as a percentage of the switching frequency. Setting RDITHER to 10 x RRT generates Q10% dither. Programmable Slope Compensation The device generates a current ramp at CSSC such that its peak is 50FA at 80% duty cycle of the oscillator. An external resistor connected from CSSC to the CS then converts this current ramp into programmable slope- 20 compensation amplitude, which is added to the currentsense signal for stability of the peak current-mode control loop. The ramp rate of the slope compensation signal is given by: m= R CSSC × 50µA × fSW 80% where m is the ramp rate of the slope-compensation signal, RCSSC is the value of the resistor connected between CSSC and CS used to program the ramp rate, and fSW is the switching frequency. Error Amplifier The MAX5974A/MAX5974B include an internal error amplifier with a sample-and-hold input. The feedback input of the MAX5974C/MAX5974D is continuously connected. The noninverting input of the error amplifier is connected to the internal reference and feedback is provided at the inverting input. High open-loop gain and unity-gain bandwidth allow good closed-loop bandwidth and transient response. Calculate the power-supply output voltage using the following equation: R + R FB2 VOUT = VREF × FB1 R FB2 where VREF = 1.52V for the MAX5974A/MAX5974B and VREF = 1.215V for the MAX5974C/MAX5974D. The amplifier’s noninverting input is internally connected to a soft-start circuit that gradually increases the reference voltage during startup. This forces the output voltage to come up in an orderly and well-defined manner under all load conditions. Applications Information Startup Time Considerations The bypass capacitor at IN, CIN, supplies current immediately after the devices wake up (see the Typical Application Circuits). Large values of CIN increase the startup time, but also supply gate charge for more cycles during initial startup. If the value of CIN is too small, VIN drops below 7V because NDRV does not have enough time to switch and build up sufficient voltage across the tertiary output (MAX5974C/MAX5974D) or coupled inductor output (MAX5974A/MAX5974B), which powers the device. The device goes back into UVLO and does not start. Use a low-leakage capacitor for CIN. Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers IG = Q GTOT fSW (I + I )(t ) CIN = IN G SS VHYST where IIN is the ICs’ internal supply current (1.8mA) after startup, QGTOT is the total gate charge for the n-channel and p-channel FETs, fSW is the ICs’ switching frequency, VHYST is the bootstrap UVLO hysteresis (13V typ), and tSS is the soft-start time. RIN is then calculated as follows: RIN ≅ VS(MIN) − VINUVR I START where VS(MIN) is the minimum input supply voltage for the application (36V for telecom), VINUVR is the bootstrap UVLO wake-up level (20V), and ISTART is the IN supply current at startup (150FA max). Choose a higher value for RIN than the one calculated above if a longer startup time can be tolerated in order to minimize power loss on this resistor. Active Clamp Circuit Traditional clamp circuits prevent transformer saturation by channeling the magnetizing current (IM) of the transformer onto a dissipative RC network. To improve efficiency, the active clamp circuit recycles IM between the magnetizing inductance and clamp capacitor. VCLAMP is given by: VCLAMP = VS 1− D where VS is the voltage of the power source and D is the duty cycle. To select n-channel and p-channel FETs with adequate breakdown voltages, use the maximum value of VCLAMP. VCLAMP(MAX) occurs when the input voltage is at its minimum and the duty cycle is at its maximum. VCLAMP(MAX-NORMAL) during normal operation is therefore: VCLAMP(MAX-NORMAL) = VS(MIN) NP × VO 1− N S × VS(MIN) where VS(MIN) is the minimum voltage of the power source, NP/NS is the primary to secondary turns ratio, and VO is the output voltage. The clamp capacitor, n-channel, and p-channel FETs must have breakdown voltages exceeding this level. If feed-forward maximum duty-cycle clamp is used then: V V D MAX-FF = MIN = 1 − DCLMP 2.43 2.43 V RDCLMP2 = 1 − S × 2.43 R DCLMP1 + R DCLMP2 Therefore, VCLAMP(MAX-FF) during feed-forward maximum duty clamp is: VCLAMP(MAX-FF) = = VS 1 − D MAX −FF 2.43 × (R DCLMP1 + R DCLMP2 ) RDCLMP2 The AUX driver controls the p-channel FET through a level shifter. The level shifter consists of an RC network (formed by CAUX and RAUX) and diode D5, as shown in the Typical Application Circuits. Choose RAUX and CAUX so that the time constant exceeds 100/fSW. Diode D5 is a small-signal diode with a voltage rating exceeding 25V. Additionally, CCLAMP should be chosen such that the complex poles formed with magnetizing inductance (LMAG) and CCLAMP are 2x to 4x away from the loop bandwidth: 1-D 2π L MAG × C CLAMP > 3 × fBW 21 MAX5974A/MAX5974B/MAX5974C/MAX5974D Typically, offline power supplies keep startup times to less than 500ms even in low-line conditions (85V AC input for universal offline or 36V DC for telecom applications). Size the startup resistor, RIN, to supply both the maximum startup bias of the device (100FA) and the charging current for CIN. CIN must be charged to 20V within the desired 500ms time period. CIN must store enough charge to deliver current to the device for at least the soft-start time (tSS) set by CSS. To calculate the approximate amount of capacitance required, use the following formula: MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Bias Circuit Optocoupler Feedback (MAX5974C/MAX5974D) An in-phase tertiary winding is needed to power the bias circuit when using optocoupler feedback. The voltage across the tertiary VT during the on-time is: N VT = VOUT × T NS where VOUT is the output voltage and NT/NS is the turns ratio from the tertiary to the secondary winding. Select the turns ratio so that VT is above the UVLO shutdown level (7.5V max) by a margin determined by the holdup time needed to “ride through” a brownout. Coupled-Inductor Feedback (MAX5974A/MAX5974B) When using coupled-inductor feedback, the power for the devices can be taken from the coupled inductor during the off-time. The voltage across the coupled inductor, VCOUPLED, during the off-time is: N VCOUPLED = VOUT × C N O where VOUT is the output voltage and NC/NO is the turns ratio from the coupled output to the main output winding. Select the turns ratio so that VCOUPLED is above the UVLO shutdown level (7.5V max) by a margin determined by the holdup time needed to “ride through” a brownout. This voltage appears at the input of the devices, less a diode drop. An RC network consisting of RSNUB and CSNUB is for damping the reverse recovery transients of diode D6. 22 During on-time, the coupled output is: N VCOUPLED-ON = −(VS × S NP NC NO − VOUT ) where VS is the input supply voltage. Care must be taken to ensure that the voltage at FB (equal to VCOUPLED-ON attenuated by the feedback resistive divider) is not more than 5V: VFB-ON = VCOUPLED-ON × R FB2 < 5V R ( FB1 + R FB2 ) If this condition is not met, a signal diode should be placed from GND (anode) to FB (cathode). Layout Recommendations Typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high dV/dt surfaces. For example, traces that carry the drain current often form high di/dt loops. Similarly, the heatsink of the main MOSFET presents a dV/dt source; therefore, minimize the surface area of the MOSFET heatsink as much as possible. Keep all PCB traces carrying switching currents as short as possible to minimize current loops. Use a ground plane for best results. For universal AC input design, follow all applicable safety regulations. Offline power supplies can require UL, VDE, and other similar agency approvals. Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers VS 36V TO 57V CBULK 33µF L1 3.3mH D1 NT RIN 100kI D2 CIN 1µF 25V L2 6.8µH D3 RDCLMP1 30.1kI 1% NP IN T1 NS RGATE2 10I RGATE1 10I COUT5 COUT1 COUT2 COUT3 COUT4 0.1µF N N2 5i412DP RFB2 2.49kI 1% EN RDCLMP2 750I 1% D4 DCLMP N CSS 0.1µF SS RDT 16.9kI 1% DT CDITHER 10nF RRT 14.7kI 1% N1 5i412DP MAX5974C MAX5974D IN N3 FDS3692 (OPTOCOUPLER FEEDBACK) DITHER/ SYNC CCLAMP 47nF RGATE3 10I NDRV N P CAUX 47nF RFFB 10.0kI 1% RF 499I 1% FFB RG1 RG2 121kI 1% 200kI 1% ROPTO3 4.99kI 1% ROPTO1 825I 1% CCOMP1 2.2nF U1 FOD817CSD RGATE4 10I AUXDRV RT N4 IRF6217 RBIAS 4.02kI 1% CINT 0.1µF CF 330pF FB D5 COMP CSSC PGND RCOMP2 499I 1% CCOMP2 6.8pF CS GND ROPTO2 1kI 1% 5V, 5A RFB1 7.5kI 1% RCSSC 4.02kI 1% RAUX 10kI RCOMP2 2.00kI 1% U2 TLV4314AIDBVT-1.24V RCS 0.2I 23 MAX5974A/MAX5974B/MAX5974C/MAX5974D Typical Application Circuits Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D Typical Application Circuits (continued) D6 RFB1 54.9kI 1% CSNUB RSNUB 10pF 69.8I 1% VS 36V TO 57V CBULK 33µF 63V TO FB RFB2 10kI 1% RIN 100kI CIN 1µF 25V RDCLMP1 30.1kI 1% NP T1 RGATE2 10I D3 NS RGATE1 10I COUT1 COUT2 COUT3 COUT4 D4 SS N1 5i412DP MAX5974A MAX5974B RDT 16.9kI 1% CDITHER 10nF N DCLMP DT (COUPLED INDUCTOR FEEDBACK) DITHER/ SYNC RRT 14.7kI 1% RGATE3 10I NDRV N3 FDS3692 N CCLAMP 47nF RGATE4 10I P AUXDRV RT CAUX 47nF RF 499I 1% RFFB 10kI 1% FFB CS CF 330pF FB CCOMP 4.7nF RZ 2kI 1% D5 COMP GND CINT 47nF 24 N2 5i412DP N EN CSS 0.1µF CSSC PGND 4 x 47µF 6.3V NO IN RDCLMP2 750I 1% LCOUPLED NC RCSSC 4.02kI 1% RCS 0.2I RAUX 10kI N4 IRF6217 5V, 5A COUT5 0.1µF Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers D1 L1 VS NT CBULK D2 RIN L2 CIN T1 D3 NP NS RGATE2 RGATE1 N IN RDCLMP1 EN N2 RFB1 RFB2 D4 RDCLMP2 N DCLMP CSS N1 SS RDT MAX5974C MAX5974D DT RDITHER CDITHER COUT1 COUT2 COUT3 COUT4 CCLAMP RGATE3 NDRV DITHER/ SYNC N N3 RGATE4 RRT P AUXDRV RT N4 CAUX RFFB FFB CS CSSC FB RCSSC COMP Rz CCOMP GND D5 RAUX PGND RCS CHF Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TQFN-EP T1633+4 21-0136 90-0031 25 MAX5974A/MAX5974B/MAX5974C/MAX5974D Typical Application Circuits (continued) MAX5974A/MAX5974B/MAX5974C/MAX5974D Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers Revision History REVISION NUMBER REVISION_ DATE 0 6/10 DESCRIPTION Initial release PAGES_ CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.