0.35§- 40MHz De-Skew PLL PLL2080X DECEMBER 1998. Ver1.0 40MHz PLL ASIC Core The PLL2080X PLL is an application specific PLL designed for the requirements of one customer. The core PLL is a standard 80MHz ring oscillator design with a phase frequency detector. Divide ratios and feedback paths are designed specific to the customers needs. Features • 3.3V operations in the Samsung 0.35um process • Core PLL jitter less than ± 200ps • 20MHz clock input matched in phase to 40MHz clock output • Selectable feedback matching paths Functional Block Diagram CLKIN MODE REFCLK Clock Input Matched Delay 1 Divide 2 0 Clock Tree Matched Delay PFD Charge Pump RCPLL VCO Differential Ring Oscillator Divide 2 CLKOUT Figure 1. Functional Block Diagram Pin Description Pin Name Description VDD 3.3V ± 5% PLL Supply VSS 0V PLL Ground CLKIN External Clock Input to PLL Duty Cycle : 40%~60% REFCLK Feedback clock input to PLL from reference point on internal device clock tree CLKOUT PLL output clock MODE Mode=1, select to REFCLK / Mode=0, select to Match Delay RCPLL Point of connection to external discrete loop filter 1 / 5 De-Skew PLL PLL2080X I/O Access requirements For testing reasons, many of the I/O pins of the PLL must be accessible from the external pins. Many of the pins require indirect access. The specific details are described below: Bypass Mode CLKIN to CLKOUT The customer netlist must include a mode for bypass of the PLL clock from the input. Primary application will be production test of digital logic. It is not reasonable to wait for lock time of the PLL. Indirect Access to VCO Output The CLKOUT node must be accessed at a chip output pin. This node can be buffered or muxed. During PLL test, a DC voltage will applied to the RCPLL pin. The tester must measure the frequency output of the VCO. Recommended Customer Connections to PLL For proper operation and testability, the following external connections to the PLL are shown. If this architecture is not used, it is important that an equivalent is found to meet all data path I/O requirements.. Other Logic 20MHz Clock Input RCPLL CLKIN Software DC Control MODE External RC Loop Filter PLL2080X CLKOUT REFCLK 0 1 Figure 2. PLL Connections within the ASIC Chip PLL Production Tests The following production tests are run to ensure proper PLL operation. A brief description is included to ensure that proper accessibility has been given to the PLL core I/O pins. VCO voltage VS Frequency Tests In this test, the VCO operation is tested by suppling various DC voltage levels to the RCPLL pin and measuring the output clock frequency. SEC ASIC 2 / 5 ANALOG De-Skew PLL PLL2080X Don't Care CLKIN Don't Care MODE Don't Care REFCLK RCPLL Low impeddance DC voltage CLKOUT Measure with Frequency Counter PLL2080X Phase Detector / Charge Pump Tests In this test,the Phase detector and the Charge pump are tested by suppling inputs to the phase detector at various frequency. A capacitive load on the RCPLL pin allows a voltage measurement of the integrated charge pump output. The CLKIN and the REFCLK inputs to the phase detector must be adjusted so that each can be at a frequency higher than the other input. If CLKIN is '0' and MODE=don't care then REFCLK will always Oscillate at a frequency greater than CLKIN. This will cause the RCPLL to decrease toward VSS. VSS CLKIN Don't Care MODE RCPLL Capacitive Load Measure Voltage PLL2080X CLKOUT REFCLK Clock Tree If CLKIN is at 20MHz and MODE='1' and User required bypass mux sets the REFCLK to be connected to CLKIN. The internal Divide / 2 will cause the REFCLK input to be less than CLKIN. This wii cause the RCPLL node to increase to VDD Capacitive Load RCPLL CLKIN 20MHz VDD MODE Measure Voltage PLL2080X CLKOUT REFCLK 0 1 VDD Clock Tree SEC ASIC 3 / 5 ANALOG De-Skew PLL PLL2080X I/O TIMING Clock at PAD input to Chip (20MHz) CLKIN to PLL TPLL_LOCK CLKOUT at PLL Clock tree output as seen by digital logc TJIT ELECTRICAL CHARACTERISTICS Parameter Dynamic Current VCO Maximum Oscillation Frequency PLL Lock/Pull In Time Min IDD 5.5 FVCO 100 TPLL_LOCK Timing Jitter from Clock input Pad to Clock Tree Output SEC ASIC Symbol 4 / 5 TJIT Typ Max Units 6 mA MHz 100 -200 us +200 ps ANALOG De-Skew PLL PLL2080X PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply Voltage Output frequency range Input frequency range Cycle to Cycle Jitter Lock up time Dynamic current Stand by current Output clock duty ratio Long term jitter Output slew rate - Do you need XTAL driver buffer in PLL Core? If you need it, what's the crystal frequency range? If not, What's the input frequency range? - Do you need the lock detector? Do you need the I/O cell of SEC? Do you need the external pin for PLL test? What's the main frequency & frequency range? What's output loading? Could you external/internal pin configurations as required? Specially requested function list : SEC ASIC 5 / 5 ANALOG