ETC AP105-69

GaAs IC Linear Power Amplifier
AP105-69
Features
SSOP-28 Slug
■ IS-136/54 TDMA
0.394 (10.00 mm)
0.386 (9.80 mm)
■ IS-95 CDMA
■ Linear Power up to 28 dBm Nominal
■ Nominal 6 V Operation, Single Supply
Operation
0.120
(3.05 mm)
MAX.
PIN 1
INDICATOR
■ Efficiency Greater Than 35%
■ High Power SSOP-28 Batwing Package
with Slug
28
R 0.010
(0.25 mm) MAX.
15 0.157 (3.99 mm)
14 0.150 (3.81 mm)
0.244
(6.20 mm)
0.228
(5.79 mm)
0.025 BSC
0.087 (2.21 mm)
0.083 (2.11 mm)
0.060 (1.52 mm) REF.
0.38 (0.015 mm)
R 0.33 (0.013 mm)
MAX. X 45˚
0.020 (0.008 mm)
CHAMFER
0.063 (1.60 mm)
0.049 (1.24 mm)
Description
The AP105-69 is a low cost IC power amplifier designed
for the 824–849 MHz frequency band. It features 5 cell
battery operation and operates from 5 V to 7.5 V with
excellent linearity, and high efficiency. An integrated
DC/DC converter supplies -4 V to the power amplifier and
can supply 1.5 mA to an external circuit. The amplifier is
designed to be stable over a temperature range of -30 to
100°C and over 3:1 VSWR loads.
0.145 (3.68 mm) REF.
0.004 MAX.
0.050 (1.27 mm)
(0.010 mm)
0.016 (0.41 mm)
Electrical Specifications at 25°C
Characteristic
Condition
Frequency
Min.
Typ.
Max.
Unit
Digital Mode
POUT (Reference at Output Pin Leads)
0<PIN<5
824–849 MHz
28
dBm
Efficiency
POUT = 28 dBm
37
%
Large Signal Gain
PIN = -20 dBm
26
dB
Idle Current
PIN = -60 dBm
150
200
mA
Noise in the Receive Band
POUT = 28 dBm
RX Band = 869–894 MHz
RX Bandwidth = 30 kHz
-100
-95
dBm
Reference Current
POUT = 28 dBm
1
5
mA
Input VSWR
PIN = -30 to +7 dBm
2.5:1
Analog Mode
POUT
0<PIN<5
28
dBm
Efficiency
POUT = 28 dBm
824–849 MHz
40
%
Large Signal Gain
PIN = -20 dBm
24
Idle Current
PIN = -60 dBm
50
Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com
Specifications subject to change without notice. 3/98A
dB
90
mA
1
GaAs IC Linear Power Amplifier
AP105-69
Operating Characteristics at 25°C
Characteristic
Condition
Frequency
Min.
Typ.
Max.
5
6
7.5
Voltage
Unit
V
[email protected] Rated POUT
[email protected] Rated POUT
POUT = 31 dBm PEP
-24
dBc
POUT = 31 dBm PEP
-34
dBc
[email protected] Rated POUT
POUT = 31 dBm PEP
-38
dBc
Harmonic Power
2fo
3fo
-30
-45
dBc
Modulation
Channel Spacing = 30 kHz,
832 Channels, Pi/4 QPSK
PADJ
30 kHz
60 kHz
90 kHz
-28
-49
-60
dBc
50
Ω
Input Impedance
25
50
20
40
15
30
10
20
5
10
0
0
-6
-4
-2
0
2
4
6
Output Power (dBm)
60
25
15
20
10
15
5
10
-6
-4
-2
0
2
4
POUT, P.A.E. vs. PIN
POUT, Gain vs. PIN
IM7
Bias Current (mA)
IM3, IM5, IM7 (dBc)
20
Input Power (dBm)
50
40
IM3
30
20
10
0
2
30
Input Power (dBm)
IM5
-4
25
0
70
-6
35
8
80
60
30
-2
0
2
4
6
8
6
8
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
17 18 19 20 21 22 23 24 25 26 27 28
Input Power (dBm)
Output Power (dBm)
Distortion. vs. PIN
Bias Current vs. POUT
Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com
Specifications subject to change without notice. 3/98A
Gain (dB)
30
Power Added Efficiency (%)
Output Power (dBm)
Typical Performance Data (824–849 MHz)
GaAs IC Linear Power Amplifier
AP105-69
Power Amplifier Typical Configuration
+4.8
R_Analog
L1
5.6 nH
+5.8
1n
C3
33 pF
C2
33 pF
C4
RF_INPUT
C1
1 nF
R2
18k
2
2k R_Analog
750
VREF
VDD
VGS2
VSS IN
VDS1
VGS1
RF Out/VDS2
1
U1
RF In RF Out/VDS2
GND
2
L3
RF Out/VDS2
AP105
1
U2
L2 C8
6.8 n 3.3 p
1.5 n
C11
5.6 p
C12
RF_OUTPUT
100 p
+5.8
GND
GND
GND
GND
CA
GND
CB
GND
VSS OUT
GND
VGEN
33 pF
C9
1n
C10
100 n
C5
100 n
C7
-4 V_EXT
100 n
C6
Output Matching Circuit
Standby Mode
The output match for the AP105 is provided externally in
order to improve performance, reduce cost, and add
flexibility. By making use of ceramic surface mount
components with better Qs than GaAs matching
elements, a lower loss matching network can be made.
This lower loss results in higher power and efficiency for
the amplifier. Also, by keeping these elements external the
GaAs die size is reduced and the overall cost is less. This
approach also permits the flexibility to tweak the amplifier
for optimum performance at different powers, and/or
frequencies.
The board schematic demonstrates one way to present
the optimum load match while providing a path for the
DC bias.
The power amplifier should be turned off whenever
possible in order to reduce the overall power consumption.
The AP105 can be turned off in several ways. The simplest
is to switch the bias controller supply voltage (Pin 1) open.
This, in effect, switches the gate voltages to VSS. The bias
current of the PA in this condition will drop to less than
1 mA. By adding PMOS switches to the drain lines biasoff currents on the order of a few µA can be achieved.
Pin Out Assignments
28
1
27
2
26
3
Bias
Control
25
4
24
5
Bias Controller Circuit
19
10
17
12
DC/DC
Converter
18
11
13
16
14
15
An on-chip bias controller circuit eliminates the need to
individually adjust the gate bias voltages. This circuit uses
+4.8 V and the negative voltage from the DC converter
(-3.5 V to -4.5 V) to set the gate voltages on each stage
for the proper bias current. Pin 1 can be used to adjust the
bias current between a linear and a saturated mode of
operation. By switching resistors between this pin and
+4.8 V, different quiescent currents can be selected. A
current of 100-200 mA for good linearity in the digital
mode, and a lower current, less than 100 mA, for better
power consumption in the analog mode is optimum.
Pin 1: VREF
Sets the quiescent bias current. Nominally +3.5 V for a bias
of 120-200 mA with best gain and linearity. Lower voltages
in the range of +1 to +3.5 V will set the amplifier for less
quiescent bias current. This is useful for analog or
saturated operation where linearity is not critical. A resistor
Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com
Specifications subject to change without notice. 3/98A
3
GaAs IC Linear Power Amplifier
AP105-69
divider network can be used with the +4.8 V regulated
supply to achieve the nominal voltage. The input
impedance of this pin is 2 kΩ. A switch can be used to
change the resistance and toggle the amp between digital
and analog mode.
Pin 2: VGS2
Second stage gate voltage tap. Should be bypassed with
a 1nF capacitor. This value is not critical.
Pin 3: VDS1
First stage drain bias feed. Requires a matching inductor
with good RF bypassing and the +5.8 V nominal supply
voltage.
Pin 28: VDD
Bias controller supply voltage. The regulated 4.8 V supply
must be connected to this pin. Disconnecting this voltage
will turn the PA bias off. A switch at this pin can turn the
PA on or off while leaving VGEN connected and the
negative supply unchanged.
Pin Configuration
Terminal
Symbol
Function
1
VREF
Reference Voltage
2
VGS2
Gate Voltage 2
3
VDS1
Supply Voltage 1
4
VGS1
Gate Voltage 1
5
RF In
RF Input
Pin 5: RF In
50 Ω RF input.
6
GND
Ground
7
GND
Ground
Pin 6-14: GND
Connect to ground.
8
GND
Ground
9
GND
Ground
Pin 15: VGEN
Supply voltage to DC/DC converter. Requires +4.8 V with
a 100 nF bypassing capacitor.
10
GND
Ground
11
GND
Ground
12
GND
Ground
Pin 16: VSS OUT
Negative output voltage from the DC/DC converter. A
100 nF capacitor is required. This voltage should be
supplied to the bias controller network at Pin 27. External
circuitry (LCD display, driver amplifiers, etc.) can tap off
the negative voltage at this point. Maximum current 2 mA.
13
GND
Ground
14
VNGND
Voltage Generator Ground
15
VGEN
Generator Voltage
16
VSS OUT
Bias Voltage Out
17
CB
Generator Flying Cap
18
CA
Generator Flying Cap
19
GND
Ground
20
GND
Ground
21
GND
Ground
Pin 18: CA
Switch capacitor for DC/DC converter, shared with Pin 17.
22
GND
Ground
23
GND
Ground
Pin 19-23: GND
Connect to ground.
24
RF Out/VDS2
RF Output/Supply Voltage 2
25
RF Out/VDS2
RF Output/Supply Voltage 2
Pin 24-26: RF Out/VDS2
RF output and bias feed for the second stage drain. Output
matching circuitry is required to transform the optimum
load impedance to 50 Ω. The circuit must also provide a
path for the +5.8 V nominal DC bias and have good
RF bypassing.
26
RF Out/VDS2
RF Output/Supply Voltage 2
27
VSS IN
Negative Bias Voltage Input
28
VDD
Positive Bias Voltage Input
Pin 4: VGS1
First stage gate voltage. Requires RF bypassing and an
18K resistor to properly bias the first stage.
Pin 17: CB
Switched capacitor for DC/DC converter. 100 nF capacitor
should be connected between Pin 17 and Pin 18 with
minimal distance between the capacitor and the chip.
Pin 27: VSS IN
Negative voltage for the bias controller circuit.The negative
voltage from the DC/DC converter (Pin 16) should be fed
to this pin.
Absolute Maximum Ratings
Characteristics
Symbol
Value
Units
VDD
10
V
Bias Voltage
VSS
-6
V
Reference Voltage
VREF
6
V
Drain Voltage
Power Input
4
PIN
12
dBm
Operating Temperature
TOPT
-30 to 100°
C
Storage Temperature
TSTG
-35 to 120°
C
Alpha Industries, Inc. [781] 935-5150 • Fax [617] 824-4579 • Email [email protected] • www.alphaind.com
Specifications subject to change without notice. 3/98A