ETC ARA2000S23P0

ARA2000
Address-Programmable Reverse
Amplifier with Step Attenuator
Data Sheet - Rev 1
FEATURES
·
·
·
·
·
·
·
·
Low cost integrated amplifier with step
attenuator
Attenuation Range: 0-58 dB, adjustable in 1dB
increments via a 3 wire serial control
Meets DOCSIS distortion requirements at a
+60dBmV output signal level
Programmable address allows multiple parts
to share control bus
Low distortion and low noise
Frequency range: 5-100MHz
5 Volt operation
-40 to +85 0C temperature range
APPLICATIONS
·
·
·
·
·
MCNS/DOCSIS Compliant Cable Modems
CATV Interactive Set-Top Box
Telephony over Cable Systems
OpenCable Set-Top Box
Residential Gateway
S23 Package
28 Pin SSOP
with Exposed Paddle
PRODUCT DESCRIPTION
The ARA2000 is designed to provide the reverse path
amplification and output level control functions in a
CATV Set-Top Box or Cable Modem. It incorporates
a digitally controlled precision step attenuator that is
preceded by an ultra low noise amplifier stage, and
followed by an ultra-linear output driver amplifier. This
device uses a balanced circuit design that exceeds
the MCNS/DOCSIS requirement for harmonic
performance at a +60dBmV output level while only
requiring a single polarity +5V supply. Both the input
and output are matched to 75 ohms with an
appropriate transformer. The precision attenuator
provides up to 58 dB of attenuation in 1 dB
increments. The ARA2000 has a programmable
address that allows multiple devices to share a
common control bus. The ARA2000 is offered in a
28-pin SSOP package featuring an exposed paddle
on the bottom of the package.
Clock
Data
Enable
Balun
Upstream
QPSK/16QAM
Modulator
Low Pass
Filter
ARA2000
Transmit Enable/Disable
2
5-42 MHz
RAM
Clock
Address Control
Data
Microcontroller
with Ethernet
MAC
MAC
Clock
ROM
Data
44 MHz
Diplexer
54-860 MHz
DoubleConversion
Tuner
SAW
Filter
QAM Receiver
with FEC
10Base-T
Transceiver
Figure 1. Cable Modem or Set Top Box Application Diagram
07-01
RJ45
Connector
ARA2000
GaAs IC
ATTOUT (+)
ATTIN (+)
A1OUT (+)
A2IN (+)
A1IN (+)
32 dB
ISET1
16 dB
8 dB
4 dB
2 dB
A2OUT (+)
1 dB
ISET2
EFET
EFET
Vg1
Vg2
A1IN (-)
A2OUT (-)
A1OUT (-)
A2IN (-)
ATTIN (-)
ATTOUT (-)
32 dB
16 dB
8 dB
4 dB
2 dB
1 dB
P5
P4
P3
P2
P1
P0
Buffer
Buffer
Clock
Data
8
2-Bit Shift
Register/
Address
2
Control Latch
Data Latch
Enable
2
8
2-Bit Shift
Register / Die ID
4-Bit Shift
Register / Chip Select
8
8-Bit Shift Register
Die
Address 0
Die
Address 1
CMOS IC (Serial to Parallel Interface)
Figure 2: Functional Block Diagram
1
GND
GND
28
2
VATTN
N/C
27
3
ATTIN (+)
ATTOUT (+)
26
4
A1OUT (+)
A2IN (+)
25
A2OUT (+)
24
Vg2
23
5
A1IN (+)
6
Vg1
7
ISET1
8
A1IN (-)
9
ISET2
22
A2OUT (-)
21
A1OUT (-)
A2IN (-)
20
10
ATTIN (-)
ATTOUT (-)
19
11
VCMOS
GNDCMOS
18
12
CLK
N/C
17
13
DAT
C1
16
14
EN
C0
15
Figure 3: Pin Out
2
Data Sheet - Rev 1
07-01
ARA2000
Table 1: Pin Description
PIN
N AME
1
GND
2
D ESC R IPTION
PIN
N AME
Ground
15
C0
D evi ce Address 0
VATTN
Supply for Attenuator
16
C1
D evi ce Address 1
3
ATTIN (+)
Attenuator (+) Input (2)
17
N/C
No C onnecti on (1)
4
A1OUT (+)
Ampli fi er A1 (+) Output
18
GND CMOS
Ground for D i gi tal
C MOS C i rcui t
5
A1IN (+)
Ampli fi er A1 (+) Input (2)
19
ATTOUT (-)
Attenuator (-) Output (2)
6
V g1
Ampli fi er A1 (+/-) C ontrol
20
A2IN (-)
Ampli fi er A2 (-) Input (2)
7
ISET1
Ampli fi er A1 (+/-) C urrent
Adjust
21
A2OUT (-)
Ampli fi er A2 (-) Output
8
A1IN (-)
Ampli fi er A1 (-) Input (2)
22
ISET2
Ampli fi er A2 (+/-)
C urrent Adjust
9
A1OUT (-)
Ampli fi er A1 (-) Output
23
V g2
Ampli fi er A2 (+/-) C ontrol
10
ATTIN (-)
Attenuator (-) Input (2)
24
11
VCMOS
Supply For D i gi tal
C MOS C i rcui t
25
A2 IN (+)
Ampli fi er A2 (+) Input (2)
12
C LK
C lock
26
ATTOUT (+)
Attenuator (+) Output (2)
13
D AT
D ata
27
N/C
No C onnecti on (1)
14
EN
Enable
28
GND
Ground
A2
OUT
(+)
D ESC R IPTION
Ampli fi er A2 (+) Output
Notes:
(1) All N/C pins should be grounded.
(2) Pins should be AC-coupled. No external DC bias should be applied.
Data Sheet - Rev 1
07-01
3
ARA2000
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PAR AMETER
MIN
MAX
U N IT
Analog Supply (pi ns 2, 4, 9, 21, 24)
0
9
VD C
D i gi tal Supply: VCMOS (pi n 11)
0
6
VD C
Ampli fi er C ontrols Vg1, Vg2 (pi ns 6, 23)
-5
2
V
RF Power at Inputs (pi ns 5, 8)
-
+60
dBmV
D i gi tal Interface (pi ns 12, 13, 14, 15, 16)
-0.5
VCMOS+0.5
V
Storage Temperature
-55
+200
0
C
Solderi ng Temperature
-
260
0
C
Solderi ng Ti me
-
5
S ec
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for
extended periods of time may adversely affect reliability.
Notes:
1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be
applied.
2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC
bias should be applied.
Table 3: Operating Ranges
PAR AMETER
MIN
TYP
MAX
U N IT
Ampli fi er Supply: VDD (pi ns 4, 9, 21, 24)
4.5
5
7
VD C
VDD-0.5
5
7
VD C
3.0
-
5.5
VD C
D i gi tal Interface (pi ns 12, 13, 14, 15, 16)
0
-
VCMOS
V
Ampli fi er C ontrols Vg1, Vg2 (pi ns 6, 23)
-5
1
2
V
C ase Temperature
-40
25
85
Attenuator Supply: VATTN (pi n 2)
D i gi tal Supply: VCMOS (pi n 11)
0
C
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
4
Data Sheet - Rev 1
07-01
ARA2000
Table 4: DC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER
MIN
TYP
MAX
U N IT
C OMMEN TS
Ampli fi er A1 C urrent (pi ns 4, 9)
-
48
2.4
80
6
mA
Tx enabled
Tx di sabled
Ampli fi er A2 C urrent (pi ns 21, 24)
-
77
3.7
120
9
mA
Tx enabled
Tx di sabled
Attenuator C urrent (pi n 2)
-
9
15
mA
Total Power C onsumpti on
-
0.67
75
1.08
150
W
mW
Tx enabled
Tx di sabled
Table 5: AC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER
MIN
TYP
MAX
U N IT
Gai n (10 MHz)
27.5
29.3
30.5
dB
0 dB attenuati on setti ng
Gai n Flatness
-
0.75
1.5
-
dB
5 to 42 MHz
5 to 65 MHz
Gai n Vari ati on over Temperature
-
-0.006
-
dB/°C
0.65
1.6
3.6
7.5
15.0
30.2
0.83
1.70
3.75
7.75
15.40
30.75
1.00
2.05
4.0
8.0
15.8
31.3
dB
58.6
60.3
-
dB
2nd Harmoni c D i storti on Level
(10 MHz)
-
-75
-53
dB c
+60 dBmV i nto 75 Ohms
3rd Harmoni c D i storti on Level
(10 MHz)
-
-60
-53
dB c
+60 dBmV i nto 75 Ohms
78
-
-
dBmV
1 dB Gai n C ompressi on Poi nt
-
68.5
-
dBmV
Noi se Fi gure
-
3.0
4.0
dB
Attenuati on Steps
1 dB
2 dB
4 dB
8 dB
16 dB
32 dB
Maxi mum Attenuati on
3rd Order Output Intercept
C OMMEN TS
Monotoni c
Includes i nput balun loss
Note: As measured in ANADIGICS test fixture
Data Sheet - Rev 1
07-01
5
ARA2000
continued: AC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER
MIN
TYP
MAX
U N IT
C OMMEN TS
Output Noi se Power
Acti ve / No Si gnal / Mi n. Atten. Set.
Acti ve / No Si gnal / Max. Atten. Set.
-
-
-38.5
-53.8
dBmV
Any 160 kHz bandwi dth
from 5 to 42 MHz
Isolati on (45 MHz) i n Tx di sable mode
-
65
-
dB
D i fference i n output
si gnal between Tx
enable and Tx di sable
D i fferenti al Input Impedance
-
300
-
Ohms
between pi ns 5 and 8
(Tx enabled)
Input Impedance
-
75
-
Ohms
wi th transformer
(Tx enabled)
Input Return Loss
(75 Ohm characteri sti c i mpedance)
-
-20
-5
-12
-
dB
D i fferenti al Output Impedance
-
300
-
Ohms
between pi ns 21 and 24
Output Impedance
-
75
-
Ohms
wi th transformer
Output Return Loss
(75 Ohm characteri sti c i mpedance)
-
-17
-15
-12
-10
dB
Output Voltage Transi ent
Tx enable / Tx di sable
-
4
100
7
mVp-p
Note: As measured in ANADIGICS test fixture
6
Data Sheet - Rev 1
07-01
Tx enabled
Tx di sabled
Tx enabled
Tx di sabled
0 dB attenuator setti ng
24 dB attenuator setti ng
RF Input
(75 Ohms)
1.2K Ohms
Turns
Ratio
1:2
2K Ohms
2K Ohms
1000pF
3.9 Ohms
1000pF
10uH
+5 V
0.1uF
0.1uF
+5 V
1uF
10uH
1000pF
0.1uF
1uF
1uF
1000pF
1.2K Ohms
470pF
1K Ohms
+5 V
Data
Data Sheet - Rev 1
07-01
Clock
Control A1
0 / +3 V
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EN
DAT
CLK
VCMOS
ATTIN (-)
A1OUT (-)
A1IN (-)
ISET1
Vg1
A1IN (+)
A1OUT (+)
ATTIN (+)
VATTN
GND
27
28
ARA2000
C0 15
C1 16
N/C 17
GNDCMOS 18
A2IN (-) 20
ATTOUT (-) 19
A2OUT (-) 21
Vg2 23
ISET2 22
A2OUT (+)
24
A2IN (+) 25
ATTOUT (+) 26
N/C
GND
470pF
1K Ohms
Turns
Ratio
2:1
0.1uF
1uF
Toko Balun
616PT-1030
+5 V
1500pF
RF Output
(75 Ohms)
Note:
Pins 15 and 16 are grounded on the ANADIGICS
test fixture, identifying device address "00".
Note:
Tx Enable: Control A1 and Control A2 = +3V
Tx Disable: Control A1 and Control A2 = 0V
470pF
470pF
2K Ohms
2K Ohms
Control A2
0 / +3 V
ARA2000
Figure 4: Test Circuit
7
Enable
ARA2000
PERFORMANCE DATA
Attenuation (dB)
Figure 5: Attenuation Level vs Control Word
64
60
56
52
48
44
40
36
32
28
24
20
16
12
8
4
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
Control Word
Figure 6: Gain & Noise Figure vs Frequency
Noise Figure
8
30
7
25
6
20
5
15
4
10
3
5
NF (dB)
Gain (dB)
Gain
35
2
10
30
50
70
90
Frequency (MHz)
Figure 7: Gain & Noise Figure vs VDD
GAIN (dB)
Noise Figure
6
32
5
29
4
26
3
23
2
Measured @ 30 MHz
20
1
3
4
5
VDD ( Volts )
8
Data Sheet - Rev 1
07-01
6
7
NF (dB)
Gain
35
ARA2000
Figure 8: Gain & Noise Figure vs Temperature
GAIN (dB)
Noise Figure
6
32
5
29
4
26
3
23
NF (dB)
Gain
35
2
Measured @ 30 MHz
20
1
-40
-25
-10
5
20
35
50
65
80
o
Temperature (C )
Figure 9: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic
3rd Harmonic
-20
Harmonic Level (dBc)
-30
-40
-50
-60
-70
Measured @ 5 MHz
-80
3
4
5
6
7
VDD ( Volts )
Figure 10: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic
3rd Harmonic
-20
Harmonic Level (dBc)
-30
-40
-50
-60
-70
Measured @ 12 MHz
-80
3
4
5
6
7
VDD ( Volts )
Data Sheet - Rev 1
07-01
9
ARA2000
Figure 11: Harmonic Distortion vs Temperature
POUT = 58dBmV
2nd Harmonic
3rd Harmonic
-40
Harmonic level (dBc)
-45
-50
-55
-60
-65
-70
-75
Measured @ 5 MHz
-80
-40
-25
-10
5
20
35
50
65
80
o
Temperature (C )
Figure 12: Harmonic Distortion vs Power Out
2nd
3rd
-30
-35
Harmonics (dBc)
-40
-45
-50
-55
-60
-65
-70
-75
49
51
53
55
57
59
61
63
65
67
Pout (dBmV)
Figure 13: Transients vs Attenuation
POUT = 55dBmV at 0dB attenuation
DOCSIS 1.1 Spec.
ARA2000
ARA2001
100
90
Transient (mV)
80
70
60
50
40
30
20
10
0
0
10
20
30
40
Power Attenuation (dB)
10
Data Sheet - Rev 1
07-01
50
60
ARA2000
Figure 14: Harmonic Performance over
Frequency POUT = +62dBmV
2nd Harmonic
3rd Harmonic
-50
Harmonic Level (dBc)
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
-72
0
5
10
15
20
Frequency (MHz)
25
30
35
40
Figure 15: IIP2 & IIP3 vs Frequency
IIP3
14
36
12
32
10
28
8
24
IIP3 (dBm)
IIP2 (dBm)
IIP2
40
6
Measured @ V DD = 5 Volts
Pin = -20 dBm per tone
20
4
5
15
25
35
45
55
65
75
85
95
Frequency (MHz)
Figure 16: IIP2 & IIP3 vs VDD
IIP3
15
36
11
32
7
28
3
24
IIP3 (dBm)
IIP2 (dBm)
IIP2
40
-1
Measured @ 65 MHz
Two tones @ 29.5 MHz
20
-5
3
4
5
VDD (Volts)
Data Sheet - Rev 1
07-01
6
7
11
ARA2000
LOGIC PROGRAMMING
Programming Instructions
The programming word is set through a 16 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
Table 6: Programming Word
D ATA B IT
D 15
D 14
D 13
D 12
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Value
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
1
C1
C0
1
1
Table 7: Data Description
VALU E
FU N C TION
(1 = on, 0 = by pass)
P7
N/A
P6
N/A
P5
32 dB Attenuator Bi t
P4
16 dB Attenuator Bi t
P3
8 dB Attenuator Bi t
P2
4 dB Attenuator Bi t
P1
2 dB Attenuator Bi t
P0
1 dB Attenuator Bi t
DATA
D15: MSB
D14
Table 8: Device Address
LOGIC LEVEL IN PU T TO
AD D R ESS D EVIC E
C1
C0
Pin 16 (C 1)
Pin 15 (C 0)
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
The device is selected when the logic inputs at pins
16 and 15 match the values of data bits C1 and C0,
respectively.
D8
D7
CLOCK
ENABLE
OR
ENABLE
Figure 17: Serial Data Input Timing
12
Data Sheet - Rev 1
07-01
D1
D0: LSB
ARA2000
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2000 includes two amplification stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 6 and 23, respectively.) By
applying a slightly positive bias of typically +1.0 Volts,
the amplifier is enabled. In order to disable the
amplifier, the control pin needs to be pulled to
ground.
A practical way to implement the necessary control
is to use bias resistor networks similar to those
shown in the test circuit schematic (Figure 4.) Each
network includes a resistor shunted to ground that
serves as a pull-down to disable the amplifier when
no control voltage is applied. When a positive voltage
is applied, the network acts as a voltage divider that
presents the required +1.0 Volts to enable the
amplifier. By selecting different resistor values for
the voltage divider, the network can accommodate
different control voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplifier Bias Current
The ISET pins (7 and 22) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Thermal Layout Considerations
The device package for the ARA2000 features an
exposed paddle on the bottom of the package body.
Use of the paddle is an integral part of the device
design. Soldering this paddle to the ground plane of
the PC board will ensure the lowest possible thermal
resistance for the device, and will result in the longest
MTF (mean time to failure.)
A PC board layout that optimizes the benefits of the
paddle is shown in Figure 18. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufficient heat sink. The recommended solder mask
outline is shown in Figure 19.
Figure 18: PC Board Layout
Data Sheet - Rev 1
07-01
13
ARA2000
Output Transformer
Matching the output of the ARA2000 to a 75 Ohm
load is accomplished using a 2:1 turns ratio
transformer. In addition to providing an impedance
transformation, this transformer provides the bias to
the output amplifier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the amplifiers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF
and DC power requirements without saturating the
core, and it must have adequate isolation and good
phase and amplitude balance. It also must operate
over the desired frequency and temperature range
for the intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
Figure 19: Solder Mask Outline
14
Data Sheet - Rev 1
07-01
ARA2000
PACKAGE OUTLINE
θ
SYMBOLS
A
A1
A2
b
C
D
E
H
e
L
y
θ
T
S
DIMENSIONS IN INCHES
MIN
0.057
0.000
0.057
0.008
0.007
0.386
0.150
0.228
0.025
0.016
−−−
0°
−−−
−−−
DIMENSIONS IN MILLIMETERS
MAX
0.061
0.004
MIN
1.45
0.00
0.012
0.010
0.394
0.157
0.244
0.20
0.18
9.80
3.81
5.80
0.050
0.004
8°
0.190
0.096
0.40
−−−
0°
−−−
−−−
1.45
.64
MAX
1.55
0.10
NOTE
1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND
GATE BURRS
2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED
3. CONTROLLING DIMENSION ARE INCHES.
4. REF. - MO-137
0.30
0.25
10.00
4.00
6.20
1.27
0.10
8°
4.82
2.43
Figure 20: S23 Package Outline - 28 Pin SSOP with Exposed Paddle
Data Sheet - Rev 1
07-01
15
ARA2000
COMPONENT PACKAGING
Volume quantities of the ARA2000 are supplied on
tape and reel. Each reel holds 3,500 pieces. Smaller
quantities are available in plastic tubes of 50 pieces.
Figure 21: Reel Dimensions
DIRECTION OF FEED
Figure 22: Tape Dimensions
16
Data Sheet - Rev 1
07-01
ARA2000
NOTES
Data Sheet - Rev 1
07-01
17
ARA2000
NOTES
18
Data Sheet - Rev 1
07-01
ARA2000
NOTES
Data Sheet - Rev 1
07-01
19
ARA2000
ORDERING INFORMATION
OR D ER N U MB ER
TEMPER ATU R E
R AN GE
PAC K AGE
D ESC R IPTION
ARA2000S23TR
-40 to 85 0C
28 Pi n SSOP wi th
Exposed Paddle
3,500 pi ece tape and reel
ARA2000S23P0
-40 to 85 0C
28 Pi n SSOP wi th
Exposed Paddle
Plasti c tubes (50 pi eces per tube)
C OMPON EN T PAC K AGIN G
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
20
Data Sheet - Rev 1
07-01