MAXIM MAX17482GTL+

19-4372; Rev 2; 7/09
KIT
ATION
EVALU
LE
B
A
IL
A
AV
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
IMVP-6+/IMVP-6.5 Core Supply
BST2
LX2
DL2
TOP VIEW
DH2
Pin Configuration
VRHOT
o
o
o
o
o
o
VDD
o
o
o
DL1
o
o
o
DH1
Applications
o
LX1
The MAX17021 supports the IMVP-6+ specification
while the MAX17082/MAX17482 support the IMVP-6.5
requirements. The MAX17021/MAX17082/MAX17482
are available in a 5mm x 5mm, 40-pin TQFN package.
o
o
Single-/Dual-Phase, Quick-PWM Controllers
MAX17021 IMVP-6+ (Montevina)
MAX17082/MAX17482 IMVP-6.5 (Calpella)
±0.5% VOUT Accuracy Over Line, Load, and
Temperature
7-Bit 0 to 1.50V VID Control
Dynamic Phase Selection Optimizes Active/Sleep
Efficiency
Transient Phase Overlap Reduces Output
Capacitance
Integrated Boost Switches
Active Voltage Positioning with Adjustable Gain
Programmable 200kHz to 800kHz Switching
Frequency
Accurate Current Balance and Current Limit
Adjustable Slew-Rate Control
Power-Good, Clock Enable, and Thermal-Fault
Outputs
Phase Current Imbalance Fault Output
Drives Large Synchronous Rectifier MOSFETs
4V to 26V Battery Input-Voltage Range
Undervoltage and Thermal-Fault Protection
Overvoltage Protection (MAX17021/MAX17082)
Soft-Startup and Soft-Shutdown
BST1
The MAX17021/MAX17082/MAX17482 are 2/1-phaseinterleaved Quick-PWM™ step-down VID power-supply
controllers for notebook CPUs. True out-of-phase operation reduces input ripple current requirements and
output- voltage ripple, while easing component selection and layout difficulties. The Quick-PWM control provides instantaneous response to fast load-current
steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and
allows ideal positioning compensation for tantalum,
polymer, or ceramic bulk output capacitors.
A slew-rate controller allows controlled transitions between
VID codes, controlled soft-start and shutdown, and controlled exit from suspend. A thermistor-based temperature
sensor provides a programmable thermal-fault output
(VRHOT). A current monitor output (IMON) provides an
analog current output proportional to the power consumed
by the CPU (MAX17082/MAX17482 only). Output undervoltage, overvoltage (MAX17021/MAX17082 only), and
thermal protection shut the controller down when any of
these faults are detected. A voltage-regulator power-OK
(PWRGD) output indicates the output is in regulation.
Additionally, the MAX17021/MAX17082/MAX17482 feature true differential current sense and a phase-good
(PHASEGD) output that indicates a phase imbalance
fault condition.
Features
o
o
o
o
30 29 28 27 26 25 24 23 22 21
Multiphase CPU Core Supply
20 PHASEGD
DPRSTP (SLOW) 31
Voltage-Positioned, Step-Down Converters
D0 32
19 PWRGD
Notebook/Desktop Computers
D1 33
18 CLKEN
D2 34
17 V3P3
Blade Servers
D3 35
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
11 CSN2
1
2
3
4
5
6
7
8
9
10
CCI
FB
FBAC
GNDS
MAX17482GTL+
-40°C to +105°C
40 TQFN-EP*
+Denotes a lead-free(Pb)/RoHS-compliant package.
*EP = Exposed pad.
+
VCC
40 TQFN-EP*
12 CSP2
CSP1 39
CSN1 40
TIME
-40°C to +105°C
40 TQFN-EP*
13 SHDN
*EP
ILIM
MAX17082GTL+
-40°C to +105°C
PIN-PACKAGE
14 DPRSLPVR
D6 38
N.C. (IMON)
MAX17021GTL+
TEMP RANGE
15 PSI
THRM
PART
D5 37
PGDIN
Ordering Information
16 TON
MAX17021
(MAX17082)
MAX17482
D4 36
THIN QFN
() DESIGNATES MAX17082/MAX17482 PIN NAME.
*EXPOSED PAD. CONNECTED TO GND.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17021/MAX17082/MAX17482
General Description
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGS
VCC, VDD, V3P3 to GND ...........................................-0.3V to +6V
D0–D6 to GND..........................................................-0.3V to +6V
PGDIN, DPRSLPVR, PSI to GND..............................-0.3V to +6V
DPRSTP (MAX17021) to GND ..................................-0.3V to +6V
SLOW (MAX17082/MAX17482) to GND...................-0.3V to +6V
CSP1, CSP2, CSN1, CSN2 to GND..........................-0.3V to +6V
THRM, ILIM, PHASEGD to GND...............................-0.3V to +6V
PWRGD, VRHOT to GND .........................................-0.3V to +6V
CLKEN to GND ...........................................-0.3V to V3P3 + 0.3V
FB, FBAC to GND .........................................-0.3V to VCC + 0.3V
TIME, CCI to GND.........................................-0.3V to VCC + 0.3V
IMON to GND (MAX17021/MAX17082) ........-0.3V to VCC + 0.3V
GNDS to GND .......................................................-0.3V to +0.3V
SHDN to GND (Note 1)...........................................-0.3V to +16V
TON to GND ...........................................................-0.3V to +30V
DL1, DL2 to GND..........................................-0.3V to VDD + 0.3V
BST1, BST2 to GND ...............................................-0.3V to +36V
BST1, BST2 to VDD .................................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................(-0.3V to VBST1) + 0.3V
DH2 to LX2 ..............................................(-0.3V to VBST2) + 0.3V
Continuous Power Dissipation
40-Pin 5mm x 5mm TQFN Up to +70°C.....................1778mW
(derate above +70°C) ............................................22.2mW/°C
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: SHDN might be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and overlapping operation.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input-Voltage Range
DC Output-Voltage
Accuracy
Boot Voltage
VOUT
VBOOT
Line Regulation Error
VCC, VDD
4.5
5.5
V3P3
3.0
3.6
DAC codes from 0.8125V
to 1.5000V
-0.5
+0.5
DAC codes from 0.3750V
to 0.8000V
-7
+7
Measured at FB
with respect to
GNDS;
includes loadregulation error
(Note 2)
+20
1.194
1.200
1.206
MAX17082/MAX17482 IMVP-6.5
1.094
1.100
1.106
VOUT/VGNDS
GNDS Gain
A GNDS
GNDS Input Bias Current
IGNDS
TA = +25°C
TIME Regulation Voltage
VTIME
RTIME = 71.5k
2
-20
MAX17021 IMVP-6+
GNDS Input Range
%
mV
DAC codes from 0 to
0.3625V
VCC = 4.5V to 5.5V, VIN = 4.5V to 26V
TA = +25°C
FB Input Bias Current
V
0.1
V
%
-0.1
+0.1
μA
-200
+200
mV
1.00
1.03
V/V
+0.5
μA
2.000
2.015
V
0.97
-0.5
1.985
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
t ON
MIN
TYP
MAX
-10
+10
RTIME = 35.7k (25mV/μs nominal) to 178k
(5mV/μs nominal)
-15
+15
Soft-start and soft-shutdown:
RTIME = 35.7k (3.125mV/μs nominal) to 178k
(0.625mV/μs nominal)
-25
+25
-15
+15
Slow:
IMVP-6.5 (MAX17082/MAX17482): VSLOW = 0V,
1/2 of nominal slew rate, RTIME = 71.5k
(6.25mV/μs nominal);
IMVP-6+ (MAX17021): VDPRSTP = VDPRSLPVR = 5V,
1/4 of nominal slew rate, RTIME = 71.5k
(3.125mV/μs nominal)
Slow:
IMVP-6.5 (MAX17082/MAX17482): VSLOW = 0V,
1/2 of nominal slew rate, RTIME = 35.7k
(12.5mV/μs nominal) to 178k (2.5mV/μs
nominal);
IMVP-6+ (MAX17021): VDPRSTP = VDPRSLPVR = 5V
1/4 of nominal slew rate, RTIME = 35.7k
(6.25mV/μs nominal) to 178k (1.25mV/μs
nominal)
TIME Slew-Rate Accuracy
On-Time
CONDITIONS
RTIME = 71.5k (12.5mV/μs nominal)
Measured
at DH_
(Note 3)
UNITS
%
-15
+15
RTON = 96.75k (600kHz per phase),
167ns nominal
-15
+15
RTON = 200k (300kHz per phase),
333ns nominal
-10
+10
RTON = 303.25k (200kHz per phase),
500ns nominal
-15
+15
%
Minimum Off-Time
t OFF(MIN)
Measured at DH_ (Note 3)
300
350
ns
TON Shutdown Input
Current
IRTON,SDN
SHDN = GND, VIN = 26V, VCC = VDD = 0V or 5V,
TA = +25°C
0.01
0.1
μA
BIAS CURRENTS
Quiescent Supply Current
(VCC)
ICC
Measured at VCC, VDPRSLPVR = 5V, FB forced
above the regulation point
2.5
5
mA
Quiescent Supply Current
(VDD)
IDD
Measured at VDD, VDPRSLPVR = 0V, FB forced
above the regulation point, TA = +25°C
0.02
1
μA
_______________________________________________________________________________________
3
MAX17021/MAX17082/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Measured at V3P3, FB forced within the CLKEN
power-good window
TYP
MAX
UNITS
2
4
μA
Quiescent Supply Current
(V3P3)
I3P3
Shutdown Supply Current
(VCC)
ICC,SDN
Measured at VCC, SHDN = GND, TA = +25°C
0.01
1
μA
Shutdown Supply Current
(VDD)
IDD,SDN
Measured at VDD, SHDN = GND, TA = +25°C
0.01
1
μA
Shutdown Supply Current
(V3P3)
I3P3,SDN
Measured at V3P3, SHDN = GND, TA = +25°C
0.01
1
μA
250
300
350
mV
IMVP-6.5
(MAX17082)
1.45
1.50
1.55
IMVP-6+
(MAX17021)
1.75
1.80
1.85
FAULT PROTECTION
Output OvervoltageProtection Threshold
(MAX17021/MAX17082 Only)
Skip mode after output reaches the regulation
voltage or PWM mode; measured at FB with
respect to the voltage target set by the VID code;
see Table 4.
VOVP
Soft-start, soft-shutdown, skip
mode, and output have not
reached the regulation
voltage; measured at FB
Minimum OVP threshold; measured at FB
0.8
10
Output OvervoltagePropagation Delay
(MAX17021/MAX17082 Only)
t OVP
FB forced 25mV above trip threshold
Output UndervoltageProtection Threshold
VUVP
Measured at FB with respect to the voltage target
set by the VID code; see Table 4
Output UndervoltagePropagation Delay
tUVP
FB forced 25mV below trip threshold
CLKEN Startup Delay and
Boot Time Period
-450
-400
V
μs
-350
10
mV
μs
Measured from the time when FB reaches the
boot target voltage (Note 2)
20
60
100
μs
PWRGD Startup Delay
Measured at startup from the time when CLKEN
goes low
3
6.5
10
ms
-350
-300
-250
CLKEN and PWRGD
Threshold
Measured at FB with respect
to the voltage target set by
the VID code; see Table 4,
20mV hysteresis (typ)
tBOOT
Lower threshold,
falling edge
(undervoltage)
mV
Upper threshold,
rising edge
(overvoltage)
+150
+200
+250
CLKEN and PWRGD Delay
FB forced 25mV outside the PWRGD trip
thresholds
10
μs
PHASEGD Delay
V(CCI,FB) forced 25mV outside trip thresholds
10
μs
4
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CLKEN, PWRGD, and
PHASEGD Transition
Blanking Time
(VID Transitions)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured from the time when FB reaches the
target voltage (Note 2)
20
μs
PHASEGD Transition
Blanking Time (Phase 2
Enable Transitions)
Number of DH2 pulses for which PHASEGD is
blanked after phase 2 is enabled
32
Pulses
CLKEN Output Low Voltage
Low state, ISINK = 3mA
CLKEN Output High
Voltage
High state, I SOURCE = 3mA
PWRGD, PHASEGD Output
Low Voltage
Low state, I SINK = 3mA
PWRGD, PHASEGD
Leakage Current
High-impedance state, PWRGD, PHASEGD forced
to 5V, TA = +25°C
CSN1 Pulldown Resistance
in Shutdown
SHDN = 0, measured after soft-shutdown
completed (DL_ = low)
VCC Undervoltage Lockout
(UVLO) Threshold
tBLANK
VUVLO(VCC)
Rising edge, 65mV typical hysteresis,
controller disabled below this level
0.4
V3P3 0.4
V
V
0.4
V
1
μA
10
4.05
4.27
4.48
V
29
30
31
%
THERMAL PROTECTION
Measured at THRM as a percentage of VCC,
falling edge, typical hysteresis = 75mV
VRHOT Trip Threshold
VRHOT Delay
t VRHOT
VRHOT Output
On-Resistance
THRM forced 25mV below the VRHOT trip
threshold, falling edge
10
R ON(VRHOT) Low state
2
High-impedance state, VRHOT forced to 5V,
TA = +25°C
VRHOT Leakage Current
THRM Input Leakage
ITHRM
VTHRM = 0 to 5V, TA = +25°C
Thermal-Shutdown Threshold
T SHDN
Typical hysteresis = 15°C
-0.1
μs
10
1
μA
+0.1
μA
160
°C
VALLEY CURRENT LIMIT, DROOP, AND CURRENT BALANCE
Current-Limit Threshold
Voltage (Positive)
VLIMIT
Current-Limit Threshold
Voltage (Negative)
Accuracy
VLIMIT(NEG)
Current-Limit Threshold
Voltage (Zero Crossing)
VZERO
VCSP_ - VCSN_
VTIME - VILIM = 100mV
7
10
13
VTIME - VILIM = 500mV
45
50
55
ILIM = VCC
20
22.5
25
VCSP_ - VCSN_, nominally -125% of VLIMIT
VGND - VLX_, DPRSLPVR = 5V
-4
+4
1
mV
mV
mV
_______________________________________________________________________________________
5
MAX17021/MAX17082/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
CSP_, CSN_ CommonMode Input Range
ILIM Input Current
Measured at CSP2
I ILIM
TA = +25°C
(1/N) x (VCSP_ - VCSN_) at
IFBAC = 0;
indicates summation over
all phases from 1 to N, N = 2
Gm(FBAC)
Current-Balance Amplifier
Offset
Current-Balance Amplifier
Transconductance
UNITS
2
V
VCC 0.4
V
-0.2
+0.2
μA
-0.1
+0.1
μA
-0.5
+0.5
-0.75
+0.75
3
ICSP_, ICSN_ TA = +25°C
Droop Amplifier Offset
Droop Amplifier
Transconductance
MAX
0
Phase 2 Disable Threshold
CSP_, CSN_ Input Current
TYP
Gm(CCI)
TA = +25oC
o
o
TA = 0 C to +85 C
IFBAC/[ (VCSP_ - VCSN_)];
indicates summation over all phases from 1 to
N, N = 2, VFBAC = VCSN- = 0.45V to 2V
590
(VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0
-1.0
ICCI/[(VCSP1 - VCSN1) - (VCSP2 - VCSN2)]
VCC 1
600
mV/
phase
608
μS
+1.0
mV
200
μS
CURRENT MONITOR (MAX17082/MAX17482 Only)
Current-Monitor Output
Current at Full Load
Condition
I IMON
VCSP1 - VCSN1 = VCSP2 - VCSN2 = 20mV,
VCSN_ = 0.45V to 2.0V
Current-Monitor
Transconductance
Gm(IMON)
I IMON/[ (VCSP_ - VCSN_)];
indicates summation over all phases from 1 to
N, N = 2, CSN_ = 0.45V to 2V
IMON Clamp Voltage
VIMON,max
I SINK = 10mA
SHDN = 0, measured after soft-shutdown
completed (DL_ = low)
IMON Pulldown Resistance
in Shutdown
93.12
96
98.88
μA
2.2
2.4
2.6
mS
1.05
1.10
1.15
V
10
GATE DRIVERS
DH_ Gate Driver
On-Resistance
R ON(DH_)
DL_ Gate Driver
On-Resistance
R ON(DL_)
DH_ Gate Driver Source
Current
DH_ Gate Driver Sink
Current
DL_ Gate Driver Source
Current
6
BST_ - LX_ forced to 5V
High state (pullup)
0.9
2.5
Low state (pulldown)
0.7
2.0
High state (pullup)
0.7
2.0
Low state (pulldown)
0.25
0.7
IDH_(SOURCE) DH_ forced to 2.5V, BST_ - LX_ forced to 5V
IDH_(SINK)
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
IDL_(SOURCE) DL_ forced to 2.5V
2.2
A
2.7
A
2.7
A
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
DL_ Gate Driver Sink
Current
IDL_(SINK)
Internal BST_ Switch
On-Resistance
R ON(BST_)
CONDITIONS
MIN
DL_ forced to 2.5V
TYP
MAX
8
10
UNITS
A
20
LOGIC AND I/O
Logic Input High Voltage
VIH
SHDN, PGDIN
MAX17021: DPRSLPVR
Logic Input Low Voltage
VIL
SHDN, PGDIN
MAX17021: DPRSLPVR
SHDN No-Fault Level
2.3
To enable no-fault mode
11
Low-Voltage Logic Input
High Voltage
VIHLV
PSI, D0–D6;
MAX17082/MAX17482: DPRSLPVR, SLOW,
MAX17021: DPRSTP
Low-Voltage Logic Input
Low Voltage
VILLV
PSI, D0–D6;
MAX17082/MAX17482: DPRSLPVR, SLOW,
MAX17021: DPRSTP
TA = +25°C, SHDN, DPRSLPVR, PGDIN, PSI,
DPRSTP, SLOW, D0–D6 = 0 or 5V
Logic Input Current
V
1.0
V
13
V
0.67
V
-1
0.33
V
+1
μA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN2 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = -40°C to +105°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input-Voltage Range
VCC, VDD
4.5
5.5
V3P3
3.0
3.6
-0.75
+0.75
-10
+10
DAC codes from
0.8125V to 1.5000V
DC Output-Voltage
Accuracy
Boot Voltage
VOUT
VBOOT
Measured at FB with
respect to GNDS;
DAC codes from
includes load0.3750V to 0.8000V
regulation error (Note 2)
DAC codes from 0 to
0.3625V
V
%
mV
-25
+25
MAX17021: IMVP-6+
1.19
1.21
MAX17082/MAX17482: IMVP-6.5
1.09
1.11
V
_______________________________________________________________________________________
7
MAX17021/MAX17082/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN2 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = -40°C to +105°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
GNDS Input Range
GNDS Gain
TIME Regulation Voltage
Minimum Off-Time
TYP
MAX
UNITS
+200
mV
A GNDS
VOUT/VGNDS
0.97
1.03
V/V
VTIME
RTIME = 71.5k
1.985
2.015
V
RTIME = 71.5k (12.5mV/μs nominal)
-10
+10
RTIME = 35.7k (25mV/μs nominal) to 178k
(5mV/μs nominal)
-15
+15
Soft-start and soft-shutdown:
RTIME = 35.7k (3.125mV/μs nominal) to 178k
(0.625mV/μs nominal)
-25
+25
Slow:
IMVP-6.5 (MAX17082/MAX17482): VSLOW = 0V,
1/2 of nominal slew rate, RTIME = 71.5k
(6.25mV/μs nominal);
IMVP-6+ (MAX17021): VDPRSTP = VDPRSLPVR = 5V,
1/4 of nominal slew rate, RTIME = 71.5k
(3.125mV/μs nominal)
-15
+15
Slow:
IMVP-6.5 (MAX17082/MAX17482): VSLOW = 0V,
1/2 of nominal slew rate, RTIME = 35.7k
(12.5mV/μs nominal) to 178k (2.5mV/μs nominal);
IMVP-6+ (MAX17021): VDPRSTP = VDPRSLPVR = 5V,
1/4 of nominal slew rate, RTIME = 35.7k
(6.25mV/μs nominal) to 178k (1.25mV/μs nominal)
-17
+17
RTON = 96.75k (600kHz per phase),
167ns nominal
-15
+15
-15
+15
-15
+15
TIME Slew-Rate Accuracy
On-Time
MIN
-200
t ON
t OFF(MIN)
Measured
RTON = 200k (300kHz per phase),
at DH_
333ns nominal
(Note 3)
RTON = 303.25k (200kHz per phase),
500ns nominal
Measured at DH_ (Note 3)
%
%
350
ns
BIAS CURRENTS
Quiescent Supply Current
(VCC)
ICC
Measured at VCC, VDPRSLPVR = 5V, FB forced
above the regulation point
5
mA
Quiescent Supply Current
(V3P3)
I3P3
Measured at V3P3, FB forced within the CLKEN
power-good window
4
μA
8
_______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN2 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = -40°C to +105°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
250
350
mV
IMVP-6.5
(MAX17082)
1.45
1.55
IMVP-6+
(MAX17021)
1.75
1.85
-450
-350
mV
FAULT PROTECTION
Output OvervoltageProtection Threshold
(MAX17021/MAX7082
Only)
Skip mode after output reaches the regulation
voltage or PWM mode, measured at FB with
respect to the voltage target set by the VID code
(see Table 4)
VOVP
Soft-start, soft-shutdown, skip
mode, and output have not
reached the regulation voltage,
measured at FB
V
Output UndervoltageProtection Threshold
VUVP
Measured at FB with respect to the voltage target
set by the VID code (see Table 4)
CLKEN Startup Delay and
Boot Time Period
tBOOT
Measured from the time when FB reaches the
boot target voltage (Note 3)
20
100
μs
Measured at startup from the time when CLKEN
goes low
3
10
ms
-350
-250
PWRGD Startup Delay
Measured at FB with respect to
the voltage target set by the VID
code (see Table 4), 20mV
hysteresis (typ)
CLKEN and PWRGD
Threshold
CLKEN Output Low Voltage
Low state, ISINK = 3mA
CLKEN Output High
Voltage
High state, I SOURCE = 3mA
PWRGD, PHASEGD Output
Low Voltage
Low state, I SINK = 3mA
VCC Undervoltage-Lockout
Threshold (UVLO)
VUVLO(VCC)
Lower
threshold,
falling edge
(undervoltage)
mV
Upper
threshold,
rising edge
(overvoltage)
+150
+250
0.4
V3P3 0.4
V
V
0.4
V
Rising edge, 65mV typical hysteresis, controller
disabled below this level
4.0
4.5
V
Measured at THRM as a percentage of VCC,
falling edge, typical hysteresis = 75mV
28
32
%
10
THERMAL PROTECTION
VRHOT Trip Threshold
VRHOT Output
On-Resistance
R ON(VRHOT) Low state
_______________________________________________________________________________________
9
MAX17021/MAX17082/MAX17482
ELECTRICAL CHARACTERISTICS (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1
= VCSN1 = VCSP2 = VCSN2 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482:
VSLOW = 5V; MAX17021: DPRSTP = GND; TA = -40°C to +105°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VALLEY CURRENT LIMIT, DROOP, AND CURRENT BALANCE
Current-Limit Threshold
Voltage (Positive)
VLIMIT
VTIME - VILIM = 100mV
7
13
VTIME - VILIM = 500mV
40
60
ILIM = VCC
19
26
0
2
V
IFBAC/[(VCSP_ - VCSN_)],
indicates summation over all phases from 1 to
N, N = 2, VFBAC = VCSN- = 0.45V to 2V
585
610
μS
(VCSP1 - VCSN1) - (VCSP2 - VCSN2) at ICCI = 0
-1.25
+1.25
mV
VCSP_ - VCSN_
CSP_, CSN_ Common-Mode
Input Range
Droop Amplifier
Transconductance
Gm(FBAC)
Current-Balance Amplifier
Offset
mV
CURRENT MONITOR (MAX17082/MAX17482 Only)
Current-Monitor
Transconductance
Gm(IMON)
I IMON/[(VCSP_ - VCSN_)],
indicates summation over all phases from 1 to
N, N = 2, VCSN_ = 0.45V to 2V
2.2
2.6
mS
IMON Clamp Voltage
VIMON,max
I SINK = 10mA
1.05
1.15
V
DH_ Gate Driver
On-Resistance
R ON(DH_)
BST_ - LX_ forced to 5V
DL_ Gate Driver
On-Resistance
R ON(DL_)
GATE DRIVERS
High state (pullup)
2.5
Low state (pulldown)
2.0
High state (pullup)
2.0
Low state (pulldown)
0.7
LOGIC AND I/O
Logic Input High Voltage
VIH
SHDN, PGDIN:
MAX17021: DPRSLPVR
Logic Input Low Voltage
VIL
SHDN, PGDIN:
MAX17021: DPRSLPVR
Low-Voltage Logic Input
High Voltage
VIHLV
PSI, D0–D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
Low-Voltage Logic Input
Low Voltage
VILLV
PSI, D0–D6:
MAX17082/MAX17482: DPRSLPVR, SLOW
MAX17021: DPRSTP
2.3
V
1.0
0.67
V
V
0.33
V
Note 2: When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DL_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times might be different due to MOSFET switching speeds.
Note 4: Specifications to TA = -40°C and +105°C are guaranteed by design and are not production tested.
10
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
7V
1.05
1.00
12V
80
0.89
OUTPUT VOLTAGE (V)
90
1.10
0.90
MAX17021 toc02
MAX17021 toc01
100
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
1.15
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)
EFFICIENCY vs. LOAD CURRENT
(VOUT(HFM) = 1.075V)
20V
70
MAX17021 toc03
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(HFM) = 1.075V)
SKIP MODE
0.88
0.87
0.86
PWM MODE
0.85
60
0.84
10
0
20
30
40
0.1
50
1.0
0
100.0
10.0
5
10
15
20
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(C4) = 0.4V)
EFFICIENCY vs. LOAD CURRENT
(VOUT(C4) = 0.4V)
OUTPUT VOLTAGE (V)
80
12V
70
20V
0.40
MAX17021 toc06
90
7V
80
EFFICIENCY (%)
7V
MAX17021 toc05
0.41
MAX17021 toc04
90
EFFICIENCY (%)
0.83
50
0.95
70
12V
60
50
20V
60
40
SKIP MODE
PWM MODE
50
1.0
10.0
100.0
3
4
0.01
5
0.10
1.00
10.00
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
(VOUT(HFM) = 1.075V)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
AT SKIP MODE (VOUT(HFM) = 1.075V)
250
200
150
100
50
DPRSLPVR = VCC
DPRSLPVR = GND
0
10
20
30
LOAD CURRENT (A)
40
50
75
IIN
50
ICC + IDD
25
DPRSLPVR = GND
0
6
9
12
15
18
INPUT VOLTAGE (V)
21
24
MAX17021 toc09
10.0
NO-LOAD SUPPLY CURRENT (mA)
VOUT(HFM) = 1.075V
MAX17021 toc08
VOUT(LFM) = 0.875V
100
NO-LOAD SUPPLY CURRENT (mA)
MAX17021 toc07
SWITCHING FREQUENCY (kHz)
2
LOAD CURRENT (A)
300
0
1
0
LOAD CURRENT (A)
400
350
DPRSLPVR = VCC
30
0.39
0.1
ICC + IDD
1.0
IIN
0.1
DPRSLPVR = VCC
0
6
9
12
15
18
21
24
INPUT VOLTAGE AT SKIP MODE (V)
______________________________________________________________________________________
11
MAX17021/MAX17082/MAX17482
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.075V, TA = +25°C, unless otherwise specified.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.075V, TA = +25°C, unless otherwise specified.)
30
20
MAX17021 toc11
40
30
20
0.5
40
0.4
30
0.3
20
0.2
0.1
610
608
606
604
602
600
598
596
594
592
590
0.8175
0.8165
0.8155
0.8145
0.8135
0
0.8125
0
0.8115
0
0.8105
10
0.8095
10
0.8085
0.6
50
10
0.8075
MAX17021 toc12
VOUT = 1.075V
0
0
5
10 15 20 25 30 35 40 45 50
LOAD CURRENT (A)
TRANSCONDUCTANCE (µs)
OUTPUT VOLTAGE (V)
SOFT-START WAVEFORM (UP TO CLKEN)
5V
0
5V
0
1.075V
MAX17021 toc15
MAX17021 toc14
A
B
C
0
D
0
5V
0
5V
0
5V
0
5V
0
1.075V
A
B
C
D
E
A. SHDN, 10V/div
B. CLKEN, 10V/div
C. VOUT, 500mV/div
B
C
D
0
0
F
G
0
0
200µs/div
A
E
F
0
0
5V
0
5V
0
5V
0
5V
0
1.075V
0
E
12
SHUTDOWN WAVEFORM
SOFT-START WAVEFORM (UP TO PWRGD)
MAX17021 toc13
G
100µs/div
1ms/div
D. ILX1, 10A/div
E. ILX2, 10A/div
IOUT = 15A
A. SHDN, 10V/div
B. PWRGD, 10V/div
C. PHASEGD, 10V/div
D. CLKEN, 10V/div
E. VOUT, 1V/div
F. ILX1, 10A/div
G. ILX2, 10A/div
IOUT = 15A
A. SHDN, 10V/div
B. CLKEN, 10V/div
C. PWRGD, 10V/div
D. DL_, 10V/div
______________________________________________________________________________________
E. VOUT, 500mV/div
F. ILX1, 10A/div
G. ILX2, 10A/div
VCSPN1 - VCSPN2 (mV)
40
50
SAMPLE SIZE = 100
+85°C
+25°C
60
VCSP_ - VCSN_ (mV)
50
60
SAMPLE PERCENTAGE (%)
MAX17021 toc10
60
SAMPLE SIZE = 100
+85°C
+25°C
CURRENT BALANCE vs. LOAD CURRENT
Gm(FB) TRANSCONDUCTANCE DISTRIBUTION
0.8125V OUTPUT-VOLTAGE DISTRIBUTION
70
SAMPLE PERCENTAGE (%)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
MAX17021 toc18
MAX17021 toc17
MAX17021 toc16
50A
10A
VID CODE CHANGE (SLOW = GND)
LOAD-TRANSIENT RESPONSE (LFM MODE)
LOAD TRANSIENT RESPONSE (HFM MODE)
5V
20A
A
A
1.075V
A
0
5A
1.075V
B
B
1V
0.875V
B
25A
0.975V
C
20A
5A
0
C
0
D
C
D
5A
5A
20µs/div
20µs/div
20μs/div
A. IOUT = 10A TO 50A
B. VOUT, 50mV/div
A. IOUT = 5A TO 20A
B. VOUT, 50mV/div
C. ILX1, 10A/div
D. ILX2, 10A/div
C. ILX1, 10A/div
D. ILX2, 10A/div
A. VID3, 5V/div
B. VOUT, 50mV/div
C. INDUCTOR CURRENT,
10A/div
DYNAMIC VID CODE CHANGE
(D0 = 12.5mV)
VID CODE CHANGE (SLOW = VDD)
MAX17021 toc20
MAX17021 toc19
5V
A
5V
0
A
0
1.075V
B
1.075V
1.0625V
0
C
5A
0
D
5A
0.975V
B
C
D
20µs/div
20µs/div
VIMON vs. LOAD CURRENT
OUTPUT UNDERVOLTAGE FAULT
MAX17021 toc21
VOUT = 1.075V
160
A
5V
0
C
140
120
VIMON (μA)
B
MAX17021 toc22
180
1.075V
0
5V
0
C. ILX1, 10A/div
D. ILX2, 10A/div
A. D0, 5V/div
B. VOUT, 20mV/div
IOUT = 10A
C. ILX1, 10A/div
D. ILX2, 10A/div
A. VID3, 5V/div
B. VOUT, 50mV/div
100
80
60
30A
D
40
DPRSLPVR = VCC
DPRSLPVR = GND
20
0
0
0
100μs/div
A. VOUT, 500mV/div
B. PWRGD, 10V/div
C. DL_, 10V/div
D. ILX1, 15A/div
10
20
30
40
50
60
70
80
VCSPN1 + VCSPN2 (mV)
______________________________________________________________________________________
13
MAX17021/MAX17082/MAX17482
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.075V, TA = +25°C, unless otherwise specified.)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 1.075V, TA = +25°C, unless otherwise specified.)
BIAS SUPPLY REMOVAL
(UVLO RESPONSE)
OUTPUT OVERVOLTAGE WAVEFORM
MAX17021 toc23
MAX17021 toc24
5V
A
A
0.875V
0.875V
0
B
5V
B
0
5V
C
0
0
5V
C
0
5V
0
D
10A
E
0
100μs/div
A. VOUT, 500mV/div
B. DL_, 5V/div
40μs/div
C. PWRGD, 5V/div
A. 5V BIAS SUPPLY, 5V/div
B. VOUT, 500mV/div
C. PWRGD, 5V/div
D. DL_, 5V/div
E. ILX1, 10A/div
IOUT = 10A
Pin Description
PIN
NAME
1
PGDIN
2
3
14
FUNCTION
System Power-Good Logic Input. PGDIN indicates the power status of other system rails and is used for
power-supply sequencing. After power-up to the boot voltage, the output voltage remains at VBOOT, CLKEN
remains high, and PWRGD remains low as long as the PGDIN stays low. When PGDIN is pulled high, the
output transitions to selected VID voltage, and CLKEN is pulled low. If the system pulls PGDIN low during
normal operation, the MAX17021/MAX17082/MAX17482 immediately drive CLKEN high, pull PWRGD low,
and slew the output to the boot voltage (using two-phase pulse-skipping mode). The controller remains at
the boot voltage until PGDIN goes high again, SHDN is toggled, or the VCC input power supply is cycled.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and
GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of VCC) at
the desired high temperature.
Current-Monitor Output. The MAX17082/MAX17482 IMON output source a current that is directly
proportional to the current-sense voltage as defined by:
I IMON = Gm(IMON) x (VCSP_ - VCSN_)
where Gm(IMON) = 2.4mS (typ).
The IMON current is unidirectional (sources current out of IMON only) for positive current-sense values.
For negative current-sense voltages, the IMON current is zero.
Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain based on
IMON
the following equation:
(MAX17082/
RIMON = 0.999V/(IMAX x R SENSE x Gm(IMON))
MAX17482 where IMAX is defined in the Current Monitor section of the Intel IMVP-6.5 specification and based on
only)
discrete increments (20A, 30A, 40A, etc.), RSENSE is the typical effective value of the current-sense
element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and
Gm(IMON) is the typical transconductance amplifier gain as defined in the Electrical Characteristics
table.
The IMON voltage is internally clamped to a maximum of 1.1V (typ).
The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly
drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 2.
IMON is pulled to ground when MAX17082/MAX17482 are in shutdown.
THRM
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
PIN
NAME
4
ILIM
FUNCTION
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP_ to CSN_
equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to VCC to set the default current-limit threshold
setting of 22.5mV (typ) nominal.
5
TIME
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of the
internal error-amplifier target. The sum of the resistance between TIME and GND (RTIME) determines the
nominal slew-rate:
SLEW RATE = (12.5mV/μs) x (71.5k/RTIME)
The guaranteed RTIME range is between 35.7k and 178k. This “nominal” slew rate applies to VID
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew rate for
all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to
the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate in order to minimize surge
currents.
MAX17021: If both DPRSLPVR and DPRSTP are pulled high, then the slew rate is reduced to 1/4 of nominal.
MAX17082/MAX17482: If SLOW is low, then the slew rate is reduced to 1/2 of nominal.
6
VCC
Controller Analog Bias Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
7
CCI
Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the
feedback remote sense. CCI is internally forced low in shutdown.
8
FB
9
FBAC
10
GNDS
11
CSN2
Negative Current-Sense Input for Phase 2. Connect CSN2 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
12
CSP2
Positive Current-Sense Input for Phase 2. Connect CSP2 to the positive terminal of the inductor currentsensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4). Short CSP2 to VCC for dedicated one-phase operation.
Remote Feedback-Sense Input. Normally shorted to FBAC and connected to the VCC_SENSE pin of the
CPU socket through the load-line gain resistor (see the FBAC pin description). FB internally connects
to the error amplifier and integrator.
Voltage-Positioning Transconductance Amplifier Output. Connect a resistor RFB between FBAC and the
positive side of the feedback remote sense to set the DC steady-state droop based on the voltagepositioning gain requirement:
RFB = RDROOP/(RSENSE x Gm(FBAC))
where RDROOP is the desired voltage-positioning slope and Gm(FBAC) = 600μS (typ). RSENSE is the
value of the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If
lossless sensing is used, R SENSE = RL. In this case, consider making RFB a resistor network that
includes an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Remote Ground-Sense Input. Normally connected to the VSS_SENSE pin of the CPU socket. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage—compensating
for voltage drops from the regulator ground to the load ground.
______________________________________________________________________________________
15
MAX17021/MAX17082/MAX17482
Pin Description (continued)
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
MAX17021/MAX17082/MAX17482
Pin Description (continued)
16
PIN
NAME
13
SHDN
14
DPRSLPVR
15
PSI
16
TON
17
V3P3
18
CLKEN
19
PWRGD
FUNCTION
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal
operation. Connect to ground to put the IC into its 1μA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at
the same slow slew rate. Forcing SHDN to 11V~13V disables both overvoltage-protection and
undervoltage-protection circuits, clears the fault latch, disables transient phase overlap, and disables
the BST_ charging switches. Do not connect SHDN to > 13V.
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the operating
mode of MAX17021/MAX17082/MAX17482. When DPRSLPVR is forced high, the controller immediately
enters the automatic pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is
forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward
output-voltage transition that occurs when the controller is in pulse-skipping mode, and stays blanked until
the transition-related PWRGD blanking period is complete and the output reaches regulation. The output
overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed-default
transitional OVP threshold during the period for which the PWRGD upper threshold is blanked.
The MAX17082 is in two-phase pulse-skipping mode during startup and while in boot mode, but is in
forced-PWM mode during the transition from boot mode to VID mode plus 20μs, and during softshutdown, irrespective of the DRPSLPVR logic level.
DPRSLPVR and PSI together determine the operating mode and the number of active phases as shown
in the following truth table:
DPRSLPVR
PSI
MODE AND PHASES
1
0
Very low current (one-phase pulse skipping)
1
1
Low current (approx 3A) (one-phase pulse skipping)
0
0
Intermediate power potential (one-phase PWM)
0
1
Max power potential ( two- or one-phase PWM as configured at CSP2)
Power-State Indicator Input. DPRSLPVR and PSI together determine the operating mode and the number
of active phases as shown in the truth table included under the PSI pin description above.
Switching Frequency Setting Input. An external resistor between the input power source and TON sets
the switching period (T SW = 1/f SW) per phase according to the following equation:
T SW = 16.3pF x (RTON + 6.5k)
TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON current is
less than 10μA, the MAX17021/MAX17082/MAX17482 disable the controller, set the TON open fault
latch, and pull DL_ and DH_ low.
3.3V CLKEN Input Supply. V3P3 input supplies the CLKEN CMOS push-pull logic output. Connect to
the system’s standard 3.3V supply voltage before SHDN is pulled high for proper IMVP-6.5 operation.
Clock Enable Push-Pull Logic Output. This inverted logic output indicates when the output voltage
sensed at FB is in regulation. During soft-start, shutdown, and when the FB is out of regulation, the
MAX17021/MAX17082/MAX17482 pull CLKEN up to V3P3. During VID transitions, the controller forces
CLKEN low. Except during the power-up sequence, CLKEN is the inverse of PWRGD. See the Startup
Timing Diagram (Figure 10). When in pulse-skipping mode (DPRSLPVR high), the upper CLKEN threshold
is disabled.
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and powerdown; if FB is in regulation then PWRGD is high impedance.
During startup, PWRGD is held low and continues to be low while the part is in boot mode and until
5ms (typ) after CLKEN goes low.
PWRGD is forced low in shutdown.
PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions).
When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked
during downward transitions.
A pullup resistor on PWRGD causes additional finite shutdown current.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
PIN
20
21
22
23
24
25
26
27
28
29
30
31
NAME
FUNCTION
Phase-Good Current-Balance Open-Drain Output. Used to signal the system that one of the two
phases either has a fault condition or is not matched with the other. Detection is done by identifying
the need for a large on-time difference between phases in order to achieve or move towards current
PHASEGD balance. PHASEGD is low in shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in one-phase operation (DPRSLPVR = high or PSI = low).
Boost Flying-Capacitor Connection for Phase 2. BST2 provides the upper supply rail for the DH2 highBST2
side gate driver. An internal switch between VDD and BST2 charges the flying capacitor while the lowside MOSFET is on (DL2 pulled high and LX2 pulled to ground).
Inductor Connection for Phase 2. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
LX2
Also used as an input to the controller’s zero-crossing comparator for phase 2.
High-Side Gate-Driver Output for Phase 2. DH2 swings from LX2 to BST2. The controller pulls DH2 low
DH2
in shutdown.
Low-Side Gate-Driver Output for Phase 2. DL2 swings from GND to VDD. DL2 is forced low in skip mode
DL2
after detecting an inductor current zero crossing. DL2 is forced low during one-phase operation (PSI =
GND or CSP2 = VCC).
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
VRHOT
1.5V (30% of VCC). VRHOT is high impedance in shutdown.
Driver Supply Voltage Input. VDD is the supply voltage used to internally power the low-side gate
drivers and refresh the BST_ flying capacitors during the off-times. Connect VDD to the 4.5V to 5.5V
VDD
system supply voltage. Bypass VDD to the system power ground with a 1μF each or greater ceramic
capacitor.
Low-Side Gate-Driver Output for Phase 1. DL1 swings from GND to VDD. DL1 is forced high when an output
DL1
overvoltage fault is detected, overriding any negative current-limit condition that might be present. DL1 is
forced low after soft-shutdown or in skip mode after detecting an inductor current zero crossing.
High-Side Gate-Driver Output for Phase 1. DH1 swings from LX1 to BST1. The controller pulls DH1 low
DH1
in shutdown.
Inductor Connection for Phase 1. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
LX1
Also used as an input to the controller’s zero-crossing comparator for phase 1.
Boost Flying-Capacitor Connection for Phase 1. BST1 provides the upper supply rail for the DH1 highBST1
side gate driver. An internal switch between VDD and BST1 charges the flying capacitor while the lowside MOSFET is on (DL1 is pulled high and LX1 is pulled to ground).
IMVP-6+ Slew-Rate Select Input. This 1.0V logic input signal from the IMVP-6+ system is usually the
logical complement of the DPRSLPVR signal. However, the IMVP-6+ specification supports a special
slow C4 exit condition that allows both DPRSTP and DPRSLPVR to be pulled high simultaneously.
When this occurs, the voltage-transition slew rate reduces to 1/4 the nominal (RTIME-based) slew rate
for the duration of this logic condition. The slew rate returns to normal when either DPRSLPVR or
DPRSTP
DPRSTP is pulled low:
(MAX17021)
DPRSLPVR DPRSTP
SLEW RATE
0
0
Nominal slew rate
0
1
Nominal slew rate
1
0
Nominal slew rate
1
1
Slew rate reduced to 1/4 of nominal
IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and “slow”
SLOW
(half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is set by
(MAX17082/
the TIME resistance as defined above. When SLOW is forced low, the slew rate is reduced to half the
MAX17482)
nominal slew rate.
______________________________________________________________________________________
17
MAX17021/MAX17082/MAX17482
Pin Description (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Pin Description (continued)
PIN
NAME
32–38
D0–D6
39
CSP1
40
CSN1
—
EP
18
FUNCTION
Low-Voltage VID DAC Code Input. The D0–D6 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. The output voltage is set by the VID code
indicated by the logic-level voltages on D0–D6 (see Table 4).
Positive Current-Sense Input for Phase 1. Connect CSP1 to the positive terminal of the inductor currentsensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4).
Negative Current-Sense Input for Phase 1. Connect CSN1 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
Under VCC UVLO conditions and after soft-shutdown is completed, CSN1 is internally pulled to GND
through a 10 FET to discharge the output.
Exposed Pad. Internally connected to GND. Connect to the ground plane through a thermally
enhanced via. For the MAX17021/MAX17082/MAX17482, the exposed pad is the only GND
connection and must be properly soldered.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ON OFF (VRON)
31
14
15
1
32
33
34
35
VID INPUTS
36
37
38
SHDN
DPRSLPVR
VDD
PSI
D0
TON
D1
D2
D3
BST1
D4
DH1
D5
LX1
D6
CSP1
ILIM
TIME
CCI
CSN2
V3P3
CSP2
R4
1.9kΩ
16
30
R9
0Ω
28
C4
29 0.22μF
27
NLO
19
25
18
R6
13kΩ
VCC
2
PHASEGD
BST2
PWRGD
DH2
VRHOT
LX2
CLKEN
NHI
DL2
PWR
L1
R10
1.21kΩ
R11
1.50kΩ
D1
R12
20kΩ
7
12
C10
1000pF
C11
0.22μF
21
R13
0Ω
23
C8
22 0.22μF
24
NLO
THRM
NTC3
100kΩ
B = 4250
NTC1
10kΩ
B = 3380
C7
0.22μF
C5
0.22μF
40
COUT
PWR
39
11
INPUT
7V TO 24V
CIN
R5
10kΩ
20
SWITCHING FREQUENCY (fSW = 1/TSW):
TSW = 16.3pF x (RTON + 6.5kΩ)
PWR
CSN1
5
C2
1.0μF
RTON
200kΩ
MAX17021
17
R3
56Ω
AGND
5V BIAS
INPUT
PWR
AGND
3.3V
1.1V
26
PGDIN
DL1
4
R1
12.1kΩ
C1
1.0μF
DPRSTP
VALLEY CURRENT LIMIT SET TO ILIM
VLIMIT = 0.2V x R1/(R1 + R2)
SLEW RATE SET BY TIME BIAS CURRENT
dV/dt = 12.5mV/μs x 71.5kΩ/(R1 + R2)
R2
59.0kΩ
VCC
R19
10Ω
6
MAX17021/MAX17082/MAX17482
13
C6
OPEN
AGND
DCR THERMAL
COMPENSATION
C9
0.22μF
C12
OPEN
AGND
NHI
CORE
OUTPUT
NTC2
10kΩ
B = 3380
R15
1.50kΩ
COUT
R16
20kΩ
R14
1.21kΩ
PWR
L2
D1
PWR
LOAD-LINE ADJUSTMENT:
RFB = RDROOP/(RSENSE x 600μs)
AGND
3
FBAC
N.C.
FB
GNDS
GND (EP)
AGND
9
8
10
RFB
4.32kΩ
1%
R20
10Ω
C13
1000pF
AGND
VCC_SENSE
REMOTE-SENSE
INPUTS
R21
10Ω
VSS_SENSE
C14
1000pF
PWR
R22
25Ω
AGND
REMOTE-SENSE FILTERS
R23
25Ω
PWR
CATCH RESISTORS
REQUIRED WHEN CPU NOT
POPULATED
Figure 1. Standard 2-Phase IMVP-6+ Application Circuit
______________________________________________________________________________________
19
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Detailed Description
Table 1 lists the component selection for standard
applications. Table 2 lists component suppliers for the
MAX17021/MAX17082/MAX17482/MAX17482.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator
with voltage feed-forward (Figure 3). This architecture
relies on the output filter capacitor’s ESR to act as the
current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional
to input voltage, and directly proportional to output voltage or the difference between the main and secondary
inductor currents (see the On-Time One-Shot section).
Another one-shot sets a minimum off-time. The on-time
one-shot triggers when the error comparator goes low,
the inductor current of the selected phase is below the
valley current-limit threshold, and the minimum off-time
one-shot times out. The controller maintains 180° out-ofphase operation by alternately triggering the main and
secondary phases after the error comparator drops
below the output-voltage set point.
Table 1. Component Selection for Standard Applications
DESIGN
PARAMETERS
IMVP-6+ SV
IMVP-6+ LV
IMVP-6.5
AUBURNDALE SV
CORE
IMVP-6.5
AUBURNDALE LV
CORE
CIRCUIT
FIGURE 1
FIGURE 1
FIGURE 2
FIGURE 2
7V to 20V
7V to 20V
7V to 20V
7V to 20V
Maximum Load Current
(TDC Current)
44A
(34A)
23A
(19A)
50A
(37A)
28A
(19A)
Transient Load Current
35A
(10A/μs)
18A
(10A/μs)
35A
(10A/μs)
23A
(10A/μs)
Load Line
-2.1mV/A
-4mV/A
-1.9mV/A
-3mV/A
TON Resistance (RTON)
200k (f SW = 300kHz)
200k (f SW = 300kHz)
200k (f SW = 300kHz)
200k (f SW = 300kHz)
Inductance (L)
NEC/TOKIN
MPC1055LR36 0.36μH,
32A, 0.8m
NEC/TOKIN
MPC1055LR36 0.36μH,
32A, 0.8m
NEC/TOKIN
MPC1055LR36 0.36μH,
32A, 0.8m
NEC/TOKIN
MPC1055LR36 0.36μH,
32A, 0.8m
High-Side MOSFET (NH)
Siliconix 1x Si4386DY
7.8m /9.5m (typ/max)
Siliconix 1x Si4386DY
7.8m /9.5m (typ/max)
Siliconix 1x Si4386DY
7.8m /9.5m (typ/max)
Siliconix 1x Si4386DY
7.8m /9.5m (typ/max)
Siliconix 2x Si4642DY
3.9m /4.7m (typ/max)
4x 330μF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
4x 10μF, 25V ceramic
(1210)
Siliconix 2x Si4642DY
3.9m /4.7m (typ/max)
3x 330μF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
4x 10μF, 25V ceramic
(1210)
Siliconix 2x Si4642DY
3.9m /4.7m (typ/max)
4x 330μF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
4x 10μF, 25V ceramic
(1210)
Siliconix 2x Si4642DY
3.9m /4.7m (typ/max)
3x 330μF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
28x 10μF, 6V ceramic
(0805)
4x 10μF, 25V ceramic
(1210)
Input-Voltage Range
COMPONENTS
Low-Side MOSFET (NL)
Output Capacitors
(COUT)
Input Capacitors (CIN)
20
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
IMVP-6+ SV
IMVP-6+ LV
IMVP-6.5
AUBURNDALE SV
CORE
IMVP-6.5
AUBURNDALE LV
CORE
TIME-ILIM Resistance
(R1)
10k
10k
10k
10k
ILIM-GND Resistance
(R2)
59k
59k
59k
59k
FB Resistance (RFB)
4.32k
8.45k
4.02k
6.34k
IMON Resistance
LX_-CSP_ Resistance
N/A
N/A
9.09k
18.2k
1.21k
1.21k
1.21k
1.21k
1.50k
1.50k
1.50k
1.50k
20k
20k
20k
20k
DCR Sense NTC (NTC1)
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
DCR Sense
Capacitance (CSENSE)
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
2x 0.22μF, 6V ceramic
(0805)
DESIGN
PARAMETERS
CSP_-CSN_ Series
Resistance (R6)
Parallel NTC
Resistance
Table 2. Component Suppliers
SUPPLIER
WEBSITE
SUPPLIER
WEBSITE
AVX Corp.
www.avxcorp.com
Pulse Engineering
www.pulseeng.com
BI Technologies
www.bitechnologies.com
Renesas Technology
Corp.
www.renesas.com
Central
Semiconductor Corp.
www.centralsemi.com
SANYO Electric Co,
Ltd.
www.sanyodevice.com
Fairchild
Semiconductor
www.fairchildsemi.com
Siliconix (Vishay)
www.vishay.com
International Rectifier
www.irf.com
Sumida
www.sumida.com
KEMET Corp
www.kemet.com
Taiyo Yuden
www.t-yuden.com
NEC/TOKIN Corp.
www.nec-tokin.com
TDK Corp.
www.component.tdk.com
Panasonic Corp.
www.panasonic.com
TOKO America, Inc.
www.tokoam.com
______________________________________________________________________________________
21
MAX17021/MAX17082/MAX17482
Table 1. Component Selection for Standard Applications (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
13
ON OFF (VRON)
14
31
AGND
15
1
32
33
34
35
VID INPUTS
36
37
38
SHDN
SLOW
VDD
PSI
5
D0
TON
D1
D2
D3
BST1
D4
DH1
D5
LX1
D6
MAX17082
MAX17482
ILIM
CSN1
TIME
CSN2
V3P3
1.1V
R3
56Ω
R4
1.9kΩ
CSP2
R5
10kΩ
20
19
25
18
R6
13kΩ
VCC
2
30
PWRGD
BST2
VRHOT
DH2
LX2
THRM
27
NLO
NHI
DL2
PWR
L1
R10
1.21kΩ
R11
1.50kΩ
D1
R12
20kΩ
7
12
21
C10
1000pF
C11
0.22μF
R13
0Ω
23
C8
22 0.22μF
24
NLO
NTC1
10kΩ
B = 3380
C7
0.22μF
C5
0.22μF
40
COUT
PWR
39
11
INPUT
7V TO 24V
CIN
C4
29 0.22μF
C6
OPEN
AGND
DCR THERMAL
COMPENSATION
C9
0.22μF
C12
OPEN
AGND
NHI
CORE
OUTPUT
NTC2
10kΩ
B = 3380
R15
1.50kΩ
COUT
R16
20kΩ
R14
1.21kΩ
PWR
L2
D1
PWR
LOAD-LINE ADJUSTMENT:
RFB = RDROOP/(RSENSE x 600μs)
AGND
C15
0.022μF
R9
0Ω
28
PHASEGD
CLKEN
SWITCHING FREQUENCY (fSW = 1/TSW):
TSW = 16.3pF x (RTON + 6.5kΩ)
RTON
200kΩ
16
NTC3
100kΩ
B = 4250
R7
4.7kΩ
C2
1.0μF
PWR
CSP1
CCI
17
AGND
PWR
AGND
3.3V
26
5V BIAS
INPUT
PGDIN
DL1
4
R1
12.1kΩ
C1
1.0μF
DPRSLPVR
VALLEY CURRENT LIMIT SET TO ILIM
VLIMIT = 0.2V x R1/(R1 + R2)
SLEW RATE SET BY TIME BIAS CURRENT
dV/dt = 12.5mV/μs x 71.5kΩ/(R1 + R2)
R2
59.0kΩ
VCC
R19
10Ω
6
3
IMON
FBAC
FB
R8
9.09kΩ
GNDS
VSS_SENSE
9
8
RFB
4.02kΩ
1%
10
GND (EP)
AGND
R20
10Ω
C13
1000pF
AGND
VCC_SENSE
REMOTE-SENSE
INPUTS
R21
10Ω
VSS_SENSE
C14
1000pF
PWR
R22
25Ω
AGND
REMOTE-SENSE FILTERS
R23
25Ω
PWR
CATCH RESISTORS
REQUIRED WHEN CPU NOT
POPULATED
Figure 2. Standard 2-Phase IMVP-6.5 (Calpella) Application Circuit
22
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
MAX17021/MAX17082/MAX17482
BST2
THRM
DH2
MAX17021
(MAX17082/MAX17482)
VRHOT
EN2
LX2
SECONDARY
PHASE DRIVERS
DL2
GND
0.3 x VCC
BLANK
CSP2
PHASEGD
10x
CSN2
Q
CSP1
TRIG
ONE-SHOT
ILIM
Q
TIME
CCI
PHASE 2
ON-TIME
10x
CSN1
5ms
STARTUP
DELAY
CURRENTBALANCE
FAULT
MINIMUM
OFF-TIME
TRIG
200kΩ
CSN2
ONE-SHOT
Gm(CCI)
PHASE 1
ON-TIME
VCC
CSP1
FB
ONE-SHOT
REF
(2.0V)
Q
CSP2
TRIG
Gm(CCI)
CSN1
TON
GND
SLEW
D0–D6
DAC
PGDIN
Q
DH1
S
SHDN
TARGET
Q
LX1
S
Q
Q
GND
LX1
1mV
T
R
VDD
SKIP
FAULT
BST1
MAIN PHASE
DRIVERS
R
R-TO-I
CONVERTER
DL1
GND
TARGET
- 300mV
PWRGD
5ms
STARTUP
DELAY
FB
CLKEN
BLANK
(SLOW)
(MAX17082/
MAX17482)
DPRSTP
CSN_
PSI
Gm(FB)
DPRSLPVR
CSP_
PGDIN
MODE/PHASE/
SLEW-RATE
CONTROL
x2
V3P3
60μs
STARTUP
DELAY
SKIP
EN2
SLEW
GNDS
FBAC
TARGET
+ 200mV
CSP_
x2
CSN_
Gm(IMON)
IMON
Figure 3. Functional Diagram
______________________________________________________________________________________
23
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Dual 180° Out-of-Phase Operation
The two phases in the MAX17021/MAX17082/
MAX17482 operate 180° out-of-phase to minimize input
and output filtering requirements, reduce electromagnetic
interference (EMI), and improve efficiency. This effectively
lowers component count—reducing cost, board space,
and component power requirements—making the
MAX17021/MAX17082/MAX17482 ideal for high-power,
cost-sensitive applications.
Typically, switching regulators provide power using
only one phase instead of dividing the power among
several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high RMS ripple current can lower
efficiency due to I2R power loss associated with the
input capacitor’s effective series resistance (ESR).
Therefore, the system typically requires several lowESR input capacitors in parallel to minimize input-voltage ripple, to reduce ESR-related power losses, and to
meet the necessary RMS ripple current rating.
With the MAX17021/MAX17082/MAX17482, the controller shares the current between two phases that
operate 180° out-of-phase, so the high-side MOSFETs
never turn on simultaneously during normal operation.
The instantaneous input current of either phase is effectively halved, resulting in reduced input-voltage ripple,
ESR power loss, and RMS ripple current (see the Input
Capacitor Selection section). Therefore, the same performance can be achieved with fewer or less-expensive
input capacitors.
+5V Bias Supply (VCC and VDD)
The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
system supply. Keeping the bias supply external to the
IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum
current drawn is:
IBIAS = ICC + fSW (QG(LOW) + QG(HIGH))
where ICC is provided in the Electrical Characteristics
table, fSW is the switching frequency, and QG(LOW) and
Q G(HIGH) are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V.
VIN and VDD can be tied together if the input power
source is a fixed +4.5V to +5.5V supply. If the +5V bias
supply is powered-up prior to the battery supply, the
24
enable signal (SHDN going from low to high) must be
delayed until the battery voltage is present to ensure
startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set
the switching period TSW = 1/fSW, per phase:
TSW = 16.3pF x (RTON + 6.5kΩ)
A 96.75kΩ to 303.25kΩ corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be
acceptable in ultra-portable devices where the load
currents are lower and the controller is powered from a
lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of
component size and board space.
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an overvoltage condition on the output. The MAX17021/
MAX17082/MAX17482 detect an open-circuit fault if the
TON current drops below 10μA for any reason—the
TON resistor (RTON) is unpopulated, a high resistance
value is used, the input voltage is low, etc. Under these
conditions, the MAX17021/MAX17082/MAX17482 stop
switching (DH_ and DL_ pulled low) and immediately
set the fault latch. Toggle SHDN or cycle the V CC
power supply below 0.5V to clear the fault latch and
reactivate the controller.
On-Time One-Shot
The core of each phase contains a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages.
The main high-side switch on-time is inversely proportional to the input voltage as measured by the TON
input, and proportional to the feedback voltage (VFB):
tON(MAIN) =
TSW ( VFB + 0.075V )
VIN
where the switching period (TSW = 1/fSW) is set by the
resistor at the TON pin, and 0.075V is an approximation
to accommodate the expected drop across the lowside MOSFET switch.
The one-shot for the secondary phase varies the ontime in response to the input voltage and the difference
between the main and secondary inductor currents.
Two identical transconductance amplifiers integrate the
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
tor current reverses at light- or negative-load currents.
With reversed inductor current, the inductor’s EMF
causes LX_ to go high earlier than normal, extending
the on-time by a period equal to the DH_-rising dead
time. For loads above the critical conduction point,
where the dead-time effect is no longer a factor, the
actual switching frequency (per phase) is:
fSW =
( VOUT + VDIS )
tON ( VIN + VDIS - VCHG )
where VDIS is the sum of the parasitic voltage drops in the
inductor discharge path, including synchronous rectifier,
inductor, and PCB resistances; VCHG is the sum of the
parasitic voltage drops in the inductor charge path,
including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above.
Current Sense
⎛V
+ 0.075V ⎞
tON(SEC) = TSW ⎜ CCI
VIN
⎝
⎠⎟
⎛ V + 0.07
⎛ ICCIZCCI ⎞
75V ⎞
= TSW ⎜ FB
⎟⎠ + TSW ⎜⎝ V
⎟
VIN
⎝
IN ⎠
= (Main On-ttime) + ( Secondary Current Balance Correction)
This algorithm results in a nearly constant switching frequency and balanced inductor currents despite the
lack of a fixed-frequency clock generator. The benefits
of a constant switching frequency are twofold: first, the
frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band; second, the
inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and
predictable output-voltage ripple. The on-time oneshots have good accuracy at the operating points
specified in the Electrical Characteristics table. Ontimes at operating points far removed from the conditions specified in the Electrical Characteristics table
can vary over a wider range.
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical
Characteristics table are influenced by switching
delays in the external high-side MOSFET. Resistive
losses, including the inductor, both MOSFETs, output
capacitor ESR, and PCB copper losses in the output
and ground tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only during forced-PWM operation
and dynamic output-voltage transitions when the induc-
The output current of each phase is sensed. Low-offset
amplifiers are used for current balance, voltage-positioning gain, and current limit. Sensing the current at
the output of each phase offers advantages, including
less noise sensitivity, more accurate current sharing
between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output
inductor.
Using the DC resistance (RDCR) of the output inductor
allows higher efficiency. In this configuration, the initial
tolerance and temperature coefficient of the inductor’s
DCR must be accounted for in the output-voltage
droop-error budget and power monitor. This currentsense method uses an RC filtering network to extract
the current information from the output inductor (see
Figure 4). The resistive divider used should provide a
current-sense resistance (RCS) low enough to meet the
current-limit requirements, and the time constant of the
RC network should match the inductor’s time constant
(L/RCS):
⎛ R2 ⎞
RCS = ⎜
R
⎝ R1 + R2 ⎟⎠ DCR
and:
RCS =
L ⎡1
1 ⎤
+
CEQ ⎢⎣ R1 R2 ⎥⎦
where RCS is the required current-sense resistance and
RDCR is the inductor’s series DC resistance.
______________________________________________________________________________________
25
MAX17021/MAX17082/MAX17482
difference between the master and slave current-sense
signals. The summed output is internally connected to
CCI, allowing adjustment of the integration time constant with a compensation network connected between
CCI and FB. The resulting compensation current and
voltage are determined by the following equations:
ICCI = Gm(VCSP1 - VCSN1) - Gm(VCSP2 - VCSN2)
VCCI = VFB + ICCIZCCI
where ZCCI is the impedance at the CCI output. The
secondary on-time one-shot uses this integrated signal
(VCCI) to set the secondary high-side MOSFETs ontime. When the main and secondary current-sense signals (VCM = VCSP1 - VCSN1 and VCS = VCSP2 - VCSN2)
become unbalanced, the transconductance amplifiers
adjust the secondary on-time, which increases or
decreases the secondary inductor current until the current-sense signals are properly balanced:
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load.
To minimize the current-sense error due to the currentsense inputs’ bias current (ICSP_ and ICSN_), choose
R1||R2 to be less than 2kΩ and use the previous equation to determine the sense capacitance (CEQ). Choose
capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is
recommended for this current-sense method. See the
Voltage Positioning and Loop Compensation section for
detailed information.
resistor (see Figure 4). The ESL induced-voltage step
does not affect the average current-sense voltage, but
results in a significant peak current-sense voltage error
that results in unwanted offsets in the regulation voltage
and results in early current-limit detection. Similar to the
inductor DCR sensing method above, the RC filter’s time
constant should match the L/R time constant formed by
the current-sense resistor’s parasitic inductance:
When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC
filter to eliminate the AC voltage step caused by the
equivalent series inductance (LESL) of the current-sense
where LESL is the equivalent series inductance of the
current-sense resistor, RSENSE is current-sense resistance value, and CEQ and R1 are the time-constant
matching components.
LESL
= CEQR1
RSENSE
INPUT (VIN)
CIN
DH_
NH
SENSE RESISTOR
LX_
MAX17021
DL_
MAX17082
MAX17482
LESL
L
NL
RSENSE
COUT
DL
PGND
R1
CEQR1 =
LSENSE
RSENSE
CEQ
CSP_
CSN_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN)
CIN
DH_
NH
INDUCTOR
LX_
MAX17021
DL_
MAX17082
MAX17482
L
RDCR
RCS =
NL
DL
COUT
R1
B) LOSSLESS INDUCTOR SENSING
R2
R1 + R2
)
RDCR
R2
RDCR =
PGND
CSP_
CSN_
(
[
L
1 1
+
CEQ R1 R2
]
CEQ
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 4. Current-Sense Methods
26
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
VOS(IBAL)
IOS(IBAL) = ILMAIN - ILSEC =
RSENSE
where RSENSE is the effective sense resistance seen at
the current-sense pins and VOS(IBAL) is the current-balance offset specification in the Electrical
Characteristics table.
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
Current Limit
The current-limit circuit employs a unique “valley” current-sensing algorithm that uses current-sense resistors
between the current-sense inputs (CSP_ to CSN_) as
the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
either phase trips the current limit, both phases are
effectively current limited since the interleaved controller does not initiate a cycle with either phase.
Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage.
When combined with the undervoltage-protection cir-
cuit, this current-limit method is effective in almost
every circumstance.
The positive valley current-limit threshold voltage at
CSP_ to CSN_ equals precisely 1/10 of the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
VCC to set the default current-limit threshold setting of
22.5mV (typ).
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immediately activates an on-time pulse—DL_ turns off, and
DH_ turns on—allowing the inductor current to remain
above the negative-current threshold.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP_, CSN_).
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop)
The MAX17021/MAX17082/MAX17482 include a
transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated by summing the current-sense inputs, which
differentially sense the voltage across either currentsense resistors or the inductor’s DCR. The amplifier’s
output connects directly to the regulator’s voltage-positioned feedback input (FB), so the resistance between
FB and the output-voltage sense point determines the
voltage-positioning gain:
VOUT = VTARGET - RFB|FB
where the target voltage (VTARGET) is defined in the
Nominal Output-Voltage Selection section, and the FB
amplifier’s output current (IFB) is determined by the
sum of the current-sense voltages:
ηPH
IFB = Gm(FB) ∑ VCSX
X =1
where VCS = VCSP_ - VCSN_ is the differential currentsense voltage, and G m(FB) is typically 600μS as
defined in the Electrical Characteristics table.
______________________________________________________________________________________
27
MAX17021/MAX17082/MAX17482
Current Balance
The MAX17021/MAX17082/MAX17482 integrate the difference between the current-sense voltages and adjust
the on-time of the secondary phase to maintain current
balance. The current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side
MOSFETs. With active current balancing, the current mismatch is determined by the current-sense resistor values
and the offset voltage of the transconductance amplifiers:
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Differential Remote Sense
The MAX17021/MAX17082/MAX17482 include differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the
processor’s power pins. The feedback-sense node connects to the voltage-positioning resistor (R FB ). The
ground-sense (GNDS) input connects to an amplifier
that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the
voltage-positioning resistor (RFB), and ground-sense
(GNDS) input directly to the processor’s remote-sense
outputs, as shown in Figure 1.
Integrator Amplifier
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure
3), allowing accurate DC output-voltage regulation
regardless of the output ripple voltage. The integrator
amplifier has the ability to shift the output voltage by
±100mV (typ). The differential input-voltage range is at
least ±60mV total, including DC offset and AC ripple.
The MAX17021/MAX17082/MAX17482 disable the integrator by connecting the amplifier inputs together at the
beginning of all VID transitions done in pulse-skipping
mode (DPRSLPVR = high). The integrator remains disabled until 20μs after the transition is completed (the
internal target settles) and the output is in regulation
(edge detected on the error comparator).
Transient-Overlap Operation
When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 180° out-ofphase when a transient occurs actually respond slower
than an equivalent single-phase controller. To provide
fast-transient response, the MAX17021/MAX17082/
MAX17482 support a phase-overlap mode, which
allows the dual regulators to operate in-phase when
heavy load transients are detected, effectively reducing
28
the response time. After either high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs
during the next on-time cycle. This maximizes the total
inductor current slew rate. The phases remain overlapped until the output voltage exceeds the regulation
voltage after the minimum off-time expires.
After the phase-overlap mode ends, the controller automatically begins with the opposite phase. For example, if the
secondary phase provided the last on-time pulse before
overlap operation began, the controller starts switching
with the main phase when overlap operation ends. Table 3
is the operating mode truth table.
Nominal Output-Voltage Selection
The nominal no-load output voltage (V TARGET ) is
defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (VGNDS) as
defined in the following equation:
VTARGET = VFB = VDAC + VGNDS
where VDAC is the selected VID voltage. On startup, the
MAX17021/MAX17082/MAX17482 slew the target voltage from ground to the preset boot voltage.
DAC Inputs (D0–D6)
The digital-to-analog converter (DAC) programs the
output voltage using the D0–D6 inputs. D0–D6 are lowvoltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0–D6 unconnected.
Changing D0–D6 initiates a transition to a new outputvoltage level. Change D0–D6 together, avoiding greater
than 20ns skew between bits. Otherwise, incorrect DAC
readings might cause a partial transition to the wrong
voltage level followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. The available DAC codes and resulting output
voltages are compatible with the IMVP-6/IMVP-6+ and
IMVP-6.5 (Table 4) specifications.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
INPUTS
SHDN
GND
DPRSTP
DPRSLPVR
(SLOW)
X
Rising
X
High
X
(High)
High
X
(High)
High
High
Falling
High
Low
(High)
High
(Low)
X
X
X
X
Low
Low
High
High
X
X
PSI
PHASE
OPERATION*
X
Disabled
X
Multiphase
pulse-skipping
1/8 RTIME slew
rate
Startup/Boot. When SHDN is pulled high, the MAX17021/
MAX17082/MAX17482 begin the startup sequence. The controller
enables the PWM regulator and ramps the output voltage up to the
boot voltage. See Figure 10.
High
Multiphase
forced-PWM
nominal RTIME
slew rate
Full Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4).
Low
1-phase forcedPWM
nominal RTIME
slew rate
Intermediate Power. The no-load output voltage is determined by
the selected VID DAC code (D0–D6, Table 4). When PSI is pulled
low, the MAX17021/MAX17082/MAX17482 immediately disable
phase 2. DH2 and DL2 are pulled low.
1-phase pulseskipping
nominal RTIME
slew rate
Deeper Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (D0–D6, Table 4). When
DPRSLPVR is pulled high, the MAX17021/MAX17082/MAX17482
immediately enter one-phase pulse-skipping operation, allowing
automatic PWM/PFM switchover under light loads. The PWRGD
and CLKEN upper thresholds are blanked during downward
transitions. DH2 and DL2 are pulled low.
X
1-phase pulseskipping
Deeper Sleep Slow Exit Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSTP is pulled high while DPRSLPVR is already high,
the MAX17021 remains in one-phase pulse-skipping operation,
allowing automatic PWM/PFM switchover under light loads, but
reduces its slew rate to 1/4 of normal. When SLOW is pulled low,
the MAX17082/MAX17482 reduce their slew rate to 1/2 of normal.
The PWRGD and CLKEN upper thresholds are blanked. DH2 and
DL2 are pulled low.
X
Multiphase
forced-PWM
1/8 RTIME slew
rate
Shutdown. When SHDN is pulled low, the MAX17021/MAX17082/
MAX17482 immediately pull PWRGD and PHASEGD low, CLKEN
becomes high, all enabled phases are activated, and the output
voltage is ramped down to ground. Once the output reaches 0V,
the controller enters the low-power shutdown state. See Figure 10.
Disabled
Fault Mode. The fault latch has been set by the MAX17021/
MAX17082/MAX17482 UVP or thermal-shutdown protection, or by the
OVP protection. The controller remains in fault mode until VCC power
is cycled or SHDN toggled.
X
X
OPERATING MODE
Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1μA (max).
*Multiphase operation—all enabled phases active.
______________________________________________________________________________________
29
MAX17021/MAX17082/MAX17482
Table 3. Operating Mode Truth Table
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Table 4. IMVP-6+/IMVP-6.5 Output-Voltage VID DAC Codes
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE
(V)
0
0
0
0
0
0
0
1.5000
1
0
0
0
0
0
0
0.7000
0
0
0
0
0
0
1
1.4875
1
0
0
0
0
0
1
0.6875
0
0
0
0
0
1
0
1.4750
1
0
0
0
0
1
0
0.6750
0
0
0
0
0
1
1
1.4625
1
0
0
0
0
1
1
0.6625
0
0
0
0
1
0
0
1.4500
1
0
0
0
1
0
0
0.6500
0
0
0
0
1
0
1
1.4375
1
0
0
0
1
0
1
0.6375
0
0
0
0
1
1
0
1.4250
1
0
0
0
1
1
0
0.6250
0
0
0
0
1
1
1
1.4125
1
0
0
0
1
1
1
0.6125
0
0
0
1
0
0
0
1.4000
1
0
0
1
0
0
0
0.6000
0
0
0
1
0
0
1
1.3875
1
0
0
1
0
0
1
0.5875
0
0
0
1
0
1
0
1.3750
1
0
0
1
0
1
0
0.5750
0
0
0
1
0
1
1
1.3625
1
0
0
1
0
1
1
0.5625
0
0
0
1
1
0
0
1.3500
1
0
0
1
1
0
0
0.5500
0
0
0
1
1
0
1
1.3375
1
0
0
1
1
0
1
0.5375
0
0
0
1
1
1
0
1.3250
1
0
0
1
1
1
0
0.5250
0
0
0
1
1
1
1
1.3125
1
0
0
1
1
1
1
0.5125
0
0
1
0
0
0
0
1.3000
1
0
1
0
0
0
0
0.5000
0
0
1
0
0
0
1
1.2875
1
0
1
0
0
0
1
0.4875
0
0
1
0
0
1
0
1.2750
1
0
1
0
0
1
0
0.4750
0
0
1
0
0
1
1
1.2625
1
0
1
0
0
1
1
0.4625
0
0
1
0
1
0
0
1.2500
1
0
1
0
1
0
0
0.4500
0
0
1
0
1
0
1
1.2375
1
0
1
0
1
0
1
0.4375
0
0
1
0
1
1
0
1.2250
1
0
1
0
1
1
0
0.4250
0
0
1
0
1
1
1
1.2125
1
0
1
0
1
1
1
0.4125
0
0
1
1
0
0
0
1.2000
1
0
1
1
0
0
0
0.4000
0
0
1
1
0
0
1
1.1875
1
0
1
1
0
0
1
0.3875
0
0
1
1
0
1
0
1.1750
1
0
1
1
0
1
0
0.3750
0
0
1
1
0
1
1
1.1625
1
0
1
1
0
1
1
0.3625
0
0
1
1
1
0
0
1.1500
1
0
1
1
1
0
0
0.3500
0
0
1
1
1
0
1
1.1375
1
0
1
1
1
0
1
0.3375
0
0
1
1
1
1
0
1.1250
1
0
1
1
1
1
0
0.3250
0
0
1
1
1
1
1
1.1125
1
0
1
1
1
1
1
0.3125
0
0
1
1
1
1
1
1.1125
1
0
1
1
1
1
1
0.3125
30
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE
(V)
0
1
0
0
0
0
0
1.1000
1
1
0
0
0
0
0
0.3000
0
1
0
0
0
0
1
1.0875
1
1
0
0
0
0
1
0.2875
0
1
0
0
0
1
0
1.0750
1
1
0
0
0
1
0
0.2750
0
1
0
0
0
1
1
1.0625
1
1
0
0
0
1
1
0.2625
0
1
0
0
1
0
0
1.0500
1
1
0
0
1
0
0
0.2500
0
1
0
0
1
0
1
1.0375
1
1
0
0
1
0
1
0.2375
0
1
0
0
1
1
0
1.0250
1
1
0
0
1
1
0
0.2250
0
1
0
0
1
1
1
1.0125
1
1
0
0
1
1
1
0.2125
0
1
0
1
0
0
0
1.0000
1
1
0
1
0
0
0
0.2000
0
1
0
1
0
0
1
0.9875
1
1
0
1
0
0
1
0.1875
0
1
0
1
0
1
0
0.9750
1
1
0
1
0
1
0
0.1750
0
1
0
1
0
1
1
0.9625
1
1
0
1
0
1
1
0.1625
0
1
0
1
1
0
0
0.9500
1
1
0
1
1
0
0
0.1500
0
1
0
1
1
0
1
0.9375
1
1
0
1
1
0
1
0.1375
0
1
0
1
1
1
0
0.9250
1
1
0
1
1
1
0
0.1250
0
1
0
1
1
1
1
0.9125
1
1
0
1
1
1
1
0.1125
0
1
1
0
0
0
0
0.9000
1
1
1
0
0
0
0
0.1000
0
1
1
0
0
0
1
0.8875
1
1
1
0
0
0
1
0.0875
0
1
1
0
0
1
0
0.8750
1
1
1
0
0
1
0
0.0750
0
1
1
0
0
1
1
0.8625
1
1
1
0
0
1
1
0.0625
0
1
1
0
1
0
0
0.8500
1
1
1
0
1
0
0
0.0500
0
1
1
0
1
0
1
0.8375
1
1
1
0
1
0
1
0.0375
0
1
1
0
1
1
0
0.8250
1
1
1
0
1
1
0
0.0250
0
1
1
0
1
1
1
0.8125
1
1
1
0
1
1
1
0.0125
0
1
1
1
0
0
0
0.8000
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0.7875
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0.7750
1
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0.7625
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0.7500
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0.7375
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0.7250
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0.7125
1
1
1
1
1
1
1
0
*D6–D0 = 1111111 is an OFF code for the MAX17082/MAX17482. The MAX17082/MAX17482 enter the shutdown sequence if the
OFF code is set, forcing PWRGD and PHASEGD low, and forcing CLKEN high. Exit from the OFF code follows the startup sequence.
If the OFF code is present when SHDN is pulled high, the MAX17082/MAX17482 remain off.
______________________________________________________________________________________
31
MAX17021/MAX17082/MAX17482
Table 4. IMVP-6+/IMVP-6.5 Output-Voltage VID DAC Codes (continued)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17021/MAX17082/MAX17482 respond by slewing
the internal target voltage to the new DAC code, switching to single-phase operation, and letting the output
voltage gradually drift down to the deeper sleep voltage. During the transition, the MAX17021/MAX17082/
MAX17482 blank both the upper and lower PWRGD
and CLKEN thresholds until 20μs after the internal target reaches the deeper sleep voltage. Once the 20μs
timer expires, the MAX17021/MAX17082/MAX17482
reenable the lower PWRGD and CLKEN threshold, but
keep the upper threshold blanked until the output voltage reaches the regulation level. PHASEGD remains
blanked high impedance while DPRSLPVR is high.
Output-Voltage-Transition Timing
The MAX17021/MAX17082/MAX17482 perform mode
transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output-voltage level with the lowest possible peak currents for a
given output capacitance.
At the beginning of an output-voltage transition, the
MAX17021/MAX17082/MAX17482 blank both PWRGD
thresholds, preventing the PWRGD open-drain output
from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20μs after the slew-rate controller reaches the
target output voltage, but the upper PWRGD threshold
remains blanked until the output voltage reaches the
regulation level if the controller enters pulse-skipping
operation. The slew rate (set by resistor RTIME) must be
set fast enough to ensure that the transition can be
completed within the maximum allotted time.
The MAX17021/MAX17082/MAX17482 automatically
control the current to the minimum level required to
complete the transition in the calculated time. The slewrate controller uses an internal capacitor and current
source programmed by RTIME to transition the output
voltage. The total transition time depends on RTIME, the
voltage difference, and the accuracy of the slew-rate
controller (C SLEW accuracy). The slew rate is not
dependent on the total output capacitance, as long as
the surge current is less than the current limit. For all
32
dynamic VID transitions, the transition time (tTRAN) is
given by:
t TRAN =
VNEW - VOLD
(dVTARGET dt)
where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the
slew rate, VOLD is the original output voltage, and VNEW
is the new target voltage. See TIME Slew Rate
Accuracy in Electrical Characteristics for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an outputvoltage transition is:
IL ≅
COUT
× (dVTARGET dt )
ηTOTAL
where dVTARGET/dt is the required slew rate, COUT is
the total output capacitance, and ηTOTAL is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and enter
pulse-skipping operation (see Figures 5 and 6). If the
VIDs are set to a lower voltage setting, the output drops
at a rate determined by the load and the output capacitance. The internal target still ramps as before, and
PWRGD remains blanked high impedance until 20μs
after the output voltage reaches the internal target.
• Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the
MAX17021/MAX17082/MAX17482 quickly slew
(50mV/μs min regardless of RTIME setting) the internal target voltage to the DAC code provided by the
processor as long as the output voltage is above the
new target. The controller remains in skip mode until
the output voltage equals the internal target. Once
the internal target reaches the output voltage, phase
2 is enabled. The controller blanks PWRGD,
PHASEGD, and CLKEN until 20μs after the transition
is completed. See Figure 5.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
•
Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep
voltage, the MAX17021/MAX17082/MAX17482
immediately activate all enabled phases and ramp
the output voltage to the LFM DAC code provided
by the processor at the slew rate set by RTIME. The
controller blanks PWRGD, PHASEGD, and CLKEN
until 20μs after the transition is completed. See
Figure 6.
IMVP-6+ Slow C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR high, DPRSTP pulled
high) while the output voltage is regulating to the
deeper sleep voltage, the MAX17021 remains in 1phase skip mode and ramps the output voltage to
the LFM DAC code provided by the processor at 1/4
the slew rate set by RTIME. The controller blanks
PWRGD, PHASEGD, and CLKEN until 20μs after the
transition is completed. See Figure 7.
ACTUAL VOUT
CPU CORE
VOLTAGE
INTERNAL TARGET
VID (D0–D6)
DEEPER SLEEP VID
DPRSLPVR
DPRSTP
DO NOT CARE (DPRSLPVR DOMINATES STATE)
PSI
INTERNAL
PWM CONTROL
FORCED PWM
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: VOUT > VTARGET
DH1
DH2
PWRGD
CLKEN
BLANK HIGH IMPEDANCE
BLANK LOW
PHASEGD
OVP
(MAX17021/
MAX17082 ONLY)
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
SET TO DEFAULT
tBLANK
20μs TYP
TRACKS INTERNAL TARGET
tBLANK
20μs TYP
Figure 5. C4E (C4 Early Exit) Transition
______________________________________________________________________________________
33
MAX17021/MAX17082/MAX17482
•
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ACTIVE VID
CPU CORE
VOLTAGE
ACTUAL VOUT
INTERNAL
TARGET
VID (D0–D6)
DEEPER SLEEP VID
LFM VID
DPRSLP VID
LFM VID
DPRSLPVR
DPRSTP
DO NOT CARE (DPRSLPVR DOMINATES STATE)
PSI
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
1-PHASE FORCED PWM
NO PULSES: VOUT > VTARGET
DH1
DH2
PWRGD
CLKEN
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH- IMPEDANCE
BLANK LOW
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
PHASEGD
OVP
(MAX17021/
MAX17082 ONLY)
SET TO DEFAULT
TRACKS INTERNAL TARGET
tBLANK
20μs TYP
tBLANK
20μs TYP
Figure 6. Standard C4 Transition
34
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
MAX17021/MAX17082/MAX17482
ACTIVE VID
CPU CORE
VOLTAGE
SLOW SLEW RATE
ACTUAL VOUT
INTERNAL
TARGET
VID (D0–D6)
LFM VID
DPRSLP VID
LFM VID
DEEPER SLEEP VID
DPRSLPVR
SLOW SLEW RATE
DPRSTP
DO NOT CARE (DPRSLPVR DOMINATES STATE)
PSI
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
1-PHASE FORCED PWM
NO PULSES: VOUT > VTARGET
DH1
DH2
PWRGD
BLANK HIGH IMPEDANCE
BLANK LOW
CLKEN
BLANK HIGH THRESHOLD ONLY
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
BLANK LOW
BLANK HIGH IMPEDANCE (1-PHASE OPERATION)
PHASEGD
SET TO DEFAULT
OVP
(MAX17021/
MAX17082 ONLY)
tBLANK
20μs TYP
TRACKS INTERNAL TARGET
tBLANK
20μs TYP
Figure 7. Slow C4 Transition
______________________________________________________________________________________
35
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
CPU FREQ
CPU LOAD
VID (D0–D6)
CPU CORE
VOLTAGE
PSI
INTERNAL
PWM CONTROL
2-PHASE PWM
1-PHASE PWM
2-PHASE PWM
PWRGD
BLANK HIGH IMPEDANCE
BLANK HIGH IMPEDANCE
CLKEN
BLANK LOW
BLANK LOW
BLANK HIGH IMPEDANCE
PHASEGD
tBLANK
20μs typ
tBLANK
20μs typ
32 SWITCHING CYCLES ON DH2
Figure 8. PSI Transition
PSI Transitions
When PSI is pulled low, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and
enter single-phase PWM operation (see Figure 8).
When PSI is pulled high, the MAX17021/MAX17082/
MAX17482 enable phase 2. PHASEGD is blanked high
impedance for 32 switching cycles on DH2, allowing
sufficient time/cycles for phases 1 and 2 to achieve current balance. In a typical IMVP-6 application, the VID is
reduced by 1 LSB (12.5mV) when PSI is pulled low,
and increased by 1 LSB when PSI is pulled high.
Forced-PWM Operation (Normal Mode)
During soft-shutdown, and normal operation—when the
CPU is actively running (DPRSLPVR = low)—the
MAX17021/MAX17082/MAX17482 operate with the lownoise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all
active phases, forcing the low-side gate-drive wave36
forms to constantly be the complement of the high-side
gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to
reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging
the output capacitors.
Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 50mA
per phase, depending on the external MOSFETs and
switching frequency. To maintain high efficiency under
light-load conditions, the processor can switch the controller to a low-power pulse-skipping control scheme
after entering suspend mode.
PSI determines how many phases are active when
operating in forced-PWM mode (DPRSLPVR = low).
When PSI is pulled low, the main phase remains active
but the secondary phase is disabled (DH2 and DL2
forced low).
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Automatic Pulse-Skipping Switchover
In skip mode (DPRSLPVR = high), an inherent automatic
switchover to PFM takes place at light loads (Figure 9).
This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator
senses the inductor current across the low-side
MOSFETs. Once VLX drops below the zero-crossing
comparator threshold (see the Electrical Characteristics
table), the comparator forces DL_ low. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation. The PFM/PWM crossover
occurs when the load current of each phase is equal to
1/2 the peak-to-peak ripple current, which is a function
of the inductor value (Figure 9). For a battery input
range of 7V to 20V, this threshold is relatively constant,
with only a minor dependence on the input voltage due
to the typically low duty cycles. The total load current at
the PFM/PWM crossover threshold (I LOAD(SKIP) ) is
approximately:
Δi
Δt
INDUCTOR CURRENT
When DPRSLPVR is pulled high, the MAX17021/
MAX17082/MAX17482 operate with a single-phase
pulse-skipping mode. The pulse-skipping mode
enables the driver’s zero-crossing comparator, so the
controller pulls DL1 low when it detects zero inductor
current. This keeps the inductor from discharging the
output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging
the output.
During downward transitions in pulse-skipping operation,
the controller temporarily sets the OVP threshold to
default, preventing false OVP faults when the transition to
pulse-skipping operation coincides with a VID code
change. Once the error amplifier detects that the output
voltage is in regulation, the OVP threshold tracks the
selected VID DAC code. The MAX17021/MAX17082/
MAX17482 automatically use forced-PWM operation during soft-shutdown, regardless of the DPRSLPVR and PSI
configuration.
The switching waveforms might appear noisy and asynchronous when light loading activates pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs between
PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values
produce a broader efficiency vs. load curve, while higher
values result in higher full-load efficiency (assuming that
the coil resistance remains fixed) and less output-voltage
ripple. Penalties for using higher inductor values include
larger physical size and degraded load-transient
response, especially at low input-voltage levels.
VBATT – VOUT
L
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 9. Pulse-Skipping/Discontinuous Crossover Point
⎞
⎛T V
⎞⎛V -V
ILOAD(SKIP) = ηTOTAL ⎜ SW OUT ⎟ ⎜ IN OUT ⎟
⎝
⎠
L
VIN
⎝
⎠
where ηTOTAL is the number of active phases.
______________________________________________________________________________________
37
MAX17021/MAX17082/MAX17482
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Power-Up Sequence (POR, UVLO)
The MAX17021/MAX17082/MAX17482 are enabled
when SHDN is driven high (Figure 10). The internal reference powers up first. Once the reference exceeds its
UVLO threshold, the internal analog blocks are turned
on and masked by a 50μs one-shot delay. The PWM
controller is then enabled.
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry
inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system
enables the controller, VCC is above 4.25V, and SHDN
is driven high. With the reference in regulation, the controller ramps the output voltage to the boot voltage
(1.2V for MAX17021 IMVP-6+ and 1.1V for MAX17082/
MAX17482 IMVP-6.5) at 1/8 the slew rate set by RTIME:
t TRAN(START) =
8VBOOT
( dVTARGET dt)
where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the
slew rate. The soft-start circuitry does not use a variable
current limit, so full output current is available immediately. CLKEN is pulled low approximately 60μs after the
MAX17021/MAX17082/MAX17482 reach the boot voltage
if PGDIN is high. At the same time, the MAX17021/
MAX17082/MAX17482 slew the output to the voltage set
at the VID inputs at the programmed slew rate. PWRGD
and PHASEGD become high impedance approximately
5ms after CLKEN is pulled low. The MAX17021/
MAX17082/MAX17482 automatically use forced-PWM
operation during soft-start and soft-shutdown, regardless
of the DPRSLPVR and PSI configuration.
For automatic startup, the battery voltage should be
present before VCC. If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the VCC power supply below 0.5V.
If the VCC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately
and forces a high-impedance output.
VCC
SHDN
VID (D0–D6)
INVALID
CODE
INVALID
CODE
SOFT-START =
1/8 SLEW RATE SET
BY RTIME
SOFT-SHUTDOWN =
1/8 SLEW RATE SET
BY RTIME
VBOOT
VCORE
INTERNAL
PWM CONTROL
SKIP
FORCED PWM
FORCED PWM
PHASEGD
CLKEN
PWRGD
tBLANK
5ms TYP
tBLANK
60μs TYP
tBLANK
20μs TYP
tBLANK
60μs TYP
Figure 10. Power-Up and Shutdown Sequence Timing Diagram
38
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the
slew rate. Slowly discharging the output capacitors by
slewing the output over a long period of time keeps the
average negative inductor current low (damped
response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode normally
connected between the output and ground to clamp
the negative output-voltage excursion. After the controller reaches the zero target, the MAX17021/
MAX17082/MAX17482 shut down completely—the drivers are disabled (DL1 and DL2 driven low) and the
supply current drops below 1μA.
When a fault condition—output UVLO or thermal shutdown—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V.
Current Monitor (IMON)
(MAX17021/MAX17482 Only)
The MAX17082/MAX17482 includes a unidirectional
transconductance amplifier that sources current proportional to the positive current-sense voltage. The
IMON output current is defined by:
IIMON = Gm(IMON) x Σ (VCSP_ - VCSN_)
where Gm(IMON) = 2.4mS (typ) and the IMON current is
unidirectional (sources current out of IMON only) for
positive current-sense values. For negative currentsense voltages, the IMON current is zero.
The current monitor allows the processor to accurately
monitor the CPU load and quickly calculate the power
dissipation to determine if the system is about to overheat before the significantly slower temperature sensor
signals an over-temperature alert.
Connect an external resistor between IMON and
VSS_SENSE to create the desired IMON gain based on
the following equation:
RIMON = 0.999V/(IMAX x RSENSE x Gm(IMON))
where IMAX is defined in the Current Monitor section of
the Intel IMVP-6.5 specification and based on discrete
increments (10A, 20A, 30A, 40A, etc.), RSENSE is the
typical effective value of the current-sense element
(sense resistor or inductor DCR) that is used to provide
the current-sense voltage, and Gm(IMON) is the typical
transconductance amplifier gain as defined in the
Electrical Characteristics table.
The IMON voltage is internally clamped to a maximum
of 1.1V (typ), preventing the IMON output from exceeding the IMON voltage rating even under overload or
short-circuit conditions. When the controller is disabled,
IMON is pulled to ground.
To filter the IMON signal, use an RC filter as shown in
Figure 2. The filter time constant is (R7 + R8) x C15.
Phase Fault (PHASEGD)
The MAX17021/MAX17082/MAX17482 include a phasefault output that signals the system that one of the two
phases either has a fault condition or is not matched with
the other. Detection is done by identifying the need for a
large on-time difference between phases in order to
achieve or move towards current balance.
PHASEGD is high impedance when the controller operates in one-phase mode (DPRSLPVR high or PSI low
and DPRSLPVR low). On exit to two-phase mode,
PHASEGD is forced high impedance for 32 switching
cycles on DH2.
PHASEGD is low in shutdown. PHASEGD is forced high
impedance whenever the slew-rate controller is active
(output-voltage transitions).
Temperature Comparator (VRHOT)
The MAX17021/MAX17082/MAX17482 also feature an
independent comparator with an accurate threshold
(VHOT) that tracks the analog supply voltage (VHOT =
0.3VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistor-divider between VCC and GND to
generate a voltage-regulator over-temperature monitor.
Place the thermistor as close to the MOSFETs and
inductors as possible.
Fault Protection (Latched)
Output Overvoltage Protection
(MAX17021/MAX17082 Only)
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17021/MAX17082 continuously monitor the
output for an overvoltage fault. The controller detects
an OVP fault if the output voltage exceeds the set VID
DAC voltage by more than 300mV, regardless of the
operating state. During downward transitions in
______________________________________________________________________________________
39
MAX17021/MAX17082/MAX17482
Shutdown
When SHDN goes low, the MAX17021/MAX17082/
MAX17482 enter low-power shutdown mode. PWRGD
is pulled low immediately, and the output voltage ramps
down at 1/8 the slew rate set by RTIME:
8VOUT
t TRAN(SHDN) =
(dVTARGET dt)
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold is set to default.
When the OVP circuit detects an overvoltage fault, the
MAX17021/MAX17082 immediately force DL1 high and
pull DH1 and DH2 low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in
turn, rapidly discharges the output filter capacitor and
forces the output low. If the condition that caused the
overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. Toggle SHDN or cycle
the VCC power supply below 0.5V to clear the fault
latch and reactivate the controller.
Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section).
Output Undervoltage Protection (UVP)
If the MAX17021/MAX17082/MAX17482 output voltage is
400mV below the target voltage, the controller activates
the shutdown sequence and sets the fault latch. Once
the controller ramps down to zero, it forces DL1 and DL2
high, and pulls DH1 and DH2 low. Toggle SHDN or cycle
the VCC power supply below 0.5V to clear the fault latch
and reactivate the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX17021/MAX17082/MAX17482 feature a thermal-fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault
latch and activates the soft-shutdown sequence. Once
the controller ramps down to zero, it forces DL1 and
DL2 high, and pulls DH1 and DH2 low. Toggle SHDN or
cycle the VCC power supply below 0.5V to clear the
fault latch and reactivate the controller after the junction
temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a no-fault test mode
is provided to disable the fault protection—overvoltage
protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if
it has been set. The no-fault test mode is entered by
forcing 11V to 13V on SHDN.
40
MOSFET Gate Drivers
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V IN V OUT differential exists. The high-side gate drivers
(DH_) source and sink 2.2A, and the low-side gate drivers (DL_) source 2.7A and sink 8A. This ensures
robust gate drive for high-current applications. The DH_
floating high-side MOSFET drivers are powered by
internal boost switch charge pumps at BST_, while the
DL_ synchronous-rectifier drivers are powered directly
by the 5V bias supply (VDD).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17021/MAX17082/
MAX17482 interprets the MOSFET gates as off while
charge actually remains. Use very short, wide traces
(50 mils to 100 mils wide if the MOSFET is 1in from the
driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.25Ω (typ) on-resistance. This helps
prevent DL_ from being pulled up due to capacitive
coupling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly
switches from ground to VIN. Applications with high
input voltages and long inductive driver traces might
require rising LX_ edges do not pull up the low-side
MOSFETs’ gate, causing shoot-through currents. The
capacitive coupling between LX_ and DL_ created by
the MOSFET’s gate-to-drain capacitance (CRSS), gateto-source capacitance (CISS - CRSS), and additional
board parasitics should not exceed the following minimum threshold:
⎛C
⎞
VGS(TH) > VIN ⎜ RSS ⎟
C
⎝ ISS ⎠
Typically, adding a 4700pF between DL_ and power
ground (C NL in Figure 11), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
BST_
(RBST_)*
INPUT (VIN)
CBST_
DH_
NH
•
L
LX_
CBYP
VDD
DL_
NL
(CNL)*
PGND
•
I
ILOAD(PHASE) = LOAD
ηTOTAL
(RBST_)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX_ TO DL_ CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
•
Figure 11. Gate Drive Circuit
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side
MOSFETs are too long, the high-side MOSFETs can
turn on before the low-side MOSFETs have actually
turned off. Adding a resistor less than 5Ω in series with
BST_ slows down the high-side MOSFET turn-on time,
eliminating the shoot-through currents without degrading the turn-off time (RBST_ in Figure 11). Slowing down
the high-side MOSFET also reduces the LX_ node rise
time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input-voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
Input-voltage range: The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest input voltage after drops
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input voltages result in better efficiency.
Maximum load current: There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous
load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit
ILOAD = ILOAD(MAX) x 80%.
For multiphase systems, each phase supports a
fraction of the load, depending on the current balancing. When properly balanced, the load current is
evenly distributed among each phase:
•
where ηTOTAL is the total number of active phases.
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2. The optimum frequency is also a moving target due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit. The optimum operating point is usually found
between 20% and 50% ripple current.
______________________________________________________________________________________
41
MAX17021/MAX17082/MAX17482
•
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Inductor Selection
Setting the Current Limit
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
⎛
⎞ ⎛ VOUT ⎞
VIN - VOUT
L = ηTOTAL ⎜
⎟⎜
⎟
⎝ fSWILOAD(MAX)LIR ⎠ ⎝ VIN ⎠
where ηTOTAL is the total number of phases.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
⎛ ILOAD(MAX) ⎞ ⎛ LIR ⎞
IPEAK = ⎜
⎟ ⎜ 1 + 2 ⎟⎠
⎝ ηTOTAL ⎠ ⎝
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the
worst-case output sag voltage can be determined by:
⎡⎛ VOUT TSW ⎞
⎤
⎢⎜
MIN) ⎥
⎟⎠ + tOFF(M
V
⎝
IN
⎣
⎦ +
VSAG =
⎡⎛ ( VIN - 2VOUT ) TSW ⎞
⎤
2COUT VOUT ⎢⎜
⎟ - 2tOFF(MIN) ⎥
V
⎝
⎠
⎢⎣
⎥⎦
IN
(
L ΔILOAD(MAX)
)2
ΔILOAD(MAX) ⎡⎛ VOUT TSW ⎞
⎤
+ tOFF(MIN) ⎥
⎢⎜
⎟
2COUT
VIN
⎠
⎢⎣⎝
⎥⎦
where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics table). The amount of overshoot
due to stored inductor energy can be calculated as:
VSOAR ≈
( ΔILOAD(MAX) )2 L
2ηTOTAL COUT VOUT
where ηTOTAL is the total number of active phases.
42
⎛ ILOAD(MAX) ⎞ ⎛ LIR ⎞
ILIMIT(LOW) > ⎜
⎟ ⎜ 1 - 2 ⎟⎠
⎝ ηTOTAL ⎠ ⎝
where ηTOTAL is the total number of active phases, and
ILIMIT(LOW) equals the minimum current-limit threshold
voltage divided by the current-sense resistor (RSENSE).
Output Capacitor Selection
The output filter capacitor must have low-enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In CPU VCORE converters and other applications where
the output is subject to large-load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
(RESR + RPCB ) ≤ ΔI
VSTEP
LOAD(MAX)
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For multiphase operation, the maximum ESR to meet ripple
requirements is:
⎤
⎡
VINfSWL
RESR ≤ ⎢
⎥ VRIPPLE
⎢⎣ ( VIN - ηTOTAL VOUT ) VOUT ⎥⎦
where ηTOTAL is the total number of active phases and
fSW is the switching frequency per phase. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
f
fESR ≤ SW
π
where:
fESR =
1
2πREFF COUT
and:
REFF = RESR + RDROOP + RPCB
where COUT is the total output capacitance, RESR is the
total equivalent series resistance, RDROOP is the voltage-positioning gain, and RPCB is the parasitic board
resistance between the output capacitors and sense
resistors.
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four
330μF/2.5V Panasonic SP (type SX) capacitors in parallel provide 1.5mΩ (max) ESR. With a 2mΩ droop and
0.5mΩ PCB resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high-ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the output without verifying that the circuit contains enough
voltage positioning and series PCB resistance to
ensure stability. When only using ceramic output
capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedbackloop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The multiphase Quick-PWM controllers operate out-ofphase while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several staggered stages. For duty cycles less than 100%/ηOUTPH
per phase, the IRMS requirements can be determined
by the following equation:
⎛ I
⎞
IRMS = ⎜ LOAD ⎟ ηTOTAL VOUT ( VIN - ηTOTAL VOUT )
η
V
⎝ TOTAL IN ⎠
where η TOTAL is the total number of out-of-phase
switching regulators. The worst-case RMS current
requirement occurs when operating with V IN =
2ηTOTALVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/ηTOTAL.
______________________________________________________________________________________
43
MAX17021/MAX17082/MAX17482
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the VSAG and VSOAR equations
in the Transient Response section).
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both these sums.
Ideally, the losses at VIN(MIN) should be approximately
equal to losses at V IN(MAX) , with lower losses in
between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the
size of NH (reducing RDS(ON) but with higher CGATE).
Conversely, if the losses at VIN(MAX) are significantly
higher than the losses at VIN(MIN), consider reducing
the size of NH (increasing RDS(ON) to lower CGATE). If
V IN does not vary over a wide range, the minimum
power dissipation occurs where the resistive losses
equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (RDS(ON)), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL_ gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gateto-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems might
occur (see the MOSFET Gate Drivers section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
2
⎞
⎛V
⎞⎛ I
PD (NH Re sistive) = ⎜ OUT ⎟ ⎜ LOAD ⎟ RDS(ON)
⎝ VIN ⎠ ⎝ ηTOTAL ⎠
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(NH) due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on NH:
⎛ VIN(MAX)ILOAD fSW ⎞ ⎛ QG(SW) ⎞
PD (NH Switching) = ⎜
⎟⎜ I
⎟
ηTOTAL
⎝
⎠ ⎝ GATE ⎠
C
V 2f
+ OSS IN SW
2
where COSS is the NH MOSFET’s output capacitance,
Q G(SW) is the charge needed to turn on the N H
MOSFET, and IGATE is the peak gate-drive source/sink
current (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
VIN2 x ƒSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low-battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
2
⎡ ⎛ V
⎞ ⎤⎛ I
⎞
PD (NL Re sistive) = ⎢1- ⎜ OUT ⎟ ⎥ ⎜ LOAD ⎟ RDS(ON)
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦ ⎝ ηTOTAL ⎠
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX) but are not quite high enough to exceed
where ηTOTAL is the total number of phases.
44
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
ΔI
⎛
⎞
ILOAD = ηTOTAL ⎜ IVALLEY(MAX) + INDUCTOR ⎟
⎝
⎠
2
⎛ ILOAD(MAX)LIR ⎞
= ηTOTALIVALLEY(MAX) + ⎜
⎟
2
⎝
⎠
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (DL) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase during the dead times. This diode is optional and can be
removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST_) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost
capacitors larger than 0.1μF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the highside MOSFETs’ gates:
CBST _ =
N × QGATE
200mV
where N is the number of high-side MOSFETs used for
one regulator, and QGATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
CBST_ =
2 × 24nC
= 0.24μF
200mV
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (CCCI)
integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R CCI = 200kΩ) improves transient
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the
integration time constant, resulting in larger current differences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. For most
applications, a 470pF capacitor from CCI to the switching regulator’s output works well.
Connecting the compensation network to the output
(VOUT) allows the controller to feed-forward the outputvoltage signal, especially during transients.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power-dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output-voltage
droop (Figure 3) as a function of the load. This adjustability allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall
power dissipated.
Steady-State Voltage Positioning
Connect a resistor (RFB) between FB and VOUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (RDROOP):
RFB =
RDROOP
RSENSEGm(FB)
where the effective current-sense resistance (RSENSE)
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G m(FB) ) is typically 600μS as
defined in the Electrical Characteristics table. The controller sums together the input signals of the currentsense inputs (CSP_, CSN_).
When the inductors’ DCR is used as the current-sense
element (RSENSE = RDCR), each current-sense input
should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
______________________________________________________________________________________
45
MAX17021/MAX17082/MAX17482
the current limit and cause the fault latch to trip. To protect against this possibility, you can over design the circuit to tolerate:
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Minimum Input-Voltage Requirements
and Dropout Performance
The output-voltage-adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot and the number of phases.
For best dropout performance, use the slower (200kHz)
on-time settings. When working with low input voltages,
the duty-factor limit must be calculated using worstcase values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an
error to the on-times. This error is greater at higher frequencies. Also, keep in mind that transient-response
performance of buck regulators operated too close to
dropout is poor, and bulk output capacitance must
often be added (see the V SAG equation in the
Multiphase Quick-PWM Design Procedure section.
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN)
as much as it ramps up during the on-time (ΔIUP). The
ratio h = ΔIUP/ΔIDOWN is an indicator of the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V SAG greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
⎡ VFB - VDROOP + VDIS ⎤
VIN(MIN) = ηTOTAL ⎢
⎥+
⎢⎣1 - ηTOTALh × tOFF(MIN)fSW ⎥⎦
VCHG - VDIS + VDROOP
where η TOTAL is the total number of out-of-phase
switching regulators, V FB is the voltage-positioning
droop, VDIS and VCHG are the parasitic voltage drops
in the discharge and charge paths (see the On-Time
One-Shot section), t OFF(MIN) is from the Electrical
Characteristics table. The absolute minimum input voltage is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated,
calculate V SAG to be sure of adequate transient
response.
46
Dropout design example:
VFB = 1.4V
fSW = 300kHz
tOFF(MIN) = 400ns
VDROOP = 3mV/A x 30A = 90mV
VDIS = VCHG = 150mV (30A Load)
h = 1.5 and ηTOTAL = 2:
⎡ 1.4V - 90mV + 150mV
⎤
VIN(MIN) = 2 × ⎢
⎥+
⎣1 - 2 × (0.4μs × 1.5 × 300kHz) ⎦
150mV - 150mV + 90mV = 4.96V
Calculating again with h = 1 gives the absolute limit of
dropout:
⎡ 1.4V - 90mV + 150mV
⎤
VIN(MIN) = 2 × ⎢
⎥+
⎣1 - 2 × (0.4μs × 1.0 × 300kHz) ⎦
150mV - 150mV + 90mV = 4.07V
Therefore, VIN must be greater than 4.1V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5.0V.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17082 evaluation kit specification for a layout example and follow these guidelines
for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitterfree operation.
• Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the
Quick-PWM controller. This includes the VCC, FB,
and GNDS bypass capacitors.
• Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
•
•
•
Keep the high-current, gate-driver traces (DL_,
DH_, LX_, and BST_) short and wide to minimize
trace resistance and inductance. This is essential
for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents.
CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvinsense connections to guarantee the current-sense
accuracy.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
Route high-speed switching nodes away from sensitive analog areas (CCI, FB, CSP_, CSN_, etc.).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN,
COUT, and D1 anode). If possible, make all these
connections on the top layer with wide, copperfilled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL_ gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST_ diodes
and capacitors, VDD bypass capacitor) together
near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 2. This diagram can be
viewed as having four separate ground planes:
input/output ground, where all the high-power components go; the power ground plane, where the
GND pin and VDD bypass capacitor go; the master’s analog ground plane where sensitive analog
components go, the master’s GND pin and VCC
bypass capacitor go; and the slave’s analog
ground plane where the slave’s GND pin and VCC
bypass capacitor go. The master’s GND plane must
meet the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the highpower output ground with a short metal trace from
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
5) Connect the output power planes (VCORE and system ground planes) directly to the output filter
capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
Package Information
Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
40 TQFN-EP
T4055-2
21-0140
______________________________________________________________________________________
47
MAX17021/MAX17082/MAX17482
•
MAX17021/MAX17082/MAX17482
Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/08
1
7/09
DESCRIPTION
Initial release
PAGES
CHANGED
—
Correction to non-OVP version, update IMON equations, fix errors in Figures 1,
2, and 4
1, 2, 4, 13, 14, 16,
19, 22, 25, 33–36,
39, 40, 46, 47
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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