19-3144; Rev 1; 3/04 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs The MAX1127 quad, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. The MAX1127 operates from a 1.7V to 1.9V single supply and consumes only 563mW while delivering a 69.6dB signal-to-noise ratio (SNR) at a 19.3MHz input frequency. In addition to low operating power, the MAX1127 features a 675µA power-down mode for idle periods. An internal 1.24V precision bandgap reference sets the ADC’s full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phaselocked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock. The MAX1127 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two’s complement or binary format. Refer to the MAX1126 data sheet for a pin-compatible 40Msps version of the MAX1127. Features ♦ Four ADC Channels with Serial LVDS/SLVS Outputs ♦ Excellent Dynamic Performance 69.6dB SNR at fIN = 19.3MHz 92dBc SFDR at fIN = 19.3MHz -87dB Channel Isolation ♦ Ultra-Low Power 135mW per Channel (Normal Operation) 1.2mW Total (Shutdown Mode) ♦ Accepts 20% to 80% Clock Duty Cycle ♦ ♦ ♦ ♦ Self-Aligning Data-Clock to Data-Output Interface Fully Differential Analog Inputs Wide ±1.4VP-P Differential Input Voltage Range Internal/External Reference Option ♦ Test Mode for Digital Signal Integrity ♦ LVDS Outputs Support Up to 30in FR-4 Backplane Connections ♦ Small, 68-Pin QFN with Exposed Paddle ♦ Evaluation Kit Available (MAX1127EVKIT) Ordering Information PART MAX1127EGK The MAX1127 is available in a small, 10mm x 10mm x 0.9mm, 68-pin QFN package with exposed paddle and is specified for the extended industrial (-40°C to +85°C) temperature range. Applications Ultrasound and Medical Imaging Positron Emission Tomography (PET) Imaging Multichannel Communication Systems Instrumentation TEMP RANGE PIN-PACKAGE 68 QFN 10mm x x 10mm x 0.9mm -40°C to +85°C GND INTREF REFIO GND LVDSTEST T/B AVDD AVDD AVDD AVDD AVDD PDALL PD3 PD2 PD1 PD0 OVDD Pin Configuration 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 GND 1 IN0P 2 50 OUT0N IN0N 3 49 OVDD GND 4 48 OUT1P IN1P 5 47 OUT1N IN1N 6 46 OVDD GND 7 45 CLKOUTP AVDD 8 AVDD 9 51 OUT0P EP 44 CLKOUTN MAX1127 43 OVDD AVDD 10 42 FRAMEP GND 11 41 FRAMEN IN2P 12 40 OVDD IN2N 13 39 OUT2P GND 14 38 OUT2N IN3P 15 37 OVDD IN3N 16 36 OUT3P GND 17 27 28 29 30 31 32 33 34 PLL0 PLL1 PLL2 PLL3 OVDD GND 26 SLVS/LVDS CVDD 25 DT AVDD 24 AVDD I.C. 23 AVDD 22 AVDD 21 GND 20 CLK 19 AVDD 35 OUT3N 18 QFN 10mm x 10mm x 0.9mm ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1127 General Description MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs ABSOLUTE MAXIMUM RATINGS T/B, LVDSTEST to GND ...........................-0.3V to (AVDD + 0.3V) REFIO, INTREF to GND............................-0.3V to (AVDD + 0.3V) I.C. to GND...............................................-0.3V to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 68-Pin QFN 10mm x 10mm x 0.9mm (derated 41.7mW/°C above +70°C)........................3333.3mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature Range (soldering, 10s)......................+300°C AVDD to GND.........................................................-0.3V to +2.0V CVDD to GND ........................................................-0.3V to +3.6V OVDD to GND ........................................................-0.3V to +2.0V IN_P, IN_N to GND...................................-0.3V to (AVDD + 0.3V) CLK to GND .............................................-0.3V to (CVDD + 0.3V) OUT_P, OUT_N, FRAME_, CLKOUT_ to GND................................-0.3V to (OVDD + 0.3V) DT, SLVS/LVDS to GND ...........................-0.3V to (AVDD + 0.3V) PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AVDD + 0.3V) PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AVDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1µF, fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL 12 Bits (Note 2) ±0.4 (Note 2) ±0.25 LSB LSB Offset Error Fixed external reference (Note 2) ±1 % FS Gain Error Fixed external reference (Note 2) ±1.5 % FS ANALOG INPUTS (IN_P, IN_N) Input Differential Range Common-Mode Voltage Range VID VCMO Differential Input Impedance RIN Differential Input Capacitance CIN Differential input 1.4 VP-P (Note 3) 0.75 V 2 kΩ 12.5 pF Switched capacitor load CONVERSION RATE Maximum Conversion Rate fSMAX Minimum Conversion Rate fSMIN 65 Data Latency MHz 16 MHz 6.5 Cycles DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) fIN = 5.3MHz at -0.5dBFS Signal-to-Noise Ratio (Note 2) SNR fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 69.7 66.6 fIN = 30.3MHz at -0.5dBFS Signal-to-Noise and Distortion (First Four Harmonics) (Note 2) Effective Number of Bits (Note 2) 2 fIN = 5.3MHz at -0.5dBFS SINAD ENOB fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 69.6 dB 69.4 69.6 66.5 69.5 fIN = 30.3MHz at -0.5dBFS 69.3 fIN = 5.3MHz at -0.5dBFS 11.4 fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 11.4 fIN = 30.3MHz at -0.5dBFS 11.3 _______________________________________________________________________________________ dB Bits Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs (AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1µF, fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Spurious-Free Dynamic Range (Note 2) SYMBOL CONDITIONS MIN fIN = 5.3MHz at -0.5dBFS SFDR fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C TYP MAX UNITS 93.3 77.5 fIN = 30.3MHz at -0.5dBFS dBc 92 88.9 fIN = 5.3MHz at -0.5dBFS -91 THD fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C -91 fIN = 30.3MHz at -0.5dBFS -88 Intermodulation Distortion IMD f1 = 12.348685MHz at -6.5dBFS, f2 = 13.650845MHz at -6.5dBFS (Note 2) 91.2 Third-Order Intermodulation IM3 (Note 2) 95.7 dBc Aperture Jitter tAJ (Note 2) <0.4 psRMS tAD (Note 2) Total Harmonic Distortion (Note 2) Aperture Delay Small-Signal Bandwidth SSBW Full-Power Bandwidth LSBW Output Noise Overdrive Recovery Time tOR Input at -20dBFS (Notes 2 and 4) -77.5 dBc dBc 1 ns 100 MHz Input at -0.5dBFS (Notes 2 and 4) 100 MHz INP = IN_N 0.35 LSBRMS 1 Clock cycles RS = 25Ω, CS = 50pF INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1µF) INTREF Internal Reference Mode Enable Voltage (Note 5) 0.1 INTREF Low-Leakage Current REFIO Output Voltage Reference Temperature Coefficient 200 VREFIO 1.18 TCREFIO 1.24 V µA 1.30 100 V ppm/°C EXTERNAL REFERENCE (INTREF = AVDD) INTREF External Reference Mode Enable Voltage (Note 5) AVDD 0.1V INTREF High-Leakage Current 200 REFIO Input Voltage Range REFIO Input Current V IREFIO µA 1.24 V <1 µA CLOCK INPUT (CLK) Input High Voltage VCLKH Input Low Voltage VCLKL Clock Duty Cycle Clock Duty-Cycle Tolerance 0.8 x CVDD V 0.2 x CVDD V 50 % ±30 % _______________________________________________________________________________________ 3 MAX1127 ELECTRICAL CHARACTERISTICS (continued) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) (AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1µF, fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Input Leakage DIIN Input Capacitance DCIN CONDITIONS MIN TYP MAX Input at GND 5 Input at AVDD 80 5 UNITS µA pF DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B) Input High Threshold VIH Input Low Threshold VIL 0.8 x AVDD V 0.2 x AVDD Input at GND, except PLL2 and PLL3 Input Leakage Input Capacitance DIIN V 5 Input at AVDD, except PLL2 and PLL3 80 PLL2 and PLL3 only 200 DCIN 5 µA pF LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0) Differential Output Voltage Output Common-Mode Voltage VOHDIFF RTERM = 100Ω 250 450 mV VOCM RTERM = 100Ω 1.125 1.375 V Rise Time (20% to 80%) tR RTERM = 100Ω, CLOAD = 5pF 150 ps Fall Time (80% to 20%) tF RTERM = 100Ω, CLOAD = 5pF 150 ps SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1 Differential Output Voltage Output Common-Mode Voltage VOHDIFF RTERM = 100Ω 240 mV VOCM RTERM = 100Ω 220 mV Rise Time (20% to 80%) tR RTERM = 100Ω, CLOAD = 5pF 120 ps Fall Time (80% to 20%) tF RTERM = 100Ω, CLOAD = 5pF 120 ps POWER-DOWN PD Fall to Output Enable tENABLE 132 µs PD Rise to Output Disable tDISABLE 10 ns POWER REQUIREMENTS AVDD Supply Voltage AVDD 1.7 1.8 1.9 V OVDD Supply Voltage OVDD 1.7 1.8 1.9 V CVDD Supply Voltage CVDD 1.7 1.8 3.6 V 4 _______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs (AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1µF, fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL AVDD Supply Current OVDD Supply Current IAVDD IOVDD CONDITIONS fIN = 19.3MHz at -0.5dBFS fIN = 19.3MHz at -0.5dBFS TYP MAX PDALL = 0, all channels active 257 295 PDALL = 0, all channels active, DT = 1 257 PDALL = 0, 1 channel active 82 PDALL = 0, PD[3:0] = 1111 23 PDALL = 1, global power down, PD[3:0] =1111, no clock input 300 PDALL = 0, all channels active 56 PDALL = 0, all channels active, DT = 1 72 PDALL = 0, 1 channel active 42 PDALL = 0, PD[3:0] = 1111 37 PDALL = 1, global powerdown, PD[3:0] =1111, no clock input 375 µA 0 mA CVDD Supply Current ICVDD CVDD is used only to bias ESD-protection diodes on CLK input, Figure 2 Power Dissipation PDISS fIN = 19.3MHz at -0.5dBFS MIN 563 UNITS mA µA 65 mA 648 mW TIMING CHARACTERISTICS (Note 6) (tSAMPLE / (tSAMPLE / tSAMPLE / 24) 24) 24 - 0.15 + 0.15 ns Figure 5 tSAMPLE / 12 ns tCL Figure 5 tSAMPLE / 12 ns FRAME Rise to CLKOUT Rise tCF Figure 4 (Note 7) (tSAMPLE / (tSAMPLE / tSAMPLE / 24) 24) 24 - 0.15 + 0.15 ns Sample CLK Rise to Frame Rise tSF Figure 4 (Notes 7 and 8) (tSAMPLE / (tSAMPLE / (tSAMPLE / 2) 2) 2) +0.9 +1.3 +1.7 ns Data Valid to CLKOUT Rise/Fall tOD fCLK = 65MHz, Figure 5 (Notes 6 and 7) CLKOUT Output Width High tCH CLKOUT Output Width Low _______________________________________________________________________________________ 5 MAX1127 ELECTRICAL CHARACTERISTICS (continued) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) (AV DD = 1.8V, OV DD = 1.8V, CV DD = 1.8V, GND = 0, external V REFIO = 1.24V, INTREF = AV DD, C REFIO to GND = 0.1µF, fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CHANNEL-TO-CHANNEL MATCHING Crosstalk (Note 2) -87 dB Gain Matching fIN = 30.3MHz (Note 2) ±0.1 dB Phase Matching fIN = 30.3.MHz (Note 2) ±1 Degrees Note 1: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization and not subject to production testing. Note 2: See definition in the Parameter Definitions section. Note 3: The MAX1127 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be overdriven to between 0.55V and 0.85V. Note 4: Limited by MAX1127EVKIT input circuitry. Note 5: Connect INTREF to GND directly to enable internal reference mode. Connect INTREF to AVDD directly to disable the internal bandgap reference and enable external reference mode. Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level. Note 7: Guaranteed by design and characterization. Not subject to production testing. Note 8: Sample CLK rise to FRAME rise timing is measured from 50% of sample clock input level to 50% of FRAME output level. 6 _______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs -70 -80 -90 -100 -110 -120 HD3 HD2 0 4 8 12 16 20 24 -40 -50 -60 -70 -80 -90 -100 -110 -120 32 28 HD3 HD2 0 4 8 12 FREQUENCY (MHz) -20 -30 -50 -60 -70 -40 0 -20 -50 -60 -70 -30 -40 -70 -90 -90 -90 -100 -100 -100 -110 -80 -110 12 16 20 24 28 32 -110 0 4 8 FREQUENCY (MHz) 12 16 20 24 28 32 0 FREQUENCY (MHz) TWO-TONE INTERMODULATION DISTORTION (32,768-POINT DATA RECORD) fIN(IN1) = 12.348685MHz fIN(IN2) = 13.650845MHz AIN1 = -6.5dBFS AIN2 = -6.5dBFS IMD = 91.2dBc IM3 = 95.7dBc -40 -50 -60 -70 -80 -90 -100 8 12 16 20 24 28 32 GAIN BANDWIDTH PLOT 1 SMALL-SIGNAL BANDWIDTH -20dBFS 0 -1 GAIN (dB) 0 -10 -20 -30 4 FREQUENCY (MHz) MAX1127 toc06 8 32 -60 -80 4 28 -50 -80 0 24 MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 3. fIN(IN1) = 5.3489349MHz fIN(IN3) = 30.2683055MHz -10 AMPLITUDE (dBFS) -40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -30 20 CROSSTALK (4096-POINT DATA RECORD) MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 2. fIN(IN1) = 5.3489349MHz fIN(IN2) = 30.2683055MHz -10 AMPLITUDE (dBFS) MEASURED ON CHANNEL 1, WITH INTERFERING SIGNAL ON CHANNEL 0. fIN(IN1) = 5.3489349MHz fIN(IN0) = 30.2683055MHz -20 0 MAX1127 toc03 0 CROSSTALK (4096-POINT DATA RECORD) MAX1127 toc04 CROSSTALK (4096-POINT DATA RECORD) -10 16 FREQUENCY (MHz) MAX1127 toc05 -50 -60 fCLK = 65.04448MHz fIN = 30.30301MHz AIN = -0.5dBFS SNR = 69.45dB SINAD = 69.4dB THD = -89.3dBc SFDR = 89.7dBc MAX1127 toc07 AMPLITUDE (dBFS) -40 0 -10 -20 -30 AMPLITUDE (dBFS) fCLK = 65.04448MHz fIN = 5.301935MHz AIN = -0.5dBFS SNR = 69.5dB SINAD = 69.47dB THD = -90.94dBc SFDR = 93.27dBc -10 -20 -30 MAX1127 toc01 0 FFT PLOT (32,768-POINT DATA RECORD) MAX1127toc02 FFT PLOT (32,768-POINT DATA RECORD) FULL-POWER BANDWIDTH -0.5dBFS -2 -3 -4 -5 LIMITED BY MAX1127EVKIT INPUT CIRCUITRY -6 -110 -120 -7 0 4 8 12 16 20 FREQUENCY (MHz) 24 28 32 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1127 Typical Operating Characteristics (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY 71 70 71 70 69 SINAD (dB) 68 67 66 68 67 66 65 65 64 64 63 63 62 62 0 20 40 60 80 100 120 0 20 40 60 80 100 fIN (MHz) fIN (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 100 MAX1127 toc10 -55 -60 -65 95 90 85 SFDR (dBc) -70 120 MAX1127 toc11 SNR (dB) 69 -75 -80 80 75 -85 70 -90 65 -95 60 -100 55 0 20 40 60 fIN (MHz) 8 MAX1127 toc09 72 MAX1127 toc08 72 THD (dBc) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs 80 100 120 0 20 40 60 80 fIN (MHz) _______________________________________________________________________________________ 100 120 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER SIGNAL TO NOISE + DISTORTION vs. ANALOG INPUT POWER fIN = 5.301935MHz 67 62 57 57 SINAD (dB) 62 52 52 47 47 42 42 37 37 32 32 -25 -20 -15 -10 -5 0 -25 -20 -15 -10 -5 ANALOG INPUT POWER (dBFS) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER fIN = 5.301935MHz -65 0 100 MAX1127 toc14 -55 -60 -30 ANALOG INPUT POWER (dBFS) MAX1127 toc15 -30 fIN = 5.301935MHz 95 90 85 SFDR (dBc) -70 THD (dBc) MAX1127 toc13 fIN = 5.301935MHz 67 SNR (dB) 72 MAX1127 toc12 72 -75 -80 80 75 -85 70 -90 65 -95 60 -100 55 -30 -25 -20 -15 -10 ANALOG INPUT POWER (dBFS) -5 0 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS) _______________________________________________________________________________________ 9 MAX1127 Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE SIGNAL-TO-NOISE + DISTORTION vs. SAMPLING RATE 70 70 69 SINAD (dB) 68 67 66 68 67 66 65 65 64 64 63 63 62 62 20 25 30 35 40 45 50 55 60 65 20 25 30 35 fCLK (MHz) 40 45 50 55 60 65 fCLK (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE TOTAL HARMONIC DISTORTION vs. SAMPLING RATE 105 MAX1127 toc18 -75 fIN = 5.301935MHz -80 MAX1127 toc19 SNR (dB) fIN = 5.301935MHz 71 69 fIN = 5.301935MHz 100 95 SFDR (dBc) -85 -90 90 -95 85 -100 80 75 -105 20 25 30 35 40 45 fCLK (MHz) 10 MAX1127 toc17 fIN = 5.301935MHz 71 72 MAX1127 toc16 72 THD (dBc) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs 50 55 60 65 20 25 30 35 40 45 50 55 fCLK (MHz) ______________________________________________________________________________________ 60 65 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE 70 70 69 SINAD (dB) 68 67 66 68 67 66 65 65 64 64 63 63 62 62 30 40 50 60 70 30 CLOCK DUTY CYCLE (%) -80 60 70 SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE 100 MAX1127 toc22 fIN = 5.301935MHz 50 CLOCK DUTY CYCLE (%) TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE -75 40 MAX1127 toc23 SNR (dB) fIN = 5.301935MHz 71 69 fIN = 5.301935MHz 95 -85 90 SFDR (dBc) THD (dBc) MAX1127 toc21 fIN = 5.301935MHz 71 72 MAX1127 toc20 72 SIGNAL-TO-NOISE + DISTORTION vs. CLOCK DUTY CYCLE -90 85 -95 80 -100 75 -105 70 30 40 50 60 CLOCK DUTY CYCLE (%) 70 30 40 50 60 70 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 11 MAX1127 Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. TEMPERATURE 68 66 fCLK = 65.04065041MHz fIN = 19.29703379MHz 4096-POINT DATA RECORD 70 SINAD (dB) 64 68 66 64 62 62 -40 -15 10 35 60 85 -40 -15 TEMPERATURE (°C) TOTAL HARMONIC DISTORTION vs. TEMPERATURE fCLK = 65.04065041MHz fIN = 19.29703379MHz 4096-POINT DATA RECORD 60 100 fCLK = 65.04065041MHz fIN = 19.29703379MHz 4096-POINT DATA RECORD 95 85 90 SFDR (dBc) -85 -90 85 -95 80 -100 75 -105 70 -40 -15 10 35 TEMPERATURE (°C) 12 35 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE MAX1127 toc26 -75 -80 10 TEMPERATURE (°C) MAX1127 toc27 SNR (dB) 72 MAX1127 toc25 fCLK = 65.04065041MHz fIN = 19.29703379MHz 4096-POINT DATA RECORD 70 SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE MAX1127 toc24 72 THD (dBc) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs 60 85 -40 -15 10 35 TEMPERATURE (°C) ______________________________________________________________________________________ 60 85 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs ANALOG SUPPLY CURRENT vs. SAMPLING RATE DIGITAL SUPPLY CURRENT vs. SAMPLING RATE 260 MAX1127 toc29 70 MAX1127 toc28 270 60 IOVDD (mA) IAVDD (mA) 50 250 240 40 30 20 230 10 220 0 25 30 35 40 45 50 55 65 20 25 30 35 40 45 50 fCLK (MHz) fCLK (MHz) OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE 0.04 0.03 60 0.8 0.6 GAIN ERROR (%FS) 0.05 55 1.0 MAX1127 toc30 0.06 OFFSET ERROR (%FS) 60 65 MAX1127 toc31 20 0.4 0.2 0 -.0.2 -0.4 -0.6 0.02 -0.8 -1.0 0.01 -15 10 35 -40 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.5 MAX1127 toc32 0.5 0.4 0.3 0.4 0.3 0.2 0.2 0.1 0.1 DNL (LSB) INL (LSB) 60 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 85 MAX1127 toc33 -40 -0.5 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE ______________________________________________________________________________________ 13 MAX1127 Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS, fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.) 1.40 MAX1127 toc35 1.26 MAX1127 toc34 1.239 INTERNAL REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 1.35 VREFIO (V) VREFIO (V) 1.237 NEGATIVE CURRENT FLOWS INTO REFIO 1.30 1.25 1.238 MAX1127 toc36 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE VREFIO (V) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs 1.24 1.25 1.20 1.15 1.23 1.236 1.10 1.05 AVDD = OVDD AVDD = OVDD 1.00 1.22 1.235 1.7 1.8 1.9 2.0 SUPPLY VOLTAGE (V) 2.1 -40 -15 10 35 60 85 TEMPERATURE (°C) -400 -300 -200 -100 0 100 200 300 400 IREFIO (µA) Pin Description PIN NAME 1, 4, 7, 11, 14, 17, 22, 24, 65, 68 GND Ground. Connect all GND pins to the same potential. 2 IN0P Channel 0 Positive Analog Input 3 IN0N Channel 0 Negative Analog Input 5 IN1P Channel 1 Positive Analog Input 6 IN1N Channel 1 Negative Analog Input AVDD Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass each AVDD to GND with a 0.1µF capacitor as close to the device as possible. Bypass the AVDD power plane to the GND ground plane with a bulk ≥2.2µF capacitor as close to the device as possible. Connect all AVDD pins to the same potential. 12 IN2P Channel 2 Positive Analog Input 13 IN2N Channel 2 Negative Analog Input 15 IN3P Channel 3 Positive Analog Input 16 IN3N 19 I.C. 21 CVDD 23 CLK 8, 9, 10, 18, 20, 25, 26, 27, 58–62 28 14 DT FUNCTION Channel 3 Negative Analog Input Internally Connected. Do not connect. Clock Power Input. Connect CVDD to a 1.7V to 3.6V supply. Bypass CVDD to GND with a 0.1µF capacitor in parallel with a ≥2.2µF capacitor. Install the bypass capacitors as close to the device as possible. Single-Ended CMOS Clock Input Double Termination Select Input. Drive DT high to select the internal 100Ω termination between the differential output pairs. Drive DT low to select no internal output termination. ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs PIN NAME FUNCTION 29 SLVS/LVDS 30 PLL0 PLL Control Input 0. PLL0 is reserved for factory testing only and must always be connected to GND. 31 PLL1 PLL Control Input 1. PLL1 is reserved for factory testing only and must always be connected to GND. 32 PLL2 PLL Control Input 2. See Table 1 for details. 33 PLL3 PLL Control Input 3. See Table 1 for details. 34, 37, 40, 43, 46, 49, 52 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass each OVDD to GND with a 0.1µF capacitor as close to the device as possible. Bypass the OVDD power plane to the GND ground plane with a bulk ≥2.2µF capacitor as close to the device as possible. Connect all OVDD pins to the same potential. 35 OUT3N Channel 3 Negative LVDS/SLVS Output 36 OUT3P Channel 3 Positive LVDS/SLVS Output 38 OUT2N Channel 2 Negative LVDS/SLVS Output 39 OUT2P Differential Output Signal Format Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive SLVS/LVDS low to select LVDS outputs. Channel 2 Positive LVDS/SLVS Output 41 FRAMEN Negative Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. 42 FRAMEP Positive Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to a valid D0 in the output data stream. 44 CLKOUTN Negative LVDS/SLVS Serial Clock Output 45 CLKOUTP Positive LVDS/SLVS Serial Clock Output 47 OUT1N Channel 1 Negative LVDS/SLVS Output 48 OUT1P Channel 1 Positive LVDS/SLVS Output 50 OUT0N Channel 0 Negative LVDS/SLVS Output 51 OUT0P Channel 0 Positive LVDS/SLVS Output 53 PD0 Channel 0 Power-Down Input. Drive PD0 high to power-down channel 0. Drive PD0 low for normal operation. 54 PD1 Channel 1 Power-Down Input. Drive PD1 high to power-down channel 1. Drive PD1 low for normal operation. 55 PD2 Channel 2 Power-Down Input. Drive PD2 high to power-down channel 2. Drive PD2 low for normal operation. 56 PD3 Channel 3 Power-Down Input. Drive PD3 high to power-down channel 3. Drive PD3 low for normal operation. 57 PDALL Global Power-Down Input. Drive PDALL high to power-down all channels and reference. Drive PDALL low for normal operation. 63 T/B Output Format Select Input. Drive T/B high to select binary output format. Drive T/B low to select two’s complement output format. ______________________________________________________________________________________ 15 MAX1127 Pin Description (continued) MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Pin Description (continued) PIN NAME FUNCTION 64 LVDSTEST 66 REFIO Reference Input/Output. For internal reference operation (INTREF = GND), the reference output voltage is 1.24V. For external reference operation (INTREF = AVDD), apply a stable reference voltage at REFIO. Bypass to GND with a 0.1µF capacitor. 67 INTREF Internal/External Reference Mode Select Input. For internal reference mode, connect INTREF directly to GND. For external reference mode, connect INTREF directly to AVDD. — EP LVDS Test Pattern Enable Input. Drive LVDSTEST high to enable the output test pattern (000010111101 MSB→LSB). As with the analog conversion results, the test pattern data is output LSB first. Drive LVDSTEST low for normal operation. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified performance. Functional Diagram PDALL PD0 REFIO INTREF REFERENCE SYSTEM PD1 PD2 PD3 POWER CONTROL T/H 12-BIT PIPELINE ADC T/H 12-BIT PIPELINE ADC IN0P IN0N AVDD OVDD DT SLVS/LVDS OUTPUT CONTROL MAX1127 LVDSTEST T/B OUT0P 12:1 SERIALIZER OUT0N OUT1P IN1P IN1N IN2P T/H IN2N IN3P T/H IN3N OUT1N 12:1 SERIALIZER OUT2P 12-BIT PIPELINE ADC 12:1 SERIALIZER 12-BIT PIPELINE ADC 12:1 SERIALIZER LVDS/SLVS OUTPUT DRIVERS OUT2N OUT3P OUT3N FRAMEP FRAMEN CLKOUTP CLK 16 CLOCK CIRCUITRY PLL 6x CVDD PLL0 PLL1 PLL2 PLL3 CLKOUTN GND ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs The MAX1127 ADC features fully differential inputs, a pipelined architecture, and digital error correction for high-speed signal conversion. The ADC pipeline architecture moves the samples taken at the inputs through the pipeline stages every half clock cycle. The converted digital results are serialized and sent through the LVDS/SLVS output drivers. The total latency from input to output is 6.5 input clock cycles. The MAX1127 offers four separate fully differential channels with synchronized inputs and outputs. Configure the outputs for binary or two’s complement with the T/B digital input. Power-down each channel individually or globally to minimize power consumption. Input Circuit Figure 1 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transcon- ductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. Analog inputs IN_P to IN_N are driven differentially. For differential inputs, balance the input impedance of IN_P and IN_N for optimum performance. The MAX1127 analog inputs are self-biased at a common-mode voltage of 0.6V (typ) and allow a differential input voltage swing of 1.4VP-P. The common-mode voltage can be overdriven to between 0.55V to 0.85V. Drive the analog inputs of the MAX1127 in AC-coupled configuration to achieve best dynamic performance. See the Using Transformer Coupling section for a detailed discussion of this configuration. SWITCHES SHOWN IN TRACK MODE INTERNAL COMMON-MODE BIAS* AVDD INTERNALLY GENERATED COMMON-MODE LEVEL* INTERNAL BIAS* S5a S2a MAX1127 C1a S3a C2a S4a IN_P OUT S4c S1 OTA OUT IN_N S4b C2b C1b S3b GND S2b INTERNAL COMMON-MODE BIAS* INTERNAL BIAS* S5b INTERNALLY GENERATED COMMON-MODE LEVEL* *NOT EXTERNALLY ACCESSIBLE Figure 1. Internal Input Circuitry ______________________________________________________________________________________ 17 MAX1127 Detailed Description MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Reference Configurations (REFIO and INTREF) The MAX1127 provides an internal 1.24V bandgap reference or can be driven with an external reference voltage. The MAX1127 full-scale analog differential input range is ±FSR. Full-scale range (FSR) is given by the following equation: V FSR = 700mV × REFIO 1.24V where VREFIO is the voltage at REFIO, generated internally or externally. For a VREFIO = 1.24V, the full-scale input range is ±700mV (1.4VP-P). Internal Reference Mode Connect INTREF to GND to use the internal bandgap reference directly. The internal bandgap reference generates REFIO to be 1.24V with a 100ppm/°C temperature coefficient in internal reference mode. Connect an external ≥0.1µF bypass capacitor from REFIO to GND for stability. REFIO sources up to 200µA and sinks up to 200µA for external circuits, and REFIO has a load regulation of 83mV/mA. The global power-down input (PDALL) enables and disables the reference circuit. REFIO has >1MΩ resistance to GND when the MAX1127 is in power-down mode. The internal reference circuit requires 132µs to power-up and settle when power is applied to the MAX1127 or when PDALL transitions from high to low. External Reference Mode The external reference mode allows for more control over the MAX1127 reference voltage and allows multiple converters to use a common reference. Connect INTREF to AVDD to disable the internal reference and enter external reference mode. Apply a stable 1.24V source at REFIO. Bypass REFIO to GND with a 0.1µF capacitor. The REFIO input impedance is >1MΩ. Clock Input (CLK) The MAX1127 accepts a CMOS-compatible clock signal with a wide 20% to 80% input-clock duty cycle. Drive CLK with an external single-ended clock signal. Figure 2 shows the simplified clock input diagram. Low clock jitter is required for the specified SNR performance of the MAX1127. Analog input sampling occurs on the rising edge of CLK, requiring this edge to provide the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 × log 2 × π × fIN × t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 69.4dB of SNR with an input frequency of 30.3MHz, the system must have less than 1.8ps of clock jitter. In actuality, there are other noise sources, such as thermal noise and quantization noise, that contribute to the system noise requiring the clock jitter to be less than 0.5ps to obtain the specified 69.4dB of SNR at 30.3MHz. The MAX1127 features a PLL that generates an output clock signal with six times the frequency of the input clock. The output clock signal is used to clock data out of the MAX1127 (see the System Timing Requirements section). Set the PLL2 and PLL3 bits according to the input clock range provided in Table 1. PLL0 and PLL1 are reserved for factory testing and must always be connected to GND. Table 1. PLL2 and PLL3 Configuration AVDD MAX1127 CVDD CLK GND DUTY-CYCLE EQUALIZER CLOCK INPUT RANGE (MHz) PLL2 PLL3 MIN MAX 0 0 48.750 65.000 0 1 32.500 48.750 1 0 24.375 32.500 1 1 16.000 24.375 *PLL0 and PLL11 are reserved for factory testing and must always be connected to GND. Figure 2. Clock Input Circuitry 18 ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs MAX1127 N+2 (VIN_P VIN_N) N+6 N+3 N N+8 N+5 N+1 N+9 N+7 N+4 tSAMPLE CLK 6.5 CLOCK-CYCLE DATA LATENCY (VFRAMEP VFRAMEN)* (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) OUTPUT DATA FOR SAMPLE N-6 OUTPUT DATA FOR SAMPLE N *DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY. Figure 3. Global Timing Diagram N+2 N (VIN_P - VIN_N) N+1 tSF tSAMPLE CLK (VFRAMEP VFRAMEN)* tCF (VCLKOUTP VCLKOUTN) (VOUT_P VOUT_N) D5N-7 D6N-7 D7N-7 D8N-7 D9N-7 D10N-7 D11N-7 D0N-6 D1N-6 D2N-6 D3N-6 D4N-6 D5N-6 D6N-6 D7N-6 D8N-6 D9N-6 D10N-6 D11N-6 D0N-5 D1N-5 D2N-5 D3N-5 D4N-5 D5N-5 D6N-5 *DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY. Figure 4. Detailed Two-Conversion Timing Diagram System Timing Requirements Figure 3 shows the relationship between the analog inputs, input clock, frame alignment output, serial clock output, and serial data output. The differential analog input (IN_P and IN_N) is sampled on the rising edge of the CLK signal and the resulting data appears at the digital outputs 6.5 clock cycles later. Figure 4 provides a detailed, two-conversion timing diagram of the relationship between the inputs and the outputs. Clock Output (CLKOUTP, CLKOUTN) The MAX1127 provides a differential clock output that consists of CLKOUTP and CLKOUTN. As shown in Figure 4, the serial output data is clocked out of the MAX1127 on both edges of the clock output. The frequency of the output clock is 6 times the frequency of CLK. ______________________________________________________________________________________ 19 MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Frame Alignment Output (FRAMEP, FRAMEN) The MAX1127 provides a differential frame alignment signal that consists of FRAMEP and FRAMEN. As shown in Figure 4, the rising edge of the frame alignment signal corresponds to the first bit (D0) of the 12-bit serial data stream. The frequency of the frame alignment signal is identical to the frequency of the sample clock. Serial Output Data (OUT_P, OUT_N) The MAX1127 provides its conversion results through individual differential outputs consisting of OUT_P and OUT_N. The results are valid 6.5 input clock cycles after the sample is taken. As shown in Figure 3, the output data is clocked out on both edges of the output clock, LSB (D0) first. Figure 5 provides the detailed serial output timing diagram. Output Data Format (T/B), Transfer Functions The MAX1127 output data format is either offset binary or two’s complement, depending on the logic input T/B. With T/B low, the output data format is two’s complement. With T/B high, the output data format is offset binary. The following equations, Table 2, Figure 6, and Figure 7 define the relationship between the digital output and the analog input. For two’s complement (T/B = 0): VIN _ P − VIN _ N = FSR × 2 × CODE10 4096 (VOUT_P VOUT_N) tOD D0 D1 tOD D2 D3 Figure 5. Serialized Output Detailed Timing Diagram where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. FSR is the full-scale range as shown in Figures 6 and 7. Keep the capacitive load on the MAX1127 digital outputs as low as possible. LVDS and SLVS Signals (SLVS/LVDS) Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high for scalable low-voltage signaling (SLVS) levels at the MAX1127 outputs (OUT_P, OUT_N, CLKOUT_P, CLKOUT_N, FRAMEP_, and FRAMEN_). See the Electrical Characteristics table for LVDS and SLVS output voltage levels. LVDS Test Pattern (LVDSTEST) Drive LVDSTEST high to enable the output test pattern on all LVDS or SLVS output channels. The output test pattern is 0000 1011 1101 MSB→LSB. As with the analog conversion results, the test pattern data is output LSB first. Drive LVDSTEST low for normal operation (test pattern disabled). and for offset binary (T/B = 1): VIN _ P − VIN _ N = FSR × 2 × tCL tCH (VCLKOUTP VCLKOUTN) CODE10 − 2048 4096 Table 2. Output Code Table (VREFIO = 1.24V) TWO’S COMPLEMENT DIGITAL OUTPUT CODE (T/B = 0) OFFSET BINARY DIGITAL OUTPUT CODE (T/B = 1) HEXADECIMAL EQUIVALENT OF D11 D0 DECIMAL EQUIVALENT OF D11 D0 VIN_P - VIN_P (mV) (VREFIO = 1.24V) 1111 1111 1111 0xFFF +4095 +699.66 1111 1111 1110 0xFFE +4094 +699.32 +1 1000 0000 0001 0x801 +2049 +0.34 0 1000 0000 0000 0x800 +2048 0 0xFFF -1 0111 1111 1111 0x7FF +2047 -0.34 1000 0000 0001 0X801 -2047 0000 0000 0001 0x001 +1 -699.66 1000 0000 0000 0x800 -2048 0000 0000 0000 0x000 0 -700.00 BINARY D11 D0 HEXADECIMAL EQUIVALENT OF D11 D0 DECIMAL EQUIVALENT OF D11 D0 BINARY D11 D0 0111 1111 1111 0x7FF +2047 0111 1111 1110 0x7FE +2046 0000 0000 0001 0x001 0000 0000 0000 0x000 1111 1111 1111 20 ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs FSR = 700mV x VREFIO 1.24V FSR 0x7FF 0x7FE 0x7FD FSR OFFSET BINARY OUTPUT CODE (LSB) TWO'S COMPLEMENT OUTPUT CODE (LSB) FSR 1 LSB = 2 x FSR 4096 0x001 0x000 0xFFF 0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 FSR = 700mV x VREFIO 1.24V FSR 0xFFF 0xFFE 0xFFD 0x801 0x800 0x7FF 0x003 0x002 0x800 0x000 +2045 +2047 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Bipolar Transfer Function with Two’s Complement Output Code (T/B = 0) MAX1127 1 LSB = 2 x FSR 4096 Figure 7. Bipolar Transfer Function with Offset Binary Output Code (T/B = 1) Double Termination (DT) As shown in Figure 8, the MAX1127 offers an optional, internal 100Ω termination between the differential output pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN, FRAMEP and FRAMEN). In addition to the termination at the end of the line, a second termination directly at the outputs helps eliminate unwanted reflections down the line. This feature is useful in applications where trace lengths are long (>5in) or with mismatched impedance. Drive DT high to select double termination, or drive DT low to disconnect the internal termination resistor (single termination). Selecting double termination increases the OV DD supply current (see the Electrical Characteristics table). DT OUT_P/ CLKOUTP/ FRAMEP 100Ω 100Ω Power-Down Modes The MAX1127 offers two types of power-down inputs, PD0–PD3 and PDALL. The power-down modes allow the MAX1127 to use power efficiently by transitioning to a low-power state when conversions are not required. Independent Channel Power-Down (PD0–PD3) PD0–PD3 control the power-down mode of each channel independently. Drive a power-down input high to power down its corresponding input channel. For example, to power down channel 1, drive PD1 high. Drive a power-down input low to place the corresponding input channel in normal operation. The differential output impedance of a powered-down output channel is approximately 378Ω, when DT is low. The output impedance of OUT_P, with respect to OUT_N, is 100Ω when Z0 = 50Ω MAX1127 OUT_N/ CLKOUTN/ FRAMEN Z0 = 50Ω SWITCHES ARE CLOSED WHEN DT IS HIGH. SWITCHES ARE OPEN WHEN DT IS LOW. Figure 8. Double Termination DT is high. See the Electrical Characteristics table for typical supply currents with powered-down channels. The state of the internal reference is independent of the PD0–PD3 inputs. To power down the internal reference circuitry, drive PDALL high (see the Global PowerDown (PDALL) section). ______________________________________________________________________________________ 21 MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Global Power-Down (PDALL) PDALL controls the power-down mode of all channels and the internal reference circuitry. Drive PDALL high to enable global power-down. In global power-down mode, the output impedance of all the LVDS/SLVS outputs is approximately 378Ω, if DT is low. The output impedance of the differential LVDS/SLVS outputs is 100Ω when DT is high. See the Electrical Characteristics table for typical supply currents with global power-down. The following list shows the state of the analog inputs and digital outputs in global powerdown mode: • IN_P, IN_N analog inputs are disconnected from the internal input amplifier. • REFIO has > 1MΩ resistance to GND. • OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN have approximately 378Ω between the output pairs when DT is low. When DT is high, the differential output pairs have 100Ω between each pair. When operating from the internal reference, the wakeup time from global power-down is typically 132µs. When using an external reference, the wake-up time is dependent on the external reference drivers. Applications Information Using Transformer Coupling An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1127 for optimum performance. The MAX1127 input common-mode voltage is internally biased to 0.6V (typ) with fCLK = 65MHz. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. Grounding, Bypassing, and Board Layout The MAX1127 requires high-speed board layout design techniques. Refer to the MAX1127 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥2.2µF ceramic capacitor. Bypass OVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥2.2µF ceramic capacitor. Bypass CVDD to GND with a 0.1µF ceramic capacitor in parallel with a ≥2.2µF ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. Connect MAX1127 ground pins and the exposed backside paddle to the same ground plane. The MAX1127 relies on the exposed backside paddle connection for a lowinductance ground connection. Isolate the ground plane from any noisy digital system ground planes. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90° turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1127 EV kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1127, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) 10Ω 0.1µF IN_P 1 VIN 6 39pF T1 N.C. 2 5 MAX1127 0.1µF 3 4 MINICIRCUITS ADT1-1WT Offset Error 10Ω IN_N 39pF Figure 9. Transformer-Coupled Input Drive 22 Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1127, DNL deviations are measured at every step and the worst-case deviation is reported in the Electrical Characteristics table. Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. For the MAX1127, the ideal midscale digital output transition occurs when there is -1/2 LSB across the analog inputs (Figures 6 and 7). ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs CLK tAD Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1127, the gain error is the difference of the measured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. For the bipolar devices (MAX1127), the full-scale transition point is from 0x7FE to 0x7FF for two’s complement output format (0xFFE to 0xFFF for offset binary) and the zero-scale transition point is from 0x800 to 0x801 for two’s complement (0x000 to 0x001 for offset binary). MAX1127 Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. ANALOG INPUT tAJ SAMPLED DATA T/H HOLD TRACK HOLD Figure 10. Aperture Jitter/Delay Specifications Crosstalk Crosstalk indicates how well each analog input is isolated from the others. For the MAX1127, a 5.3MHz, -0.5dBFS analog signal is applied to one channel while a 30.3MHz, -0.5dBFS analog signal is applied to all other channels. An FFT is taken on the channel with the 5.3MHz analog signal. From this FFT, the crosstalk is measured as the difference in the 5.3MHz and 30.3MHz amplitudes. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. See Figure 10. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay. See Figure 10. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB x N x 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. For the MAX1127, SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD − 1.76 ENOB = 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 × log V1 ______________________________________________________________________________________ 23 MAX1127 Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Spurious-Free Dynamic Range (SFDR) Small-Signal Bandwidth SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). A small -20dBFS analog input signal is applied to an ADC so the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Intermodulation Distortion (IMD) Full-Power Bandwidth IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6.5dBFS. The intermodulation products are as follows: • 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. • 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 • 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 • 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1 Third-Order Intermodulation (IM3) IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -6.5dBFS. The 3rd-order intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1. 24 Gain Matching Gain matching is a figure of merit that indicates how well the gain of all four ADC channels is matched to each other. For the MAX1127, gain matching is measured by applying the same 30.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 65MHz and the maximum deviation in amplitude is reported in dB as gain matching in the Electrical Characteristics table. Phase Matching Phase matching is a figure of merit that indicates how well the phase of all four ADC channels is matched to each other. For the MAX1127, phase matching is measured by applying the same 30.3MHz, -0.5dBFS analog signal to all analog input channels. These analog inputs are sampled at 65MHz and the maximum deviation in phase is reported in degrees as phase matching in the Electrical Characteristics table. ______________________________________________________________________________________ Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs 68L QFN.EPS PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Note: For the MAX1127 Exposed Pad Variation, the package code is G6800-4. PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1127 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)