19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels. The MAX9210/MAX9214/MAX9220/MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. Each deserializer decodes data transmitted by one of MAX9209/MAX9213 serializers. The MAX9210/MAX9214 have rising-edge output strobes, and when DC balance is not programmed, are compatible with non-DC-balanced 21-bit deserializers such as the DS90CR216A and DS90CR218A. The MAX9220/MAX9222 have falling-edge output strobes. Two frequency versions and two DC-balance default conditions are available for maximum replacement flexibility and compatibility with popular non-DC-balanced deserializers. The transition time of the single-ended outputs is increased on the low-frequency version parts (MAX9210/MAX9220) for reduced EMI. The LVDS inputs meet IEC 61000-4-2 Level 4 ESD specification, ±15kV for Air Discharge and ±8kV Contact Discharge. The MAX9210/MAX9214/MAX9220/MAX9222 are available in a TSSOP package, and operate over the -40°C to +85°C temperature range. Features ♦ Programmable DC Balance or Non-DC Balance ♦ DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range ♦ As Low as 8MHz Operation (MAX9210/MAX9220) ♦ Falling-Edge Output Strobe (MAX9220/MAX9222) ♦ Slower Output Transitions for Reduced EMI (MAX9210/MAX9220) ♦ High-Impedance Outputs when PWRDWN is Low Allow Output Busing ♦ Pin Compatible with DS90CR216A/DS90CR218A (MAX9210/MAX9214) ♦ Fail-Safe Inputs in Non-DC-Balanced Mode ♦ 5V Tolerant PWRDWN Input ♦ PLL Requires No External Components ♦ Up to 1.785Gbps Throughput ♦ Separate Output Supply Pins Allow Interface to 1.8V, 2.5V, 3.3V, and 5V Logic ♦ LVDS Inputs Meet IEC 61000-4-2 Level and ISO 10605 ESD Requirements ♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS Standard ♦ Low-Profile 48-Lead TSSOP Package ♦ +3.3V Main Power Supply ♦ -40°C to +85°C Operating Temperature Range Applications Automotive Navigation Systems Ordering Information PART TEMP RANGE PIN-PACKAGE Automotive DVD Entertainment Systems MAX9210EUM -40°C to +85°C 48 TSSOP Digital Copiers MAX9214EUM -40°C to +85°C 48 TSSOP Laser Printers MAX9220EUM -40°C to +85°C 48 TSSOP MAX9222EUM -40°C to +85°C 48 TSSOP Functional Diagram and Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9210/MAX9214/MAX9220/MAX9222 General Description MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.5V to +4.0V VCCO to GND.........................................................-0.5V to +6.0V RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND .................................................-0.5V to +6.0V DCB/NC to GND.........................................-0.5V to (VCC + 0.5V) RxOUT_, RxCLK OUT to GND .................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND ..........................................................±5kV IEC 61000-4-2 (RD = 330Ω, CS = 150pF) Contact Discharge (RxIN_, RxCLK IN_) to GND ...........±8kV Air Discharge (RxIN_, RxCLK IN_) to GND ..................±15kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (RxIN_, RxCLK IN_) to GND ...........±8kV Air Discharge (RxIN_, RxCLK IN_) to GND ..................±25kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID| = 0.2V, VCM = 1.25V, TA = +25°C). (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (PWRDWN, DCB/NC) High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Current IIN Input Clamp Voltage VCL PWRDWN 2.0 5.5 DCB/NC 2.0 VCC + 0.3 -0.3 +0.8 V -20 +20 µA -1.5 V VIN = high or low, PWRDWN = high or low ICL = -18mA V SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT) VCCO 0.1 IOH = -100µA High-Level Output Voltage RxCLK OUT VCCO 0.25 RxOUT_ VCCO 0.40 MAX9210/ MAX9220 VOH IOH = -2mA V MAX9214/MAX9222 VCCO 0.25 IOL = 100µA Low-Level Output Voltage VOL IOL = 2mA 0.1 MAX9210/ MAX9220 RxCLK OUT 0.2 RxOUT_ 0.26 V MAX9214/MAX9222 High-Impedance Output Current 2 IOZ PWRDWN = low, VOUT_ = -0.3V to VCCO + 0.3V 0.2 -20 _______________________________________________________________________________________ 20 µA Programmable DC-Balance 21-Bit Deserializers (VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |VID| = 0.05V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID| = 0.2V, VCM = 1.25V, TA = +25°C). (Notes 1, 2) PARAMETER Output Short-Circuit Current (Note: Short one output at a time.) SYMBOL IOS CONDITIONS MIN TYP MAX RxCLK OUT VCCO = 3.0V MAX9210/ MAX9220 to 3.6V, RxOUT_ VOUT = 0 MAX9214/MAX9222 -10 -40 -5 -20 -10 -40 RxCLK OUT VCCO = 4.5V MAX9210/ MAX9220 to 5.5V, RxOUT_ VOUT = 0 MAX9214/MAX9222 -28 -75 -14 -37 -28 -75 UNITS mA LVDS INPUTS Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current IIN+, IIN- Power-Off Input Current IINO+, IINO- Input Resistor 1 RIN1 Input Resistor 2 RIN2 50 -50 mV mV PWRDWN = high or low -25 +25 µA VCC = VCCO = 0 or open, DCB/NC, PWRDWN = 0 or open -25 +25 µA 42 78 kΩ 246 410 kΩ PWRDWN = high or low, Figure 1 VCC = VCCO = 0 or open, Figure 1 PWRDWN = high or low, Figure 1 VCC = VCCO = 0 or open, Figure 1 POWER SUPPLY CL = 8pF, worstcase pattern, DC- balanced mode; VCC = VCCO = 3.0V to 3.6V, Figure 2 Worst-Case Supply Current ICCW CL = 8pF, worst case pattern, non-DC-balanced mode; VCC = VCCO = 3.0V to 3.6V, Figure 2 Power-Down Supply Current ICCZ PWRDWN = low MAX9210/ MAX9220 MAX9214/ MAX9222 MAX9210/ MAX9220 MAX9214/ MAX9222 8MHz 32 16MHz 46 42 57 34MHz 81 98 16MHz 52 63 34MHz 86 106 66MHz 152 177 10MHz 33 42 20MHz 46 58 33MHz 67 80 40MHz 78 94 20MHz 53 64 33MHz 72 85 40MHz 81 99 66MHz 127 149 85MHz 159 186 50 mA µA _______________________________________________________________________________________ 3 MAX9210/MAX9214/MAX9220/MAX9222 DC ELECTRICAL CHARACTERISTICS (continued) MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers AC ELECTRICAL CHARACTERISTICS (VCC = VCCO = +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, DCB/NC = high or low, differential input voltage |VID| = 0.1V to 1.2V, Input Common Mode Voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, |VID| = 0.2V, VCM = 1.25V, TA = 25°C). (Notes 3, 4, 5) PARAMETER Output Rise Time Output Fall Time SYMBOL CLHT CHLT CONDITIONS MIN TYP MAX RxOUT_ 0.1VCCO MAX9210/ to MAX9220 RxCLK OUT 0.9VCCO, Figure 3 MAX9214/MAX9222 3.52 5.04 6.24 2.2 3.15 3.9 2.2 3.15 3.9 RxOUT_ 0.9VCCO MAX9210/ to MAX9220 RxCLK OUT 0.1VCCO, Figure 3 MAX9214/MAX9222 1.95 3.18 4.35 1.3 2.12 2.9 1.3 2.12 2.9 8MHz 6600 7044 16MHz 2560 3137 34MHz 900 1327 66MHz 330 685 10MHz 6600 7044 20MHz 2500 3300 40MHz 960 1448 85MHz 330 685 DC-balanced mode, Figure 4 (Note 6) RxIN Skew Margin RSKM Non-DC-balanced mode, Figure 4 (Note 6) UNITS ns ns ps RxCLK OUT High Time RCOH Figures 5a, 5b 0.35 x RCOP ns RxCLK OUT Low Time RCOL Figures 5a, 5b 0.35 x RCOP ns RxOUT Setup to RxCLK OUT RSRC Figures 5a, 5b 0.30 x RCOP ns RxOUT Hold from RxCLK OUT RHRC Figures 5a, 5b 0.45 x RCOP ns RxCLK IN to RxCLK OUT Delay RCCD Figures 6a, 6b 4.9 Deserializer Phase-Locked Loop Set RPLLS Deserializer Power-Down Delay RPDD 6.17 8.1 ns Figure 7 32800 x RCIP ns Figure 8 100 ns Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 4: CL includes probe and test jig capacitance. Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP. Note 6: RSKM measured with ≤150ps cycle-to-cycle jitter on RxCLK IN. 4 _______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers (VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25°C, unless otherwise noted.) WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY WORST-CASE PATTERN 70 60 50 27 - 1 PRBS 40 80 70 50 40 27 - 1 PRBS 30 20 20 10 15 20 30 25 FREQUENCY (MHz) 35 40 5 120 100 80 35 40 MAX9214 NON-DC-BALANCED MODE 140 SUPPLY CURRENT (mA) 140 20 30 25 FREQUENCY (MHz) 160 MAX9210 toc03 MAX9214 DC-BALANCED MODE 15 WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY 160 10 MAX9210 toc04 5 120 100 80 60 60 40 40 5 20 35 50 65 15 80 30 45 60 75 90 FREQUENCY (MHz) FREQUENCY (MHz) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) MAX9214 4 tR 3 tF 2 1 7 OUTPUT TRANSITION TIME (ns) MAX9210 toc05 5 MAX9210 toc06 SUPPLY CURRENT (mA) WORST-CASE PATTERN 60 30 OUTPUT TRANSITION TIME (ns) MAX9220 NON-DC-BALANCED MODE 90 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 80 MAX9210 toc02 MAX9220 DC-BALANCED MODE 90 100 MAX9210 toc01 100 WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY MAX9220 6 tR 5 4 tF 3 2 1 2.5 3.0 3.5 4.0 4.5 OUTPUT SUPPLY VOLTAGE (V) 5.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX9210/MAX9214/MAX9220/MAX9222 Typical Operating Characteristics MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers Pin Description PIN TSSOP NAME 1, 2, 4, 5, 45, 46, 47 RxOUT14– RxOUT20 3, 25, 32, 38, 44 GND 6 DCB/NC 7, 13, 18 LVDS GND 8 RxIN0- FUNCTION Channel 2 Single-Ended Outputs Ground LVTTL/LVCMOS DC-Balance Programming Input: MAX9210: pulled up to VCC MAX9214: pulled up to VCC MAX9220: pulled up to VCC MAX9222: pulled up to VCC See Table 1. LVDS Ground Inverting Channel 0 LVDS Serial Data Input 9 RxIN0+ Noninverting Channel 0 LVDS Serial Data Input 10 RxIN1- Inverting Channel 1 LVDS Serial Data Input 11 RxIN1+ Noninverting Channel 1 LVDS Serial Data Input 12 LVDS VCC 14 RxIN2- Inverting Channel 2 LVDS Serial Data Input 15 RxIN2+ Noninverting Channel 2 LVDS Serial Data Input LVDS Supply Voltage 16 RxCLK IN- Inverting LVDS Parallel Rate Clock Input 17 RxCLK IN+ Noninverting LVDS Parallel Rate Clock Input 19, 21 PLL GND PLL Ground 20 PLL VCC PLL Supply Voltage 22 PWRDWN 23 RxCLK OUT 24, 26, 27, 29, 30, 31, 33 RxOUT0– RxOUT6 28, 36, 48 VCCO 34, 35, 37, 39, 40, 41, 43 RxOUT7– RxOUT13 42 VCC 6 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. Parallel Rate Clock Single-Ended Output. MAX9210/MAX9214, rising edge strobe. MAX9220/MAX9222, falling edge strobe. Channel 0 Single-Ended Outputs Output Supply Voltage Channel 1 Single-Ended Outputs Digital Supply Voltage _______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers DEVICE MAX9210 MAX9214 MAX9220 MAX9222 DCB/NC High or open Low High or open Low High or open Low High or open Low OUTPUT STROBE EDGE Rising Falling Falling Detailed Description The MAX9210/MAX9220 operate at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and 10MHz to 40MHz in non-DC-balanced mode. The MAX9214/MAX9222 operate at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in non-DC-balanced mode. The transition times of the single-ended outputs are increased on the MAX9210/MAX9220 for reduced EMI. DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1 for DCB/NC default settings and operating modes). In non-DC-balanced mode, each channel deserializes 7 bits every cycle of the parallel clock. In DC-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 DCbalance bits). The highest data rate in DC-balanced mode for the MAX9214 and MAX9222 is 66MHz x 9 = 594Mbps. In non-DC-balanced mode, the maximum data rate is 85MHz x 7 = 595Mbps. DC balanced 8 to 34 Non-DC balanced 10 to 40 DC balanced 16 to 66 Non-DC balanced 20 to 85 DC balanced 8 to 34 Non-DC balanced 10 to 40 DC balanced 16 to 66 Non-DC balanced 20 to 85 VCC RIN2 RxIN_ + OR RxCLK IN+ RxIN_ + OR RxCLK IN+ VCC - 0.3V RIN1 RIN1 1.2V RIN1 RIN1 RxIN_ - OR RxCLK IN- RxIN_ - OR RxCLK IN- NON-DC-BALANCED MODE DC-BALANCED MODE Figure 1. LVDS Input Circuits DC Balance Data coding by the MAX9209/MAX9213 serializers (which are companion devices to the MAX9210/ MAX9214/MAX9220/MAX9222 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros than ones, or 10 more ones than zeros, are transmitted. The maximum DSV for the clock channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on AC-coupled links. OPERATING FREQUENCY (MHz) OPERATING MODE Rising MAX9210/MAX9214/MAX9220/MAX9222 Table 1. DC-Balance Programming RCIP RxCLK OUT ODD RxOUT EVEN RxOUT RISING EDGE STROBE SHOWN. Figure 2. Worst-Case Test Pattern _______________________________________________________________________________________ 7 MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers 90% RxOUT_ OR RxCLK OUT 90% 10% RxOUT_ OR RxCLK OUT 10% 8pF CLHT CHLT Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME 1.3V RxCLK IN VID = 0 RCCD 1.5V 1.1V RSKM RxCLK OUT RSKM IDEAL MIN IDEAL Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay MAX INTERNAL STROBE + RxCLK IN Figure 4. LVDS Receiver Input Skew Margin VID = 0 RCCD RCIP 1.5V RxCLK OUT RxCLK OUT 2.0V 0.8V 0.8V RCOL RCOH RSRC RHRC 2.0V 0.8V RxOUT_ 2.0V 2.0V Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay 2.0V 0.8V 2V Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times PWRDWN 3V RCIP VCC RPLLS RxCLK OUT 2.0V 2.0V 0.8V 0.8V RCOH RSRC RxOUT_ 2.0V 0.8V 0.8V RHRC 2.0V 0.8V Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times 8 RxCLK IN RCOL RxCLK OUT HIGH-Z Figure 7. Phase-Locked Loop Set Time _______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers 0.8V RxCLK IN RPDD RxOUT_ RxCLK OUT AC-Coupling Benefits Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the common-mode voltage range of an LVDS receiver to nearly HIGH-Z Figure 8. Power-Down Delay + RxCLK IN CYCLE N - 1 TxIN15 CYCLE N CYCLE N + 1 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 RxIN2 TxIN8 RxIN1 TxIN1 RxIN0 TxIN_ IS DATA FROM THE SERIALIZER. Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode + RxCLK IN CYCLE N - 1 DCA2 CYCLE N CYCLE N + 1 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 DCA1 DCB1 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 DCA0 DCB0 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 RxIN2 DCA1 RxIN1 DCA0 RxIN0 TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER. Figure 10. Deserializer Serial Input in DC-Balanced Mode _______________________________________________________________________________________ 9 MAX9210/MAX9214/MAX9220/MAX9222 To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/ MAX9214/MAX9220/MAX9222 deserializers whether the data bits are inverted (see Figures 9 and 10). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC balance. PWRDWN MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0 to 2.4V, allowing approximately ±1V common-mode difference between the driver and receiver on a DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V). Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than ±1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However, two capacitors—one at the serializer output and one at the deserializer input—provide protection in case either end of the cable is shorted to a high voltage. Applications Information Selection of AC-Coupling Capacitors Voltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value MAX9209 MAX9213 MAX9210 MAX9214 MAX9220 MAX9222 TRANSMISSION LINE TxOUT RxIN 7 7 7:1 100Ω 1:7 7:1 100Ω 1:7 7:1 100Ω 1:7 PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 3:21 DESERIALIZER Figure 11. DC-Coupled Link, Non-DC-Balanced Mode 10 ______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT THE SERIALIZER INSTEAD OF THE DESERIALIZER. TxOUT MAX9210 MAX9214 MAX9220 MAX9222 RxIN 7 7 (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode series capacitors is (C x (RT + RO))/2 (Figure 12). The RC time constant for four equal-value series capacitors is (C x (RT + RO))/4 (Figure 13). RT is required to match the transmission line impedance (usually 100Ω) and RO is determined by the LVDS driver design (the minimum differential output resistance of 78Ω for the MAX9209/MAX9213 serializers is used in the following example). This leaves the capacitor selection to change the system time constant. In the following example, the capacitor value for a droop of 2% is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = - (2 x tB x DSV)/(ln (1 - D) x (RT + RO)) (Eq 1) Equation 1 is for two series capacitors (Figure 12). The bit time (tB) is the period of the parallel clock divided by 9. The DSV is 10. See equation 3 for four series capacitors (Figure 13). The capacitor for 2% maximum droop at 8MHz parallel rate clock is: C = - (2 x tB x DSV)/(ln (1 - D) x (RT + RO)) C = - (2 x 13.9ns x 10)/(ln (1 - 0.02) x (100Ω + 78Ω)) where: C = AC-coupling capacitor (F). tB = bit time (s). DSV = digital sum variation (integer). ln = natural log. D = droop (% of signal amplitude). RT = termination resistor (Ω). RO = output resistance (Ω). where: tJ = jitter (s). tT = transition time (s) (0 to 100%). D = droop (% of signal amplitude). C = 0.0773µF Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.02 tJ = 20ps ______________________________________________________________________________________ 11 MAX9210/MAX9214/MAX9220/MAX9222 MAX9209 MAX9213 MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers MAX9209 MAX9213 MAX9210 MAX9214 MAX9220 MAX9222 HIGH-FREQUENCY CERAMIC SURFACE-MOUNT CAPACITORS TxOUT RxIN 7 7 (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) (7 + 2):1 100Ω 1:(9 - 2) PLL 100Ω PLL 7 7 TxIN RxOUT 7 7 PWRDWN PWRDWN RxCLK OUT TxCLK IN TxCLK OUT RxCLK IN 21:3 SERIALIZER 3:21 DESERIALIZER Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode The transition time in a real system depends on the frequency response of the cable driven by the serializer. The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. Use high-frequency, surface-mount ceramic capacitors. Equation 1 altered for four series capacitors (Figure 13) is: C = - (4 x tB x DSV)/(ln (1 - D) x (RT + RO)) (Eq 3) Fail-Safe The MAX9210/MAX9214/MAX9220/MAX9222 have failsafe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the corresponding LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low. Fail-safe does not operate in DC-balanced mode. Input Bias and Frequency Detection In DC-balanced mode, the inverting and noninverting LVDS inputs are internally connected to +1.2V through 42kΩ (min) to provide biasing for AC-coupling (Figure 1). A frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low 12 frequency. In this case, all outputs are driven low. To prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mV by connecting a 10kΩ ±1% pullup resistor between the noninverting input and VCC, and a 10kΩ ±1% pulldown resistor between the inverting input and ground. These bias resistors, along with the 100Ω ±1% tolerance termination resistor, provide +15mV of differential input. However, the +15mV bias causes degradation of RSKM proportional to the slew rate of the clock input. For example, if the clock transitions 250mV in 500ps, the slew rate of 0.5mV/ps reduces RSKM by 30ps. Unused LVDS Data Inputs In non-DC-balanced mode, leave unused LVDS data inputs open. In non-DC balanced mode, the input failsafe circuit drives the corresponding outputs low and no pullup or pulldown resistors are needed. In DC-balanced mode, at each unused LVDS data input, pull the inverting input up to VCC using a 10kΩ resistor, and pull the noninverting input down to ground using a 10kΩ resistor. Do not connect a termination resistor. The pullup and pulldown resistors drive the corresponding outputs low and prevent switching due to noise. ______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers Input Clock and PLL Lock Time There is no required timing sequence for the application or reapplication of the parallel rate clock (RxCLK IN) relative to PWRDWN, or to a power-supply ramp for proper PLL lock. The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and clock should be stable to meet the lock time specification. When the PLL is locking, the outputs are low. Power-Supply Bypassing There are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs. Bypass each VCC, VCCO, PLL VCC, and LVDS VCC pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. RD = 330Ω (Figure 14). For IEC 61000-4-2, the LVDS inputs are rated for ±8kV Contact Discharge and ±15kV Air Discharge. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 15). For the Human Body Model, all pins are rated for ±5kV Contact Discharge. The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 16). For ISO 10605, the LVDS inputs are rated for ±8kV Contact Discharge and ±25kV Air Discharge. 5V Tolerant Input PWRDWN is 5V tolerant and is internally pulled down to GND. DCB/NC is not 5V tolerant. The input voltage range for DCB/NC is nominally ground to V CC . Normally, DCB/NC is connected to VCC or ground. 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE The MAX9210/MAX9214/MAX9220/MAX9222 ESD tolerance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC 61000-4-2 discharge components are CS = 150pF and STORAGE CAPACITOR DEVICE UNDER TEST CS 100pF RD 1.5kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 15. Human Body ESD Test Circuit Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer printedcircuit board (PCB) with separate layers for power, ground, LVDS inputs, and digital signals is recommended. ESD Protection DISCHARGE RESISTANCE Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit Cables and Connectors Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. RD 330Ω 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 330pF RD 2kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 16. ISO 10605 Contact Discharge ESD Test Circuit ______________________________________________________________________________________ 13 MAX9210/MAX9214/MAX9220/MAX9222 PWRDWN Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to 50µA or less. Driving PWRDWN high drives the outputs low until the PLL locks. The outputs of two deserializers can be bused to form a 2:1 mux with the outputs controlled by PWRDWN. Wait 100ns between disabling one deserializer (driving PWRDWN low) and enabling the second one (driving PWRDWN high) to avoid contention of the bused outputs. MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers Skew Margin (RSKM) Skew margin (RSKM) is the time allowed for degradation of the serial data sampling setup and hold times by sources other than the deserializer. The deserializer sampling uncertainty is accounted for and does not need to be subtracted from RSKM. The main outside contributors of jitter and skew that subtract from RSKM are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew. VCCO Output Supply and Power Dissipation The outputs have a separate supply (VCCO) for interfacing to systems with 1.8V to 5V nominal input logic levels. The DC Electrical Characteristics table gives the maximum supply current for VCCO = 3.6V with 8pF load at several switching frequencies with all outputs switching in the worst-case switching pattern. The approximate incremental supply current for VCCO other than 3.6V with the same 8pF load and worst-case pattern can be calculated using: II = CTVI 0.5fC x 21 (data outputs) + CTVIfC x 1 (clock output) where: II = incremental supply current. CT = total internal (CINT) and external (CL) load capacitance. VI = incremental supply voltage. fC = output clock switching frequency. The incremental current is added to (for VCCO > 3.6V) or subtracted from (for VCCO < 3.6V) the DC Electrical Characteristics table maximum supply current. The internal output buffer capacitance is CINT = 6pF. The worst-case pattern switching frequency of the data outputs is half the switching frequency of the output clock. In the following example, the incremental supply current is calculated for VCCO = 5.5V, fC = 34MHz, and CL = 8pF: The maximum supply current in DC-balanced mode for VCC = VCCO = 3.6V at fC = 34MHz is 106mA (from the DC Electrical Characteristics table). Add 10.4mA to get the total approximate maximum supply current at VCCO = 5.5V and VCC = 3.6V. If the output supply voltage is less than VCCO = 3.6V, the reduced supply current can be calculated using the same formula and method. At high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power dissipation rating. Do not exceed the maximum package power dissipation rating. See the Absolute Maximum Ratings for maximum package power dissipation capacity and temperature derating. Rising- or Falling-Edge Output Strobe The MAX9210/MAX9214 have a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLK OUT. The MAX9220/MAX9222 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLK OUT. The deserializer output strobe polarity does not need to match the serializer input strobe polarity. A deserializer with rising or falling edge output strobe can be driven by a serializer with a rising edge input strobe. VI = 5.5V - 3.6V = 1.9V CT = CINT + CL = 6pF + 8pF = 14pF where: II = CTVI 0.5FC x 21 (data outputs) + CTVIfC x 1 (clock output). II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz). II = 9.5mA + 0.9mA = 10.4mA. 14 ______________________________________________________________________________________ Programmable DC-Balance 21-Bit Deserializers DATA CHANNEL 0 LVDS DATA RECEIVER 0 RxIN0+ STROBE RxIN0- RxIN1+ STROBE SERIAL-TOPARALLEL CONVERTER RxIN2+ STROBE SERIAL-TOPARALLEL CONVERTER LVDS CLOCK RECEIVER RxCLK IN+ RxCLK IN- RxOUT7–13 DATA CHANNEL 2 LVDS DATA RECEIVER 2 RxIN2- TOP VIEW RxOUT0–6 DATA CHANNEL 1 LVDS DATA RECEIVER 1 RxIN1- SERIAL-TOPARALLEL CONVERTER Pin Configuration RxOUT14–20 RxOUT17 1 48 VCCO RxOUT18 2 47 RxOUT16 GND 3 46 RxOUT15 RxOUT19 4 45 RxOUT14 RxOUT20 5 44 GND DCB/NC 6 43 RxOUT13 LVDS GND 7 42 VCC RxIN0- 8 41 RxOUT12 RxIN0+ 9 40 RxOUT11 39 RxOUT10 38 GND RxIN1- 10 RxCLK OUT 7x/9x PLL REFERENCE CLOCK GENERATOR RxIN1+ 11 MAX9210 MAX9214 MAX9220 MAX9222 LVDS VCC 12 37 RxOUT9 LVDS GND 13 36 VCCO RxIN2- 14 35 RxOUT8 DCB/NC PWRDWN Chip Information MAX9210 TRANSISTOR COUNT: 10,248 MAX9214 TRANSISTOR COUNT: 10,248 MAX9220 TRANSISTOR COUNT: 10,248 MAX9222 TRANSISTOR COUNT: 10,248 PROCESS: CMOS RxIN2+ 15 34 RxOUT7 RxCLK IN- 16 33 RxOUT6 RxCLK IN+ 17 32 GND LVDS GND 18 31 RxOUT5 19 30 RxOUT4 PLL VCC 20 29 RxOUT3 PLL GND 21 28 VCCO PWRDWN 22 27 RxOUT2 23 26 RxOUT1 RxOUT0 24 25 GND PLL GND RxCLK OUT TSSOP ______________________________________________________________________________________ 15 MAX9210/MAX9214/MAX9220/MAX9222 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 48L TSSOP.EPS MAX9210/MAX9214/MAX9220/MAX9222 Programmable DC-Balance 21-Bit Deserializers N MARKING AAA A E H 1 2 3 TOP VIEW BOTTOM VIEW SEE DETAIL A b A1 A2 A CL e D c END VIEW SEATING PLANE SIDE VIEW ( b ) PARTING LINE 0.25 L b1 WITH PLATING DETAIL A NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L). 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED. 7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. c1 BASE METAL SECTION C-C PACKAGE OUTLINE, 48 & 56L TSSOP, 6.1mm BODY 21-0155 16 c ______________________________________________________________________________________ C 1 1 Programmable DC-Balance 21-Bit Deserializers REVISION NUMBER REVISION DATE REVISION DESCRIPTION PAGES CHANGED 0 — Initial release — 1 — — — 2 — — — 3 — — — 4 3/05 Various changes — 5 11/07 Removed all references to MAX9212/MAX9216 and thin QFN-EP package; various style edits; and updated package outline for TSSOP. All pages Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX9210/MAX9214/MAX9220/MAX9222 Revision History