ETC AT29C256-70PI

Features
• Fast Read Access Time - 70 ns
• 5-volt Only Reprogramming
• Page Program Operation
•
•
•
•
•
•
•
•
•
– Single Cycle Reprogram (Erase and Program)
– Internal Address and Data Latches for 64 Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Fast Program Cycle Times
– Page (64 Byte) Program Time - 10 ms
– Chip Erase Time - 10 ms
DATA Polling for End of Program Detection
Low-power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
256K (32K x 8)
5-volt Only
Flash Memory
AT29C256
Description
The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.
(continued)
Pin Configurations
Pin Name
Function
A0 - A14
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don’t Connect
DIP Top View
WE
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC and LCC Top View
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4
3
2
1
32
31
30
A7
A12
WE
DC
VCC
A14
A13
TSOP Top View
Type 1
Note: PLCC package pins 1 and 17
are DON’T CONNECT.
OE
A11
A9
A8
A13
A14
VCC
WE
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
Rev. 0046N–08/99
1
To allow for simple in-system reprogrammability, the
AT29C256 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar
to reading from a static RAM. Reprogramming the
AT29C256 is performed on a page basis; 64 bytes of data
are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased
by using a six-byte software code (although erasure before
programming is not needed).
During a reprogram cycle, the address locations and 64
bytes of data are internally latched, freeing the address and
data bus for other operations. Following the initiation of a
program cycle, the device will automatically erase the page
and then program the latched data using an internal control
timer. The end of a program cycle can be detected by
DATA polling of I/O7. Once the end of a program cycle has
been detected a new access for a read, program or chip
erase can begin.
Block Diagram
Device Operation
READ: The AT29C256 is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: A byte load is performed by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Byte loads are
used to enter the 64 bytes of a page to be programmed or
the software codes for data protection and chip erasure.
PROGRAM: The device is reprogrammed on a page
basis. If a byte of data within a page is to be changed, data
for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will
be indeterminate. Once the bytes of a page are loaded into
the device, they are simultaneously programmed during the
internal programming period. After the first data byte has
been loaded into the device, successive bytes are entered
in the same manner. Each new byte to be programmed
must have its high-to-low transition on WE (or CE) within
150 µs of the low-to-high transition of WE (or CE) of the
preceding byte. If a high-to-low transition is not detected
within 150 µs of the last low-to-high transition, the load
2
AT29C256
period will end and the internal programming period will
start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of
WE (or CE). A0 to A5 specify the byte address within the
page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has
been initiated, and for the duration of tWC, a read operation
will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature is available on the AT29C256. Once
the software protection is enabled a software algorithm
must be issued to the device before a program may be performed. The software protection feature may be enabled or
disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands
to specific addresses with specific data must be performed.
After the software data protection is enabled the same
three program commands must begin each program cycle
in order for the programs to occur. All software program
commands must obey the page program timing specifications. Once set, the software data protection feature
remains active unless its disable command is issued.
Power transitions will not reset the software data protection
feature, however the software feature will guard against
inadvertent program cycles during power transitions.
AT29C256
Once set, software data protection will remain active unless
the disable command sequence is issued.
After setting SDP, any attempt to write to the device without
the three-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of tWC, a read operation will effectively be a
polling operation.
After the software data protection’s three-byte command
code is given, a byte load is performed by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. The 64 bytes
of data must be loaded into each sector by the same procedure as outlined in the program section under device
operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C256 in
the following ways: (a) V CC sense—if V CC is below 3.8V
(typical), the program function is inhibited; (b) VCC power on
delay—once V CC has reached the V CC sense level, the
device will automatically time out 5 ms (typical) before programming; (c) Program inhibit—holding any one of OE low,
CE high or WE high inhibits program cycles; and (d) Noise
filter—pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer and may be
accessed by a hardware operation. For details, see Operating Modes or Product Identification.
DATA POLLING: The AT29C256 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT29C256
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased by using a six-byte software code. Please see
Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT29C256-70
AT29C256-90
AT29C256-12
AT29C256-15
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 5%
5V± 10%
5V± 10%
5V± 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
Program
VIL
VIH
VIL
Ai
DIN
5V Chip Erase
VIL
VIH
VIL
Ai
Standby/Write Inhibit
VIH
X(1)
X
X
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Voltage Chip Erase
VIL
VH(3)
VIL
VIL
VIL
VIH
Read
(2)
High Z
High Z
X
High Z
Product Identification
Hardware
Software(5)
Notes:
A1-A14 = VIL, A9 = VH, A0 = VIL
Manufacturer Code(4)
A1-A14 = VIL, A9 = VH, A0 = VIH
Device Code(4)
A0 = VIL
Manufacturer Code(4)
A0 = VIH
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: DC.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
4
Min
2.0
AT29C256
V
0.45
V
AT29C256
AC Read Characteristics
Symbol
Parameter
tACC
AT29C256-70
AT29C256-90
AT29C256-12
AT29C256-15
Min
Min
Min
Min
Max
Max
Max
Max
Units
Address to Output Delay
70
90
120
150
ns
(1)
CE to Output Delay
70
90
120
150
ns
(2)
OE to Output Delay
0
40
0
40
0
50
0
70
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
0
30
0
40
ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first
0
tCE
tOE
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
Parameter
Min
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
35
ns
tDH,tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
100
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
6
AT29C256
Max
Units
AT29C256
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
10
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
35
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
100
µs
ns
Program Cycle Waveforms(1)(2)(3)
Notes:
1.
A6 through A14 must specify the page address during each high-to-low transition of WE (or CE).
2.
OE must be high when WE and CE are both low.
3.
All bytes that are not loaded within the page being programmed will be indeterminate.
7
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA 80
TO
ADDRESS 5555
ENTER DATA
PROTECT STATE
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA
TO
PAGE (64 BYTES)(4)
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be re-activated at end of program cycle.
3. Data Protect state will be deactivated at end of program period.
4. 64 bytes of data MUST BE loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA
TO
PAGE (64 BYTES)(4)
Software Protected Program Cycle Waveform(1)(2)(3)
Notes:
1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE) after the software code has
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.
8
AT29C256
AT29C256
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
0
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
0
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is DC.
10
Software Product Identification Exit(1)
AT29C256
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
AT29C256
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. TEMPERATURE
1.4
N
O
R
M 1.2
A
L
I
1.0
Z
E
D
1.4
N
O
R
M
A
L
I
Z
E
D
1.3
1.2
1.1
1.0
I
0.9
C
C
0.8
-55
I
C
C
-25
5
35
65
95
125
0.8
0.6
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT
vs. ADDRESS FREQUENCY
1.1
N
O
R
M 1.0
A
L
I
0.9
Z
E
D
I
C
C
VCC = 5V
T = 25C
0.8
0.7
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
11
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
70
50
0.3
AT29C256-70JC
AT29C256-70PC
AT29C256-70TC
32J
28P6
28T
AT29C256-70JI
AT29C256-70TI
32J
28T
AT29C256-90JC
AT29C256-90PC
AT29C256-90TC
32J
28P6
28T
Commercial
(0° to 70°C)
AT29C256-90JI
AT29C256-90PI
AT29C256-90TI
32J
28P6
28T
Industrial
(-40° to 85°C)
AT29C256-12JC
AT29C256-12PC
AT29C256-12TC
32J
28P6
28T
Commercial
(0° to 70°C)
AT29C256-12JI
AT29C256-12PI
AT29C256-12TI
32J
28P6
28T
Industrial
(-40° to 85°C)
AT29C256-15JC
AT29C256-15PC
AT29C256-15TC
32J
28P6
28T
Commercial
(0° to 70°C)
AT29C256-15JI
AT29C256-15PI
AT29C256-15TI
32J
28P6
28T
Industrial
(-40° to 85°C)
90
120
150
50
50
50
0.3
0.3
0.3
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28T
28-lead, Plastic Thin Small Outline Package (TSOP)
12
AT29C256
Operation Range
Commercial
(0° to 70°C)
Industrial
(-40° to 85°C)
AT29C256
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
.045(1.14) X 45˚
PIN NO. 1
IDENTIFY
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
.050(1.27) TYP
1.47(37.3)
1.44(36.6)
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
PIN
1
.566(14.4)
.530(13.5)
.530(13.5)
.490(12.4)
.021(.533)
.013(.330)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.022(.559) X 45˚ MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
.090(2.29)
MAX
1.300(33.02) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
11.9 (0.469)
11.7 (0.461)
13.7 (0.539)
13.1 (0.516)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
5 REF
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
13
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Atmel Colorado Springs
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Atmel Rousset
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Zone Industrielle
13106 Rousset Cedex
France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
Marks bearing
®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0046N–08/99/xM