RF2406 8 CDMA/FM LOW NOISE AMPLIFIER/MIXER Typical Applications • CDMA/FM Cellular Systems • General Purpose Downconverter • Supports Dual-Mode AMPS/CDMA • Commercial and Consumer Systems • Supports Dual-Mode TACS/CDMA • Portable Battery Powered Equipment D 44 ES 9 & IG R F2 N 46 S .012 .008 .386 .402 .025 .244 .228 Si Bi-CMOS SiGe HBT F2 .050 .016 .010 .008 Package Style: SSOP-28 Si CMOS • Complete Receiver Front-End GND1 2 27 GND4 • Stepped LNA Gain Control VCC1 3 26 LNA OUT • Low Current-Drain “Lazy” Mode VCC2 4 25 GND5 IF2- 5 24 GND6 N S ee O T U 28 GND3 P ro Features LNA IN 1 IF2+ 6 23 GND7 pg GND2 7 22 BYP IF1+ 8 21 MIX IN IF1- 9 20 GND8 C1 10 19 LO IN- C2 11 C3 12 18 GND9 CONTROL LOGIC 17 LO OUT C4 13 16 GND11 PD 14 15 LO IN+ Functional Block Diagram Rev B8 000822 8 GaAs MESFET F ra O de R d ! GaAs HBT .069 .053 8°MAX 0°MIN s Optimum Technology Matching® Applied 1 .032 1 R N du E ct W The RF2406 is a receiver front-end designed for the receive section of dual-mode CDMA/FM cellular applications. It is designed to amplify and down-convert RF signals while providing 30dB of stepped gain control range and features digital control of LNA gain, IF output selection, LO buffer enable, power down mode, and low current “lazy” mode. The digitally selected “lazy” mode reduces current drain by approximately 10mA, putting the IC in a lower current drain, noise and IP3 state. This gives the receiver designer added flexibility to dynamically optimize these downconverter parameters. Noise Figure, IP3, and other specs are designed to be compatible with the IS-95 Interim Standard for CDMA cellular communications. The IC is manufactured on an advanced Silicon Bipolar process and packaged in an SSOP-28. Si BJT .010 .004 .157 .150 FRONT-ENDS Product Description • Buffered LO Output • Digitally Selectable IF Outputs • 500MHz to 1100MHz Operation Ordering Information RF2406 RF2406 PCBA CDMA/FM Low Noise Amplifier/Mixer Fully Assembled Evaluation Board RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-13 RF2406 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature Parameter Rating Unit -0.5 to +5.0 +6 -40 to +85 -40 to +150 VDC dBm °C °C Specification Min. Typ. Max. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Power Supply Voltage Current Consumption 2.7 to 4.0 20 25 26 18 adds 4 subtracts 10 < 20 Cascade Conversion Gain Cascade Input IP3 to IF1 Cascade Noise Figure Cascaded Perform. to IF2 Input P1dB Reverse Isolation Input VSWR 14.5 7.5 -5 2.5 4.5 9.0 +7 >+14 >+20 -11 25 <4:1 dB dB dB dB dB dB dBm dBm dBm dBm dB Output VSWR <1.5:1 Input IP3 8-14 pg N S ee O T U Noise Figure ro P 1 1kΩ balanced load, 3.0dB Image Filter Loss CDMA Max. Gain 870Ω load, 3dB Image Filter Loss FM dB dBm dB First Section (LNA) FM CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain LO Buffer ON “Lazy” Mode Power Down dB dBm dB 18 -4 4.3 F ra O de R d Cascade Conversion Gain Cascade Input IP3 Cascade Noise Figure 24 -4 4.3 R Cascaded Perform. to IF1 V mA mA mA mA mA mA µA s Max Dynamic Range Mode MHz MHz MHz N du E ct W 8 D 44 ES 9 & IG R F2 N 46 S 500 to 1100 500 to 1100 0.1 to 250 F2 RF Frequency Range LO Frequency Range IF Frequency Range Gain Condition T = 25°C, VCC =3.6V, RF=881MHz, LO=966MHz @-3dBm RF2=882 MHz for IIP3 Measurements See Mode Control Logic Table Overall FRONT-ENDS Caution! ESD sensitive device. FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain FM and CDMA Max. Gain Internally matched for optimum noise figure from 50Ω source With external match (partial) Rev B8 000822 RF2406 Parameter Specification Min. Typ. Max. Unit Condition Second Section (Mixer, IF1 or IF2 Output) Noise Figure Input VSWR Input IP3 to IF1 Input IP3 to IF2 Input P1dB, IF2 Input P1dB, IF1 MIX IN to IF1, IF2 Rejection IF1, IF2 Output Freq. Range Output Impedance LO Input LO Input Range LO Output Level LO Output Level LO IN to LNA Input Rejection LO IN to IF1, IF2 Rejection LO Input VSWR -6 to 0 0 -35 37 15 <2:1 “Lazy” Mode Noise Figure Input P1dB Reverse Isolation Input VSWR Output VSWR Rev B8 000822 Buffer ON, 0dBm input Buffer OFF, 0dBm input <1.5:1 870Ω load, 3dB Image Filter Loss. FM dB dBm dB dB dB dB dB dB dB dBm dBm dBm dBm dB 8 FRONT-ENDS F2 dB dBm dB R 9.0 6.2 -5 2.4 4.8 9.0 +1 >+6 >+20 -16 25 <4:1 ro pg N S ee O T U Input IP3 15.3 -8 4.0 P Gain 21 -8 4.1 F ra O de R d First Section (LNA) With external IF interface network IF1, balanced, open collector IF2, single ended, with external inductor. With external matching network s Cascade Conversion Gain Cascade Input IP3 Cascade Noise Figure dBm dBm dBm dB dB N du E ct W Cascaded Perform. to IF2 dBm dBm dBm dBm dB MHz kΩ Ω IF 1, 1kΩ balanced load. IF 2, 870Ω load. Single sideband. With external matching network 1kΩ balanced load, 3.0dB Image Filter Loss. CDMA Max. Gain Cascaded Perform. to IF1 Cascade Conversion Gain Cascade Input IP3 to IF1 Cascade Noise Figure dB dB dB 1 16 7 11.5 <1.5:1 +7 +7 -4 -8 35 70 to 100 >1 870 D 44 ES 9 & IG R F2 N 46 S Conversion Gain FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain CDMA Nom. Gain CDMA Min. Gain FM and CDMA Max. Gain FM and CDMA Max. Gain Internally matched for optimum noise figure from 50Ω source With external match (partial) 8-15 RF2406 Parameter Specification Min. Typ. Max. Unit Condition Second Section (Mixer, IF1 or IF2 Output) LO Input LO Input Range LO Output Level LO Output Level LO IN to LNA Input Rejection LO IN to IF1, IF2 Rejection LO Input VSWR H H L L H H L L X X X ro P C3 X X X X X X X X H L X C4 PD H H H H L L L L X X X H H H H H H H H H X L R C2 L H H L L H H L X X L Buffer On, 0dBm input Buffer Off, 0dBm input With external matching network s C1 F ra O de R d MODE FM (IF2) CDMA Max. Gain (IF1) CDMA Nom. Gain (IF1) CDMA Min. Gain (IF1) Lazy FM (IF2) Lazy CDMA Max. Gain (IF1) Lazy CDMA Nom. Gain (IF1) Lazy CDMA Min. Gain (IF1) LO Buffer ON LO Buffer OFF Power Down With external IF interface network IF1, balanced, open collector IF2, single ended, with external inductor. dBm dBm dBm dB dB N du E ct W Mode Control Logic dBm dBm dBm dBm dB MHz kΩ Ω pg N S ee O T U FRONT-ENDS 8 -6 to 0 0 -35 30 15 <2:1 IF 1, 1kΩ balanced load. IF 2, 870Ω load. Single sideband. With external matching network 1 Noise Figure Input VSWR Input IP3 to IF1 Input IP3 to IF2 Input P1dB, IF2 Input P1dB, IF1 MIX IN to IF1, IF2 Rejection IF1, IF2 Output Freq. Range Output Impedance dB dB dB D 44 ES 9 & IG R F2 N 46 S 14 5.5 9.5 <1.5:1 +2 +2 -9 -6 35 70 to 100 >1 870 F2 Conversion Gain 8-16 Rev B8 000822 RF2406 Pin 1 Function LNA IN Description Interface Schematic RF Input pin. This pin is internally matched for optimum noise figure from a 50Ω source. This pin is internally DC biased and, if connected to a device with DC present, should be DC blocked with a capacitor suitable for the frequency of operation. VCC1 LNA OUT LNA IN VCC1 4 VCC2 See pin 1. Same as pin 6, except complementary output. For typical single ended operation, this pin is connected directly to VCC. 6 IF2+ FM IF Output pin. This is a balanced output, but is typically used as a single-ended output. The internal circuitry, in conjunction with an external matching/bias inductor to VCC, sets the operating impedance. This inductor is typically incorporated in the matching network between the output and IF filter. The net output impedance, including the external inductor, is about 870Ω at 85MHz. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. See Application Schematic. Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. CDMA IF Output pin. This is a balanced output. The internal circuitry, in conjunction with an external matching/bias inductor to VCC, sets the operating impedance. This inductor is typically incorporated in the matching network between the output and IF filter. The net output impedance, including the external inductor, at 85MHz is higher than 1kΩ, even though the part is designed to drive a 1kΩ load. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. See Application Schematic. Same as pin 8, except complementary output. BIAS LO OUT See pin 6. 8 IF2+ F2 IF2- IF2- 8.5 pF R N du E ct W 5 VCC2 FRONT-ENDS 3 Ground connection for the LNA circuits. Keep traces physically short and connect immediately to ground plane for best performance. Supply Voltage for the LNA. External inductance, ~12nH, is required in addition to internal inductance to achieve optimum LNA performance. This extra inductance can be easily achieved with a thin microstrip line. The value of this inductance will change with the frequency of operation. RF and IF bypassing is required on the supply side of the inductance. The ground side of the bypass capacitors should connect immediately to ground plane. Supply Voltage for the LO buffer amplifier, bias circuits, and control logic. External RF and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. 1 GND1 D 44 ES 9 & IG R F2 N 46 S 2 GND2 8 IF1+ N S ee O T U P IF 1+ ro 7 F ra O de R d s 2.1 kΩ 11 12 IF 1C1 pg 9 10 C2 C3 Rev B8 000822 1.2 pF 1.2 pF See pin 8. Control line for mode/gain select. See specification table for details. The threshold voltage is 1.6V, and the pin draws less than 50µA when selected. C1 Control line for mode/gain select. See specification table for details. The threshold voltage is 1.6V, and the pin draws less than 50µA when selected. C3 Enable pin for the LO output buffer amplifier. This is a digitally controlled input. A logic "high" turns the buffer amplifier on, and the current consumption increases by 4mA (with 0dBm LO input). A logic "low" turns the buffer amplifier off. The threshold voltage is approximately 1.6V. GND2 IF1- 50 kΩ 50 kΩ 50 kΩ C3 8-17 RF2406 14 PD Description Interface Schematic Enable pin for “Lazy Mode”. This is a digitally controlled input. A logic "high" maintains the part in full performance mode. A logic "low" places the part in a reduced-current/reduced performance mode. See the specification table for details. The threshold voltage is 1.6V, and the pin draws less than 50µA when selected. Power down pin. A logic “low” turns the part off. A logic “high” (>1.6V) turns the part on. In addition, pin 10 (C1) should also be taken low during power down. LO IN+ Mixer LO Balanced Input Pin. For single-ended input operation, this pin is used as an input and pin 18 is bypassed to ground. 16 GND11 17 LO OUT 18 GND9 19 20 LO INGND8 Ground connection for LO buffer amplifier. Keep traces physically short and connect immediately to ground plane for best performance. Optional Buffered LO Output. This pin is internally DC blocked and matched to 50Ω. The buffer amplifier is switched on or off by the voltage level at pin 12. Die flag ground. Keep traces physically short and connect immediately to ground plane for best performance. Mixer LO bypass. 21 MIX IN 27 28 GND4 GND3 See pin 4. See pin 15. MIX IN F2 GND7 GND6 GND5 LNA OUT LO IN- Internal voltage reference. External RF and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 2. R 23 24 25 26 LO IN+ s BYP Ground connection for the mixer. Keep traces physically short and connect immediately to ground plane for best performance. Mixer RF Input Pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. External matching network sets RF and IF impedance for optimum performance. N du E ct W 22 50 kΩ PD D 44 ES 9 & IG R F2 N 46 S 15 50 kΩ C4 Same as pin 2. ro F ra O de R d Same as pin 2. See pin 1. P LNA Output pin. This pin is internally DC blocked and externally matched to 50Ω at pin 3 in order to facilitate an easy interface to a 50Ω Image Filter. Same as pin 25. Same as pin 25. pg N S ee O T U FRONT-ENDS 8 Function C4 1 Pin 13 8-18 Rev B8 000822 RF2406 Application Schematic C L 1 28 2 27 3 26 4 25 VCC 1 µF 33 nF FM SAW Filter L FM IF OUT 10 nH 5 6 D 44 ES 9 & IG R F2 N 46 S 12 nH 24 23 33 nF L L CDMA SAW Filter CDMA IF OUT 7 L 22 33 nF 8 9 Rx RF Filter 1 LNA IN 15 nH 21 20 C1 10 19 C2 11 18 C3 12 15 nH 33 nF PD 16 12 nH 180 Ω LO IN 15 33 nF pg N S ee O T U P ro F ra O de R d s 14 8 LO OUT 17 Rev B8 000822 8-19 FRONT-ENDS 13 F2 C4 R N du E ct W CONTROL LOGIC RF2406 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) L3* DNI P1 P1-3 50 Ω µstrip J2 FM IF OUT C3 10 pF L1 150 nH C1 33 nF + C11 1 uF 50 Ω µstrip C13 33 nF C14 9 pF L6 3.3 uH R1 33 Ω R2 68 Ω L5 3.3 uH L9 390 nH C12 9 pF T1 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 VCC P2-3 GAIN LO BUFFER LAZY LO BUFFER 2 GND 3 LAZY P3-1 P3-3 CON3 L14 10 nH R8 0Ω 1 IF SELECT 2 GND 3 GAIN CON3 50 Ω µstrip J4 LNA OUT R9* DNI 3 OUT GND F1* C7 33 nF C5 33 nF L8 15 nH Rx RF FILTER L7* DNI 50 Ω µstrip L10 15 nH J5 MIXER IN 18 11 TRANS3 12 8 3 2 C15* DNI IF SELECT GND P3 1 1 R4* DNI R3 10 Ω 2 P2-1 IN C1 33 nF R6 10 Ω ENABLE CON3 L2 12 nH VCC P2 1 D 44 ES 9 & IG R F2 N 46 S C4 33 nF R5 10 Ω J3 CDMA IF OUT P1-1 C10 33 nF 1 50 Ω µstrip L4 47 nH CONTROL LOGIC 50 Ω µstrip 17 13 16 14 15 L13 12 nH R7* DNI C8 3 pF C9 33 nF 50 Ω µstrip J6 LO OUT J7 LO IN 2406400 Rev- pg N S ee O T U P ro F ra O de R d s R FRONT-ENDS N du E ct W ENABLE F2 J1 LNA IN C2* DNI 8-20 Rev B8 000822 RF2406 Evaluation Board Layout Board Size 3.088" x 2.948" FRONT-ENDS F2 8 pg N S ee O T U P ro F ra O de R d s R N du E ct W 1 D 44 ES 9 & IG R F2 N 46 S Board Thickness 0.056”, Board Material FR-4, Multi-Layer Rev B8 000822 8-21 pg P ro s R 1 D 44 ES 9 & IG R F2 N 46 S 8 8-22 F2 N du E ct W F ra O de R d N S ee O T U FRONT-ENDS RF2406 Rev B8 000822