Features • All-in-one Design • • • • • • • – MIDI Control Processor – Synthesis – Compatible Effects: Reverb + Chorus – Programmable Spatial Effects for Four-channel Surround(1) – Four-band Stereo Equalizer State-of-the-art Synthesis Supplies Best Quality for Price – 34-voice Polyphony + Effects – Up to 1 MB Wavetable/Firmware Support Synthesizer Chipset: ATSAM9713 + 8-Mbit ROM + 32K x 8 SRAM + DAC Hardware-programmable DAC Mode – I2S 16 to 20 bits – Japanese 16 bits Firmware/Sample Set Available for Turnkey Designs – 8-Mbit GS® GMS960800B(2) – 8-Mbit CleanWave® GMS970800B Typical Applications: Cost-sensitive Portable Karaoke/VCD Karaoke 80-lead TQFP Package: Small Footprint, Easy Mounting Ideal for Battery Operation – Low Power – Power-down Mode – Wide Supply Voltage Range: 3V to 4.5V Core, 3V to 5.5V Periphery Notes: 1. Four-channel surround requires additional DAC. 2. GMS960800B with express permission of Roland Corporation. Special licensing conditions apply. Refer to warning on last page of this datasheet. Sound Synthesis ATSAM9713 Low-cost Integrated Synthesizer with Effects Description The highly integrated architecture of the ATSAM9713 combines a specialized highperformance RISC digital signal processor and a general-purpose 16-bit CISC control processor on a single chip. An on-chip memory management unit allows the digital signal processor and the control processor to share external ROM and RAM devices. The ROM bus width should be 16 bits while the SRAM can be selected to be 8 or 16 bits wide. When using an 8-bit SRAM, fast type (static cache) should be selected because two SRAM cycles will be completed in one ROM cycle duration. Running at 300 million operations per second (MOPS), the digital signal processor supports high-quality PCM synthesis as well as most important functions like reverb, chorus, surround effect and equalizer. By adding an additional stereo DAC, four-channel audio surround can also be obtained. The ATSAM9713 operates from a low-frequency 9.6 MHz typical crystal. A built-in PLL raises this frequency to a 38.4 MHz internal clock that controls the two processors. Care has been taken that output pin signals change only when necessary. This minimizes RFI (radio frequency interferences) and power consumption. Minimizing RFI is mostly important in order to comply with standards such as FCC, CSA and CE. The core power supply for the ATSAM9713 should range from 3V to 4.5V; the periphery supports supply from 3V to 5.5V. Therefore, by selecting 3.3V ROM, SRAM and DAC, it is possible to develop low-power/low-voltage portable applications. Rev. 1712B-DRMSD–11/02 1 Figure 1. Typical Hardware Configuration 1 MB ROM MIDI_IN 2 32K x 8 RAM ATSAM9713 Stereo DAC Audio Out ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Pin Description Pins by Function Table 1. Power Supply Group Pin Name Pin Number Type Function GND 5, 14, 21, 23, 36, 38, 57, 61, 62, 65, 74 PWR Digital Ground All pins should be connected to a ground plane. VCC 1, 6, 13, 18, 22, 32, 56, 6480 PWR Power Supply, 3V to 5.5V All pins should be connected to a VCC plane VC3 7, 17, 63 PWR Core Power Supply, 3V to 4.5V All pins should be connected to nominal 3.3V. If 3.3V is not available, then VC3 can be derived from 5V by two 1N4148 diodes in series. Pin Number Type Function 15 IN Table 2. Serial MIDI Pin Name MIDI_IN Serial TTL MIDI IN. All controls are received by this pin. Table 3. External ROM/RAM Group Pin Name Pin Number Type Function WA[18:0] 37, 39, 41 - 55, 58, 59 OUT External ROM/RAM address for up to 512K words (8M bits) of memory. ROM memory holds firmware and PCM data. RAM memory holds working variables and effects delay lines. WD[15:0] 66 - 73, 75 - 79, 2 - 4 I/O External ROM/RAM data. Holds read data from ROM or RAM when WOE is low, writes data to RAM when WWE is low. WCS0 29 OUT External ROM chip select, active low. WCS1 30 OUT External RAM chip select, active low. WOE 31 OUT External ROM/RAM output enable, active low. WWE 28 OUT External RAM write, active low. RBS 20 OUT RAM byte select. Used as lower address from RAM when an 8-bit wide RAM is connected. Note: Pin names exhibiting an overbar (WOE for example) indicate that the signal is active low. Table 4. Digital Audio Group Pin Name Pin Number Type Function CLBD 19 OUT Digital audio bit clock WSBD 27 OUT Digital audio left/right select DABD0 25 OUT Digital audio main stereo output DABD1 26 OUT Auxiliary digital stereo output. Reserved for surround effects. DAC/DAAD 24 IN DAC type: 0 = I2S 16 to 20 bits, 1 = Japanese 16 bits Can also be used as digital audio input if 32K x 16 RAM is connected. 3 1712B–DRMSD–11/02 Table 5. Miscellaneous Group Pin Name Pin Number Type Function X1 X2 10, 9 LFT 8 RESET 11 IN Reset input, active low. This is a Schmitt trigger input, allowing direct connection of an RC network. PDWN 12 IN Power-down, active low. When power-down is active, then all output pins will be floated. The crystal oscillator will be stopped. To exit from power-down, PDWN should be high and RESET applied. 33, 34, 35 IN Test pins. Should be grounded. 16 OUT TEST[2:0] RUN 4 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (3.3V input). X2 cannot be used to drive external circuits. PLL external RC network When high, indicates that the synthesizer is up and running. ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VCC WD12 WD11 WD10 WD9 WD8 GND WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 GND VCC VC3 GND GND Figure 2. ATSAM9713 Pinout in 80-lead TQFP Package 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC WA18 WA17 GND VCC WA16 WA15 WA14 WA13 WA12 WA11 WA10 WA9 WA8 WA7 WA6 WA5 WA4 WA3 WA2 GND VCC GND DAC/DAAD DABD0 DABD1 WSBD WWE WCS0 WCS1 WOE VCC TEST0 TEST1 TEST2 GND WA0 GND WA1 NC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VCC WD13 WD14 WD15 GND VCC VC3 LFT X2 X1 RESET PDWN VCC GND MIDI IN RUN VC3 VCC CLBD RBS 5 1712B–DRMSD–11/02 Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Ambient Temperature (Power Applied)................-40°C to + 85°C Storage Temperature.........................................-65°C to + 150°C Voltage on any pin (except X1)......................-0.5V to VCC + 0.5V VCC Supply Voltage..............................................-0.5V to + 6.5V. VC3 Supply Voltage...............................................-0.5V t0 + 4.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect device reliability. Maximum IOL per I/O pin.....................................................10mA Recommended Operating Conditions Table 7. Recommended Operating Conditions Symbol Parameter/Condition (1) Min Typ Max Unit 3 3.3/5.0 5.5 V 3.3 4.5 V 70 °C VCC Supply Voltage VC3 Supply Voltage 3 TA Operating Ambient Temperature 0 Note: 1. When using 3.3V supply in a 5V environment, care must be taken that any pin voltage does not exceed VCC + 0.5V. Pin X1 is powered by VC3 input. If X1 is driven by a 5V device, then a minimum series resistor is required (typ 330W). DC Characteristics Table 8. DC Characteristics (TA = 25°C, VC3 = 3.3V ± 10%) Symbol Parameter/Condition VCC Min VIL Low-level Input Voltage 3.3 5.0 VIH High-level Input Voltage 3.3 5.0 VOL Low-level Output Voltage IOL = -3.2mA 3.3 5.0 VOH High-level Output Voltage IOH = 0.8mA 3.3 5.0 ICC Power Supply Current (crystal freq. = 9.6 MHz) 3.3 5.0 Power-down Supply Current 6 Typ Max Unit -0.5 -0.5 1.0 1.7 V V 2.3 3.3 VCC + 0.5 VCC + 0.5 V V 0.45 0.45 V V 2.8 4.5 V V 70 25 90 35 mA mA 70 100 µA ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Timings All timing conditions: TA = 25°C, VCC = 5V, VC3 = 3.3V, all outputs except X2 and LFT load capacitance = 30pF, crystal frequency or external clock at X1 = 9.6 MHz. External ROM Timing Figure 3. ROM Read Cycle tRC WCS0 tCSOE WA[24:0] tPOE WOE tOE WD[15:0] tDF t ACE Table 9. Timing Parameters Symbol Parameter Min tRC Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE Low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Access Time 125 ns tOE Output Enable Access Time 70 ns tDF Chip Select or WOE High to Input Data High-Z 0 External RAM Timing Typ Max Unit ns 80 78 ns ns 50 ns Figure 4. 16-bit SRAM Read Cycle tRC WCS1 tCSOE WA[24:0] tPOE WOE WWE tOE WD[15:0] tDF tACE 7 1712B–DRMSD–11/02 Figure 5. 16-bit SRAM Write Cycle tWC WCS1 tCSWE WA[18:0] WOE tWP WWE tDW tDH WD[15:0] Table 10. Timing Parameters Symbol Parameter Min tRC Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE Low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Access Time 125 ns tOE Output Enable Access Time 70 ns tDF Chip Select or WOE High to Input Data High-Z 0 tWC Write Cycle Time 130 ns tCSWE Write Enable Low from CS or Address or WOE 40 ns tWP Write Pulse Width tDW Data Out Setup Time 95 ns tDH Data Out Hold Time 10 ns 8 Typ Max Unit ns 80 78 ns 50 104 ns ns ns ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Figure 6. 8-bit SRAM Read Cycle tRC WCS1 tCSOE WA[18:0] tPOE WOE WWE tORB tACE RBS tOE tACH tDF Low WD[7:0] High Figure 7. 8-bit SRAM Write Cycle t WC WCS1 tCSWE WA[18:0] WOE t WP t WP WWE tAS RBS tDW1 tDH1 WD[7:0] Low tDW2 tDH2 High 9 1712B–DRMSD–11/02 Table 11. Timing Parameters Symbol Parameter Min tRC Word Read Cycle Time 130 tCSOE Chip Select Low/Address Valid to WOE Low 45 tPOE Output Enable Pulse Width tACE Chip Select/Address Low Byte Access Time 70 ns tOE Output Enable Low Byte Access Time 20 ns tORB Output Enable Low to Byte Select High tACH Byte Select High Byte Access Time 45 tDF Chip Select or WOE High to Input Data High-Z 0 tWC Word Write Cycle Time 130 ns tCSWE 1st WWE Low from CS or Address or WOE 40 ns tWP Write (Low and High Byte) Pulse Width 20 ns tDW1 Data Out Low Byte Setup Time 25 ns tDH1 Data Out Low Byte Hold Time 20 ns tAS RBS High to Second Write Pulse 8 ns tDW2 Data Out High Byte Setup Time 40 ns tDH2 Data Out High Byte Hold Time 10 ns Digital Audio Typ Max Unit ns 80 78 ns ns 26 ns ns 50 ns Figure 8. Digital Audio Timing tCW tCLBD tCW WSBD CLBD tSOD tSOD DABD0 DABD1 DAC/DAAD (1) Note: 1. When used as audio in. Table 12. Timing Parameters Symbol Parameter Min tCW CLBD Rising to WSBD Change 200 ns tSOD DABD Valid before/after CLBD Rising 200 ns tCLBD CLBD Cycle Time 10 Typ 416.67 Max Unit ns ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Digital Audio Frame Figure 9. Digital Audio Frame Format WSBD (I2S) (1) WSBD(1) (Japanese) CLBD DABD0 DABD1 (2) DAC/DAAD (3) X MSB LSB (16 bits) X X X X X X X X X X LSB (20 bits) X MSB LSB (18 bits) Notes: 1. Selection between I2S and Japanese format is through pin DAC/DAAD in case of 32K x 8 SRAM. 2. Digital audio in is available only in case of 32K x 16 SRAM. In this case, DAAD is 16 bits only. 3. When used as audio in. Reset and Power-down During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20 ms. A typical RC/diode power-up network can be used. After the low-to-high transition of RESET, the following occurs: • Synthesis enters an idle state • The RUN output is set to zero • Firmware execution starts from address 0100H in ROM space (WCS0 low) If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power-down, PDWN has to be asserted high, then RESET applied. Recommended Board Layout As for all HCMOS high-integration ICs, some rules of board layout should be followed for reliable device operation: • GND, VCC, VC3 distribution, decouplings All GND, VCC, VC3 pins should be connected. GND and VCC planes are strongly recommended below the ATSAM9713. The board GND and VCC distribution should be in grid form. For 5V VCC operation, if 3.3V is not available, VC3 can be connected to VCC by two 1N4148 diodes in series. This guarantees a minimum voltage drop of 1.2V. Recommended VCC decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC3 requires a single 0.1 µF decoupling close to the IC. • Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the ATSAM9713 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM9713. 11 1712B–DRMSD–11/02 • Analog section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the codec vendor recommended layout for correct implementation of the analog section. • Unused inputs Unused inputs should always be connected. A floating input can cause internal oscillation inside the IC, which can destroy the IC by dramatically increasing the power consumption. If you plan to use the power-down feature, care should be taken that no pin is left floating during power- down. Usually, a 1 MW ground return is sufficient. Recommended Crystal Compensation and LFT Filter Figure 10. Recommended Crystal Compensation and LFT FIlter Description C1 X1 22 pF X1 9.6 MHz C4 X2 22 pF LFT R1 100Ω C2 2.2 nF VCC Note: 12 DABD0 DABD1 WSBD CLBD RUN PDWN C3 10 nF The X2 output cannot be used to drive another circuit. ATSAM9713 1712B–DRMSD–11/02 ATSAM9713 Mechanical Dimensions Figure 11. 80-lead Thin Plastic Quad Flat Pack Table 13. Package Dimensions (in mm) Dimension Min Typ Max A 1.40 1.50 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 D 15.90 16.00 16.10 D1 13.90 14.00 14.10 E 15.90 16.00 16.10 E1 13.90 14.00 14.10 L 0.45 0.60 0.75 P – 0.65 – B 0.22 0.32 0.38 13 1712B–DRMSD–11/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Warning: GMS960800B may not be installed in any musical instrument except electronic keyboards and synthesizers that have a sale price of less than $75 FOB. Using this product in the manufacture of musical instruments or selling this product for use in a musical instrument (other than the exceptions noted above) is a violation of the intellectual property rights of Roland Corporation and will result in liability for infringement. e-mail [email protected] Web Site http://www.atmel.com © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ®, Dream ® and CleanWave ® are the registered trademarks of Atmel. GS® is the registered trademark of the Roland Company. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1712B–DRMSD–11/02 0M