MAXIM MAX3679AETJ+

19-4858; Rev 0; 8/09
KIT
ATION
EVALU
E
L
B
AVAILA
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
Features
♦ Crystal Oscillator Interface: 25MHz
The MAX3679A is a low-jitter precision clock generator
with the integration of three LVPECL and one LVCMOS
outputs optimized for Ethernet applications. The device
integrates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet applications.
Maxim’s proprietary PLL design features ultra-low jitter
(0.36psRMS) and excellent power-supply noise rejection,
minimizing design risk for network equipment.
♦ CMOS Input: 25MHz
♦ Output Frequencies for Ethernet
62.5MHz, 125MHz, 156.25MHz, 312.5MHz
♦ Low Jitter
0.14psRMS (1.875MHz to 20MHz)
0.36psRMS (12kHz to 20MHz)
♦ Excellent Power-Supply Noise Rejection
♦ No External Loop Filter Capacitor Required
Applications
Ordering Information
Ethernet Networking Equipment
Pin Configuration appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX3679AETJ+
-40°C to +85°C
32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Application Circuit
+3.3V ±5%
0.1μF
10.5Ω
VCC
10μF
0.1μF
VCCO_A
VCCO_B
VCCA
0.1μF
0.1μF
0.01μF
VDDO_A
0.1μF
36Ω
Z0 = 50Ω
QA_C
ASIC
125MHz
MR
REF_IN
IN_SEL
QA
Z0 = 50Ω
QA
Z0 = 50Ω
ASIC
125MHz
QAC_OE
50Ω
50Ω
QA_OE
QB0_OE
VCC
(VCC - 2V)
QB1_OE
MAX3679A
BYPASS
QB0
Z0 = 50Ω
QB0
Z0 = 50Ω
ASIC
312.5MHz
SELA1
50Ω
SELA0
50Ω
SELB1
(VCC - 2V)
SELB0
RES1
QB1
Z0 = 50Ω
RES0
QB1
Z0 = 50Ω
X_OUT
X_IN
GND
25MHz
(CL = 18pF)
33pF
GNDO_A
ASIC
312.5MHz
50Ω
50Ω
(VCC - 2V)
27pF
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX3679A
General Description
MAX3679A
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA,
VDDO_A, VCCO_A, VCCO_B ................................-0.3V to +4.0V
Voltage Range at REF_IN, IN_SEL,
SELA[1:0], SELB[1:0], RES[1:0],
QAC_OE, QA_OE, QB0_OE, QB1_OE,
MR, BYPASS ..........................................-0.3V to (VCC + 0.3V)
Voltage Range at X_IN Pin ...................................-0.3V to +1.2V
Voltage Range at GNDO_A...................................-0.3V to +0.3V
Voltage Range at X_OUT ............................-0.3V to (VCC - 0.6V)
Current into QA_C ...........................................................±50mA
Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER
Power-Supply Current
SYMBOL
ICC
CONDITIONS
MIN
(Note 4)
TYP
MAX
UNITS
77
100
mA
CONTROL INPUT CHARACTERISTICS
(SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins)
Input Capacitance
Input Pulldown Resistor
Input Logic Bias Resistor
Input Pullup Resistor
CIN
RPULLDOWN Pin MR
RBIAS
RPULLUP
2
pF
75
k
Pins SELA[1:0], SELB[1:0], QB0_OE
50
k
Pins QAC_OE, QA_OE, QB1_OE, IN_SEL,
BYPASS
75
k
LVPECL OUTPUT SPECIFICATIONS (QA, QA, QB0, QB0, QB1, QB1 Pins)
Output High Voltage
Output Low Voltage
TA = 0°C to +85°C
VCC 1.13
TA = -40°C to 0°C
VCC 1.18
TA = 0°C to +85°C
VCC 1.85
TA = -40°C to 0°C
VCC 1.90
VOH
VOL
VCC 0.98
VCC 0.83
V
VCC 0.83
VCC 1.7
VCC 1.55
V
VCC 1.55
Peak-to-Peak Output-Voltage
Swing (Single-Ended)
(Note 2)
0.6
0.72
0.9
VP-P
Clock Output Rise/Fall Time
20% to 80% (Note 2)
200
350
600
ps
PLL enabled
48
50
52
PLL bypassed (Note 5)
40
50
60
Output Duty-Cycle Distortion
%
LVCMOS/LVTTL INPUT SPECIFICATIONS
(SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins)
Input-Voltage High
VIH
Input-Voltage Low
VIL
2
2.0
_______________________________________________________________________________________
V
0.8
V
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
Input High Current
I IH
VIN = VCC
Input Low Current
I IL
VIN = 0V
MIN
TYP
MAX
UNITS
80
μA
-80
μA
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
PLL enabled
Reference Clock Frequency
25
PLL bypassed
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input High Current
I IH
VIN = VCC
Input Low Current
I IL
VIN = 0V
Reference Clock Duty Cycle
320
2.0
PLL enabled
V
0.8
V
240
μA
-240
μA
30
Input Capacitance
MHz
70
2.5
%
pF
QA_C SPECIFICATIONS
Output High Voltage
VOH
QA_C sourcing 12mA
Output Low Voltage
VOL
QA_C sinking 12mA
Output Rise/Fall Time
(Notes 3, 6)
Output Duty-Cycle Distortion
2.6
V
0.4
V
ps
250
500
1000
PLL enabled
42
50
58
PLL bypassed (Note 5)
40
Output Impedance
60
%
14
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
Random Jitter (Note 7)
Deterministic Jitter Due to
Supply Noise
Spurs Induced by Power-Supply
Noise (Notes 7, 9, 10)
625
RJRMS
12kHz to 20MHz
0.36
1.875MHz to 20MHz
0.14
LVPECL output (Notes 7, 8, 9)
5.0
LVPECL output
-59
LVCMOS output
-47
Nonharmonic and Subharmonic
Spurs
Output Skew
Clock Output SSB Phase Noise
at 125MHz (Note 11)
Note 1:
-70
Between QB0 and QB1
15
Between QA and QB0 or QB1,
PECL outputs
20
f = 1kHz
-124
f = 10kHz
-125
f = 100kHz
-130
f = 1MHz
-145
f > 10MHz
-153
MHz
1.0
psRMS
psP-P
dBc
dBc
ps
dBc/Hz
A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply
tolerance is VCC = 3.3V ±5%. See Figure 2.
_______________________________________________________________________________________
3
MAX3679A
ELECTRICAL CHARACTERISTICS (continued)
MAX3679A
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, and 3)
Guaranteed up to 320MHz for LVPECL output.
Guaranteed up to 160MHz for LVCMOS output.
All outputs enabled and unloaded. IN_SEL set high.
Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN.
Measured using setup shown in Figure 1 with VCC = 3.3V ±5%.
Measured with crystal source.
Total TIE including random and deterministic jitter. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope
using 2M sample record length.
Note 9: Measured with 40mVP-P, 100kHz sinusoidal signal on the supply.
Note 10: Measured at 156.25MHz output.
Note 11: Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
36Ω
MAX3679A
499Ω
OSCILLOSCOPE
0.1μF
Z0 = 50Ω
QA_C
4.7pF
50Ω
Figure 1. LVCMOS Output Measurement Setup
4
_______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
SUPPLY CURRENT
vs. TEMPERATURE
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz (LVPECL OUTPUT)
MAX3679A toc03
MAX3679A toc02
MAX3679A toc01
250
175
ALL OUTPUTS ACTIVE AND TERMINATED
150
125
100
ALL OUTPUTS ACTIVE AND UNTERMINATED
75
AMPLITUDE (50mV/div)
200
MEASURED USING 50Ω OSCILLOSCOPE INPUT
THROUGH NETWORK SHOWN IN FIGURE 1
AMPLITUDE (200mV/div)
225
50
25
0
-15
10
35
60
85
1ns/div
1ns/div
AMBIENT TEMPERATURE (°C)
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY
-100
-110
-120
-130
-140
-150
MAX3679A toc05
-90
-80
NOISE POWER DENSITY (dBc/Hz)
-80
PHASE NOISE AT 125MHz
CLOCK FREQUENCY
MAX3679A toc04
-90
-100
-110
-120
-130
-140
-150
-160
-160
1
10
100
1000 10,000 100,000
0.1
OFFSET FREQUENCY (kHz)
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
JITTER HISTOGRAM (312.5MHz OUTPUT,
40mVP-P SUPPLY NOISE AT 100kHz)
NOISE SPUR AMPLITUDE
vs. NOISE FREQUENCY
MAX3679A toc06
0
fC = 156.25MHz
NOISE AMPLITUDE = 40mVP-P
-10
DJ = 5.0psP-P
-20
MAX3679A toc07
0.1
SPUR AMPLITUDE (dBc)
-40
NOISE POWER DENSITY (dBc/Hz)
SUPPLY CURRENT (mA)
OUTPUT WAVEFORM AT 125MHz
(LVCMOS OUTPUT)
-30
-40
-50
-60
-70
-80
-90
10
5ps/div
100
1000
10,000
NOISE FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX3679A
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25°C, crystal frequency = 25MHz.)
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
MAX3679A
Pin Description
6
PIN
NAME
1
VCCO_B
FUNCTION
2, 19, 24
GND
3
QB0_OE
LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high to enable LVPECL
clock output QB0. Connect low to set QB0 to a logic 0. Has internal 50k input impedance.
4, 5
SELB1,
SELB0
LVCMOS/LVTTL Input. Controls NB divider setting. Has 50k input impedance. See Table 2 for
more information.
6
QAC_OE
LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C.
Connect low to set QA_C to a high-impedance state. Has internal 75k pullup to VCC.
7
MR
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal
75k pulldown to GND. Not required for normal operation.
8
GNDO_A
9
QA_C
10
VDDO_A
Power Supply for QA_C Clock Output. Connect to +3.3V.
11
VCCO_A
Power Supply for QA Clock Output. Connect to +3.3V.
12
QA
Noninverting Clock Output, LVPECL
13
QA
Inverting Clock Output, LVPECL
14
BYPASS
15
RES1
Not Internally Connected. Connect to GND, VCC, or leave open for normal operation.
16
RES0
Reserved for Test. Connect to GND for normal operation.
17
VCCA
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering,
this pin can connect to VCC through 10.5 as shown in Figure 2 (requires VCC = +3.3V ±5%).
18
VCC
Core Power Supply. Connect to +3.3V.
20
QA_OE
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high to enable the
LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to VCC.
21, 22
SELA0,
SELA1
LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50k
input impedance.
23
QB1_OE
LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high to enable LVPECL
clock output QB1. Connect low to set QB1 to a logic 0. Has internal 50k input impedance.
25
X_OUT
26
X_IN
27
REF_IN
LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.
28
IN_SEL
LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN.
Has internal 75k pullup to VCC.
29
QB1
LVPECL, Inverting Clock Output
30
QB1
LVPECL, Noninverting Clock Output
31
QB0
LVPECL, Inverting Clock Output
32
QB0
LVPECL, Noninverting Clock Output
—
EP
Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V.
Supply Ground
Ground for QA_C Output. Connect to supply ground.
LVCMOS Clock Output
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high for
normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal
75k pullup to VCC.
Crystal Oscillator Output
Crystal Oscillator Input
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
_______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
The MAX3679A is a low-jitter clock generator designed
to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, programmable dividers,
LVCMOS output buffer, and LVPECL output buffers.
Using a low-frequency clock (crystal or CMOS input) as
a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance.
Crystal Oscillator
An integrated oscillator provides the low-frequency
reference clock for the PLL. This oscillator requires an
external crystal connected between X_IN and X_OUT.
Crystal frequency is 25MHz.
REF_IN Buffer
An LVCMOS-compatible clock source can be connected
to REF_IN to serve as the reference clock.
The LVCMOS REF_IN buffer is internally biased to allow
AC- or DC-coupling. It is designed to operate up to
320MHz.
PLL
The PLL takes the signal from the crystal oscillator or
reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency
detector (PFD), a lowpass filter, and a 625MHz voltagecontrolled oscillator (VCO). The VCO output is connected to the PFD input through a feedback divider. The
PFD compares the reference frequency to the divideddown VCO output (fVCO/25) and generates a control
signal that keeps the VCO locked to the reference
clock. The high-frequency VCO output clock is sent to
the output dividers. To minimize noise-induced jitter,
the VCO supply (VCCA) is isolated from the core logic
and output buffer supplies.
LVCMOS Driver
QA_C, the LVCMOS output, is designed to drive a single-ended high-impedance load. The maximum operating frequency is specified up to 160MHz. This output
can be disabled by the QAC_OE pin if not used and
goes to a high impedance when disabled.
Reset Logic/POR
During power-on, the power-on reset (POR) signal is
generated to synchronize all dividers. An external master reset (MR) signal is not required.
Applications Information
Power-Supply Filtering
The MAX3679A is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
In addition to excellent on-chip power-supply noise
rejection, the MAX3679A provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 2 illustrates the recommended power-supply filter network for
V CCA . The purpose of this design technique is to
ensure clean input power supply to the VCO circuitry
and to improve the overall immunity to power-supply
noise. This network requires that the power supply is
+3.3V ±5%. Decoupling capacitors should be used on
all other supply pins for best performance.
Output Divider Configuration
Table 2 shows the input settings required to set the output dividers. Leakage in the OPEN case must be less
than 1µA. Note that when the MAX3679A is in bypass
mode (BYPASS set low), the output dividers are automatically set to divide by 1.
Output Dividers
The output divider is programmable to allow a range of
output frequencies. See Table 2 for the divider input
settings. The output dividers are automatically set to
divide by 1 when the MAX3679A is in bypass mode
(BYPASS = 0).
+3.3V ±5%
VCC
0.1μF
10.5Ω
VCCA
LVPECL Drivers
The high-frequency outputs—QA, QB0, and QB1—are
differential PECL buffers designed to drive transmission
lines terminated with 50Ω to VCC - 2.0V. The maximum
operating frequency is specified up to 320MHz. Each
output can be individually disabled, if not used. The
outputs go to a logic 0 when disabled.
0.1μF
10μF
Figure 2. Analog Supply Filtering
_______________________________________________________________________________________
7
MAX3679A
Detailed Description
MAX3679A
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
Table 1. Output Frequency Determination
XO OR CMOS
INPUT
FREQUENCY
(MHz)
FEEDBACK
DIVIDER, M
25
25
VCO
FREQUENCY
(MHz)
625
Table 2. Output Divider Configuration
SELA0/SELB0
0
0
1
0
0
OUTPUT
FREQUENCY
(MHz)
÷2
312.5
÷4
156.25
÷5
125
÷10
62.5
1
OPEN
NA/NB DIVIDER
APPLICATIONS
Ethernet
Table 3. Crystal Selection Parameters
PARAMETER
INPUT
SELA1/SELB1
1
OUTPUT
DIVIDER,
NA AND NB
SYMBOL
MIN
TYP
f OSC
25
÷2*
Crystal Oscillation
Frequency
÷4
Shunt Capacitance
CO
2.0
÷5
Load Capacitance
CL
18
÷10
Equivalent Series
Resistance (ESR)
RS
*Maximum guaranteed output frequency is 160MHz for CMOS
and 320MHz for LVPECL output.
Maximum Crystal
Drive Level
MAX
UNITS
MHz
7.0
pF
pF
50
300
μW
27pF
X_IN
25MHz CRYSTAL
(CL = 18pF)
X_OUT
33pF
Figure 4. Crystal, Capacitors Connection
Crystal Input Layout and
Frequency Stability
Figure 3. Crystal Layout
Crystal Selection
The crystal oscillator is designed to drive a fundamental
mode, AT-cut crystal resonator. See Table 3 for recommended crystal specifications. See Figure 4 for external
capacitance connection.
8
The crystal, trace, and two external capacitors should
be placed on the board as close as possible to the
MAX3679A’s X_IN and X_OUT pins to reduce crosstalk
of active signals into the oscillator.
The layout shown in Figure 3 gives approximately 3pF
of trace plus footprint capacitors per side of the crystal
(Y1). The dielectric material is FR4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz
crystal and the capacitor values of C22 = 27pF and
C23 = 33pF, the measured output frequency accuracy
is -14ppm at +25°C ambient temperature.
_______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
Interface Models
+3.3V
130Ω
termination methods can be used such as shown in
Figures 5 and 6. Unused outputs should be disabled and
can be left open. For more information on LVPECL terminations and how to interface with other logic families,
refer to Application Note 291: HFAN-01.0: Introduction to
LVDS, PECL, and CML.
Figures 7, 8, and 9 show examples of interface models.
130Ω
VCC
MAX3679A Qx
Z0 = 50Ω
Qx
Z0 = 50Ω
HIGH
IMPEDANCE
82Ω
82Ω
Qx
Figure 5. Thevenin Equivalent of Standard PECL Termination
Qx
0.1μF
Z0 = 50Ω
Qx
100Ω
MAX3679A
0.1μF
HIGH
IMPEDANCE
ESD
STRUCTURES
Z0 = 50Ω
Qx
150Ω
150Ω
Figure 8. Simplified LVPECL Output Circuit Schematic
NOTE: AC-COUPLING IS OPTIONAL.
Figure 6. AC-Coupled PECL Termination
VDDO_A
VCC
DISABLE
VB = 1.4V
VCC
10Ω
VB
IN
QA_C
14.5kΩ
10Ω
VB
REF_IN
ESD
STRUCTURES
ESD
STRUCTURES
Figure 7. Simplified REF_IN Pin Circuit Schematic
Figure 9. Simplified LVCMOS Output Circuit Schematic
_______________________________________________________________________________________
9
MAX3679A
Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure 8.
These outputs are designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC - 2V. If a
separate termination voltage (VTT) is not available, other
Pin Configuration
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is also
electrical ground on the MAX3679A and must be soldered to the circuit board ground for proper electrical
performance.
10
QB1
IN_SEL
REF_IN
X_IN
X_OUT
31
QB1
32
30
29
28
27
26
25
1
SELB0
5
QAC_OE
6
MR
7
GNDO_A
8
MAX3679A
*EP
9
10
11
12
13
14
15
16
RES0
4
RES1
SELB1
BYPASS
3
QA
QB0_OE
QA
2
VCCO_A
GND
+
VDDO_A
VCCO_B
QB0
TOP VIEW
QB0
Layout Considerations
The inputs and outputs are critical paths for the
MAX3679A, and care should be taken to minimize discontinuities on these transmission line. Here are some
suggestions for maximizing the MAX3679A’s performance:
• An uninterrupted ground plane should be positioned beneath the clock I/Os.
• Ground pin vias should be placed close to the IC
and the input/output interfaces to allow a return
current path to the MAX3679A and the receive
devices.
• Supply decoupling capacitors should be placed
close to the MAX3679A supply pins.
• Maintain 100Ω differential (or 50Ω single-ended)
transmission line impedance out of the MAX3679A.
• Use good high-frequency layout techniques and a
multilayer board with an uninterrupted ground
plane to minimize EMI and crosstalk.
Refer to the MAX3679A Evaluation Kit for more information.
QA_C
MAX3679A
+3.3V, Low-Jitter Crystal to LVPECL
Clock Generator
24
GND
23
QB1_OE
22
SELA1
21
SELA0
20
QA_OE
19
GND
18
VCC
17
VCCA
THIN QFN
(5mm × 5mm)
*EXPOSED PAD CONNECTED TO GROUND.
Chip Information
TRANSISTOR COUNT: 10,780
PROCESS: BiCMOS
______________________________________________________________________________________
+3.3V, Low-Jitter Crystal to
LVPECL Clock Generator
BYPASS
IN_SEL
SELA[1:0]
QAC_OE
LVCMOS
BUFFER
QA_C
DIVIDER
NA
QA_OE
QA
LVPECL
BUFFER
0
REF_IN
25MHz
625MHz
PFD
27pF
FILTER
VCO
QB1_OE
1
CRYSTAL
OSCILLATOR
X_OUT
QB1
LVPECL
BUFFER
1
X_IN
QA
0
LVCMOS
QB1
DIVIDER
NB
÷25
QB0_OE
33pF
DIVIDERS:
NA = 2, 4, 5, 10
NB = 2, 4, 5, 10
QB0
LVPECL
BUFFER
QB0
MAX3679A
SELB[1:0]
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFN-EP
T3255+3
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX3679A
Block Diagram