Rev 0; 4/05 8-Channel Cold-Cathode Fluorescent Lamp Controller The DS3988 is an 8-channel controller for cold-cathode fluorescent lamps (CCFLs) used to backlight liquid crystal displays (LCDs) in TV and PC monitor applications. The DS3988 supports configurations of 1 to 8 lamps, and multiple DS3988 controllers can be cascaded to support applications requiring more than 8 lamps. Applications LCD Televisions LCD PC Monitors Ordering Information PART TEMP RANGE PIN-PACKAGE DS3988T -40°C to +85°C 48 TQFP DS3988T+ -40°C to +85°C 48 TQFP +Denotes lead-free package. Pin Configuration FAULT SCL SDA 37 38 39 40 41 42 43 GND POSC PSYNC A0 LOSC LSYNC 45 44 SVM BRIGHT 46 VCC 47 1 36 2 35 3 34 4 33 GA2 GB2 5 LCM2 OVD8 LCM8 32 GB8 GA8 OVD7 6 31 LCM7 7 30 OVD2 GA3 8 29 GB7 GA7 9 28 GB3 LCM3 10 27 11 26 OVD3 12 25 24 23 22 21 20 OVD6 LCM6 GB6 GA6 GB5 LCM5 OVD5 VCC GND 19 18 17 16 14 15 13 DS3988 GA4 GB4 LCM4 OVD4 GND GA5 ♦ Can Be Easily Cascaded to Support More Than 8 Lamps ♦ Minimal External Components ♦ Analog Brightness Control ♦ Per-Channel Lamp Control Ensures Equal Brightness Among Lamps and Maximizes Lamp Life ♦ Gate Driver Phasing Minimizes DC Supply Current Surges ♦ Per-Channel Lamp Fault Monitoring for Lamp Open, Lamp Overcurrent, Failure to Strike, and Overvoltage Conditions ♦ Accurate (±5%) Independent On-Board Oscillators for Lamp Frequency (40kHz to 80kHz) and DPWM Burst Dimming Frequency (22.5Hz to 440Hz) ♦ Can Be Synchronized to External Sources for the Lamp and DPWM Frequencies ♦ Programmable Soft-Start Minimizes Audible Transformer Noise GA1 GB1 LCM1 OVD1 GND ♦ High-Density CCFL Controller for LCD TV and PC Monitor Backlights ♦ <10% to 100% Dimming Range 48 TOP VIEW Features ♦ I2C-Compatible Serial Port and On-Board Nonvolatile (NV) Memory Allow Device Customization ♦ 8-Byte NV User Memory for Storage of Serial Numbers and Date Codes ♦ 4.5V to 5.5V Single-Supply Operation ♦ -40°C to +85°C Temperature Range ♦ 48-Lead TQFP (7mm x 7mm) Package I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 48-LEAD TQFP 7 x 7 x 1.0mm Typical Operating Circuit appears at end of data sheet. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3988 General Description DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller ABSOLUTE MAXIMUM RATINGS Voltage on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage on Leads Other than VCC, SDA, and SCL…………………………..-0.5V to (VCC + 0.5V), not to exceed +6.0V Operating Temperature Range ...........................-40°C to +85°C EEPROM Programming Temperature Range .........0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................See J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C.) PARAMETER SYMBOL MAX UNITS 4.5 5.5 V VIH 0.7 x VCC VCC + 0.3 V VIL -0.3 0.3 x VCC V VSVM -0.3 VCC + 0.3 V VBRIGHT -0.3 VCC + 0.3 V Supply Voltage VCC Input Logic 1 Input Logic 0 SVM Voltage Range BRIGHT Voltage Range CONDITIONS (Note 1) MIN TYP LCM Voltage Range VLCM (Note 2) -0.3 VCC + 0.3 V OVD Voltage Range VOVD (Note 2) -0.3 VCC + 0.3 V 20 nC TYP MAX UNITS 15 20 mA -1.0 +1.0 µA -1.0 +1.0 µA Gate-Driver Output Charge Loading QG ELECTRICAL CHARACTERISTICS (VCC = +4.5V to +5.5V, TA = -40°C to +85°C.) PARAMETER Supply Current Input Leakage (Digital Pins) Output Leakage (SDA, FAULT) SYMBOL ICC CONDITIONS GA, GB loaded with 600pF, 8 channels active IL ILO MIN High impedance VOL1 IOL1 = 3mA 0.4 VOL2 IOL2 = 6mA 0.6 Low-Level Output Voltage (PSYNC, LSYNC) VOL3 IOL3 = 4mA 0.4 V Low-Level Output Voltage (GA, GB) VOL4 IOL4 = 4mA 0.4 V High-Level Output Voltage (PSYNC, LSYNC) VOH1 IOH1 = -1mA Low-Level Output Voltage (SDA, Fault) 2 _____________________________________________________________________ VCC - 0.4 V V 8-Channel Cold-Cathode Fluorescent Lamp Controller (VCC = +4.5V to +5.5V, TA = -40°C to +85°C.) PARAMETER High-Level Output Voltage (GA, GB) SYMBOL VOH2 UVLO Threshold—VCC Rising VUVLOR UVLO Threshold—VCC Falling VUVLOF UVLO Hysteresis VUVLOH SVM Threshold VSVMT SVM Hysteresis VSVMH CONDITIONS IOH2 = -1mA MIN TYP MAX VCC - 0.4 V 4.3 3.7 V V 100 1.8 UNITS 2.0 mV 2.2 V 50 mV LCM and OVD Source Current 4 µA LCM and OVD Sink Current 4 µA 1.35 V LCM and OVD DC Bias Voltage VDCB LCM and OVD Input Resistance RDCB Lamp Off Threshold VLOT (Note 3) 0.3 0.4 0.5 V Lamp Overcurrent Threshold VLOC (Note 3) 1.8 2.0 2.2 V Lamp Regulation Threshold VLRT (Note 3) 0.9 1.0 1.1 V OVD Threshold VOVDT (Note 3) 0.9 1.0 1.1 V Lamp Frequency Range fLF:OSC 40 80 kHz Lamp Frequency Source Frequency Tolerance fLFS:TOL -5 +5 % 50 LOSC resistor ±2% over temperature kΩ Lamp Frequency Receiver Duty Cycle fLFR:DUTY 40 60 % DPWM Frequency Range fD:OSC 22.5 440.0 Hz DPWM Source Frequency Tolerance fDSR:TOL -5 +5 % DPWM Receiver Duty Cycle fDFE:DUTY 40 60 % DPWM Receiver Frequency Range fDR:OSC 22.5 440.0 Hz DPWM Receiver Minimum Pulse Width tDR:MIN BRIGHT Voltage—Minimum Brightness VBMIN BRIGHT Voltage—Maximum Brightness VBMAX Gate-Driver Output Rise/Fall Time GAn and GBn Duty Cycle tR/tF POSC resistor ±2% over temperature (Note 4) 25 µs 0.5 2.0 V V CL = 600pF 100 ns (Note 5) 44 % _____________________________________________________________________ 3 DS3988 ELECTRICAL CHARACTERISTICS (continued) DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller I2C AC ELECTRICAL CHARACTERISTICS (See Figure 9) (VCC = +4.5V to +5.5V, timing referenced to VIL(MAX) and VIH(MIN), TA = -40°C to +85°C.) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between Stop and Start Conditions tBUF Hold Time (Repeated) Start Condition tHD:STA CONDITIONS (Note 6) MIN TYP 0 (Note 7) MAX UNITS 400 kHz 1.3 µs 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 µs Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 0.9 µs ns Start Setup Time tSU:STA 0.6 µs SDA and SCL Rise Time tR (Note 8) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 8) 20 + 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 8) EEPROM Write Time tW (Note 9) µs 400 pF 20 30 ms TYP MAX UNITS NONVOLATILE MEMORY CHARACTERISTICS (VCC = +4.5V to +5.5V) PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS +70°C (Note 10) MIN 50,000 Cycles Note 1: All voltages are referenced to ground, unless otherwise noted. Currents into the IC are positive, out of the IC negative. Note 2: During fault conditions, the AC-coupled feedback values are allowed to be outside the Absolute Max Rating of the LCM or OVD pin for up to 1 second. Note 3: Voltage with respect to VDCB. Note 4: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3988’s minimum burst duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input is greater than the DS3988’s minimum duty cycle, the output’s duty cycle will track the PSYNC’s duty cycle. Leaving PSYNC low (0% duty cycle) disables the GAn and GBn outputs in DPWM Slave mode. Note 5: This is the maximum lamp frequency duty cycle that will be generated at any of the GAn or GBn outputs. Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 7: After this period, the first clock pulse can be generated. Note 8: CB—total capacitance allowed on one bus line in picofarads. Note 9: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs. Note 10: Guaranteed by design. 4 _____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller 15 DPWM = 50% 13 DPWM = 10% 11 9 17 16 15 14 13 DS3988 toc03 VCC = 5.0V 18 4 DS3988 toc02 VCC = 5.5V 3 FREQUENCY CHANGE (%) 17 VCC = 4.5V 19 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) DPWM = 100% 20 DS3988 toc01 fLF:OSC = 71kHz GATE QC = 3.5nC 19 INTERNAL FREQUENCY CHANGE vs. TEMPERATURE ACTIVE SUPPLY CURRENT vs. TEMPERATURE ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 2 LAMP FREQUENCY 1 0 -1 DPWM FREQUENCY -2 12 7 SVM = 0V fLF:OSC = 71kHz GATE QC = 3.5nC 11 -3 DPWM = 100% -4 10 5 4.7 4.9 5.1 5.3 -40 5.5 -15 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (°C) TYPICAL OPERATION AT 12V TYPICAL OPERATION AT 15V TYPICAL OPERATION AT 18V 10µs 5.0V GA 10µs 5.0V GA 10µs 5.0V GB 10µs 5.0V GB 10µs 5.0V GB 10µs 2.0V LCM 10µs 2.0V LCM 10µs 2.0V LCM 10µs 2.0V OVD 10µs 2.0V OVD 10µs 2.0V OVD BURST DIMMING AT 150Hz AND 10% 2ms 2.0V SVM 2ms 5.0V GB 2ms 2.0V LCM 2ms 2.0V OVD DS3988 toc07 TYPICAL STARTUP WITH SVM 1ms 5.0V GA DS3988 toc08 10µs 5.0V GA 85 DS3988 toc06 TEMPERATURE (°C) DS3988 toc05 SUPPLY VOLTAGE (V) DS3988 toc04 4.5 1ms 5.0V GB 1ms 2.0V LCM 1ms 2.0V OVD _____________________________________________________________________ 5 DS3988 Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) 1ms 5.0V GB 50µs 5.0V GB 1ms 5.0V GB 1ms 2.0V LCM 50µs 2.0V LCM 1ms 2.0V LCM 1ms 2.0V OVD 50µs 2.0V OVD 1ms 2.0V OVD LAMP STRIKE WITH OPEN LAMP AUTORETRY DISABLED 50ms 5.0V GA STAGGERED BURST DIMMING START DS3988 toc13 LAMP STRIKE WITH OPEN LAMP AUTORETRY ENABLED 50ms 5.0V GA 0.1ms 5.0V GA1 0.1ms 5.0V GA2 50ms 5.0V GB 50ms 5.0V GB 50ms 2.0V LCM 50ms 2.0V LCM 0.1ms 5.0V GA3 50ms 2.0V OVD 0.1ms 5.0V GA4 50ms 2.0V OVD LAMP-OUT (LAMP OPENED) AUTORETRY DISABLED 6 LAMP-OUT (LAMP OPENED) AUTORETRY ENABLED DS3988 toc15 0.5ms 5.0V GA DS3988 toc11 1ms 5.0V GA DS3988 toc14 50µs 5.0V GA 50ms 5.0V GA 0.5ms 5.0V GB 50ms 5.0V GB 0.5ms 2.0V LCM 50ms 2.0V LCM 0.5ms 2.0V OVD 50ms 2.0V OVD _____________________________________________________________________ DS3988 toc16 1ms 5.0V GA LAMP STRIKE—EXPANDED VIEW DS3988 toc10 SOFT-START AT VINV = 18V DS3988 toc09 BURST DIMMING AT 150Hz AND 50% DS3988 toc12 DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller 8-Channel Cold-Cathode Fluorescent Lamp Controller NAME PINS BY CHANNEL (n = 1–8) DESCRIPTION CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8 GAn 1 5 9 14 19 25 29 33 MOSFET A Gate Drive. Connect directly to logiclevel mode n-channel MOSFET. Leave open if channel is unused. GBn 2 6 10 15 20 26 30 34 MOSFET B Gate Drive. Connect directly to logiclevel mode n-channel MOSFET. Leave open if channel is unused. 35 Lamp Current Monitor Input. Lamp current is monitored by measuring a voltage across a resistor placed in series with the low-voltage side of the lamp. Leave open if channel is unused. 36 Overvoltage Detection. Lamp voltage is monitored through a capacitor-divider placed on the high-voltage side of the transformer. Leave open if channel is unused. LCMn 3 7 12 16 21 17 22 27 28 31 OVDn 4 NAME PIN GND 13, 18, 24, 45 Ground Connection VCC 23, 48 Power-Supply Connection SDA 37 Serial Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high logic levels. SCL 38 Serial Clock Input. I2C clock input. FAULT 39 Fault Output. Active-low, open-drain, requires external pullup resistor to realize high logic levels. 40 Lamp Frequency Input/Output. This pin is the input for an externally sourced lamp frequency when the DS3988 is configured as a lamp frequency receiver. If the DS3988 is configured as a lamp frequency source (i.e., the lamp frequency is generated internally), the frequency is output on this pin for use by other lamp frequency receiver DS3988s. LSYNC 8 11 32 DESCRIPTION LOSC 41 Lamp Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the lamp oscillator. A0 42 Address Select Input. Determines the DS3988’s I2C slave address. PSYNC 43 DPWM Input/Output. This pin is the input for an externally generated DPWM signal when the DS3988 is configured as a DPWM receiver. If the DS3988 is configured as a DPWM source (i.e., the DPWM signal is generated internally), the DPWM signal is output on this pin for use by other DPWM receiver DS3988s. POSC 44 DPWM Oscillator Resistor Adjust. A resistor to ground on this lead sets the frequency of the DPWM oscillator (dimming clock). This lead can optionally accept a 22.5Hz to 440Hz clock as the source timing for the internal DPWM signal. BRIGHT 46 Analog Brightness Control Input. Used to control DPWM dimming. Ground when using a PWM signal at PSYNC to control brightness. SVM 47 Supply Voltage Monitor Input. Used to monitor the inverter voltage for undervoltage conditions. _____________________________________________________________________ 7 DS3988 Pin Description 8-Channel Cold-Cathode Fluorescent Lamp Controller DS3988 Functional Diagram EEPROM I2C DEVICE CONFIGURATION PORT SDA SCL A0 I2CCOMPATIBLE INTERFACE UVLO CONTROL REGISTERS 8-BYTE USER MEMORY VCC [4.5V TO 5.5V] SYSTEM ENABLE/POR 2.0V SVM SUPPLY VOLTAGE MONITOR DS3988 FAULT CHANNEL FAULT FAULT HANDLING LFSS BIT AT CR1.2 LOSC LCMn LAMP CURRENT MONITOR 40kHz TO 80kHz LAMP FREQUENCY INPUT/OUTPUT LSYNC EXTERNAL RESISTOR LAMP FREQUENCY SET CHANNEL ENABLE x512 PLL 8-PHASE GENERATOR EIGHT INDEPENDENT CCFL CONTROLLERS 40kHz TO 80kHz OSCILLATOR (±5%) DPSS BIT AT CR1.3 DPWM SIGNAL INPUT/OUTPUT PSYNC MUX RGSO BIT AT CR1.4 0 1 MOSFET GATE GBn DRIVERS GAn 1 ANALOG BRIGHTNESS CONTROL BRIGHT MUX DPSS BIT AT CR1.3 DPWM SIGNAL 0 POSC 1 22.5Hz TO 440Hz OSCILLATOR (±5%) 8 OVDn OVERVOLTAGE DETECTION [20.48MHz TO 40.96MHz] 0 EXTERNAL RESISTOR DPWM FREQUENCY SET/ DPWM CLOCK INPUT [40kHz TO 80kHz] MUX POSCS BIT AT CR1.1 RAMP GENERATOR 22.5Hz TO 440Hz _____________________________________________________________________ GND 8-Channel Cold-Cathode Fluorescent Lamp Controller DS3988 1 OF 8 CHANNELS LAMP OUT 400mV CHANNEL ENABLE CHANNEL FAULT LAMP OVERCURRENT LSE BIT AT CR1.0 DPWM SIGNAL 512 x LAMP FREQUENCY [20.48MHz TO 40.96MHz] DS3988 256 LAMP CYCLE INTEGRATOR PEAK DETECT/ HOLD LCM LAMP CURRENT MONITOR PEAK DETECT OVD OVERVOLTAGE DETECTION 2.0V LAMP REGULATION DIGITAL CCFL CONTROLLER 1.0V 256 LAMP CYCLE INTEGRATOR PHASED LAMP FREQUENCY [40kHz TO 80kHz] OVERVOLTAGE 1.0V GATE DRIVERS GA GB MOSFET GATE DRIVERS Figure 1. Per Channel Logic Diagram Detailed Description The DS3988 uses a push-pull drive scheme to convert a DC voltage (5V to 24V) to the high-voltage (600VRMS to 1200VRMS) AC waveform that is required to power the CCFLs. The push-pull drive scheme uses a minimal number of external components, which reduces assembly cost and makes the printed circuit board (PC board) design easy to implement. The push-pull drive scheme also provides an efficient DC-to-AC conversion and produces near-sinusoidal waveforms. Each DS3988 channel drives two logic-level n-channel MOSFETs that are connected between the ends of a step-up transformer and ground (see Figure 1 and the Typical Operating Circuit). The transformer has a center tap on the primary side that is connected to a DC voltage supply. The DS3988 alternately turns on the two MOSFETs to create the high-voltage AC waveform on the secondary side. By varying the duration of the MOSFET turn-on times, the controller is able to accurately control the amount of current flowing through the CCFL. A resistor in series with the CCFL’s ground connection enables current monitoring. The voltage across this resistor is fed to the lamp current monitor (LCM) input on the DS3988. The DS3988 compares the peak resistor voltage against an internal reference voltage to determine the duty cycle for the MOSFET gates. Each CCFL receives independent current monitoring and control, which results in equal brightness across all of the lamps and maximizes the lamp’s brightness and lifetime. EEPROM Registers and I2C-Compatible Serial Interface The DS3988 uses an I2C-compatible serial interface for communication with the on-board EEPROM configuration registers and user memory. The configuration registers—four Soft-Start Profile registers (SSP1/2/3/4) and two Control Registers (CR1/2)—allow the user to customize many DS3988 parameters such as the soft-start ramp rate, the lamp and dimming frequency sources, fault-monitoring options, and channel enabling/disabling. The eight bytes of nonvolatile user memory can be used to store manufacturing data such as date codes, serial numbers, or product identification numbers. The device is shipped from the factory with the configuration registers programmed to a set of default configuration parameters. To inquire about custom factory programming, email [email protected]. _____________________________________________________________________ 9 DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Channel Phasing lamp frequency (40kHz to 80kHz) as shown in Figure 6. This part of the cycle is called the “burst” period because of the lamp frequency burst that occurs during this time. During the low period of the DPWM cycle, the controller disables the MOSFET gate drivers so the lamps are not driven. This causes the current to stop flowing in the lamps, but the time is short enough to keep the lamps from de-ionizing. Dimming is increased/ decreased by adjusting (i.e., modulating) the duty cycle of the DPWM signal. The DS3988 can generate its own DPWM signal internally (set DPSS = 0 in CR1), which can then be sourced to other DS3988s if required, or the DPWM signal can be supplied from an external source (set DPSS = 1 in CR1). The lamp-frequency MOSFET gate turn-on times are equally phased among the eight channels during the burst period. This reduces the inrush current that would result from all lamps switching simultaneously, and hence eases the design requirements for the DC supply. Figure 2 details how the eight channels are phased. Note that it is the lamp-frequency signals that are phased, NOT the DPWM signals. Lamp Dimming Control (DPWM) The DS3988 uses a digital pulse-width modulated (DPWM) signal (22.5Hz to 440Hz) to provide efficient and precise lamp dimming. During the high period of the DPWM cycle, the lamps are driven at the selected CHANNEL SEQUENCE 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 GA1 GB1 3 4 5 6 7 8 VARIABLE MOSFET GATE DUTY CYCLE GA2 GB2 GA3 GB3 GA4 GB4 GA5 GB5 GA6 GB6 GA7 GB7 GA8 GB8 MOSFET GATEDRIVE SIGNALS AT LAMP FREQUENCY Figure 2. Channel Phasing Detail 10 ____________________________________________________________________ DIMMING CLOCK (DPWM) FREQUENCY 8-Channel Cold-Cathode Fluorescent Lamp Controller 2.0V ANALOG DIMMING CONTROL VOLTAGE 0.5V DPWM SIGNAL BRIGHT PSYNC (OUTPUT) EXTERNAL DIMMING CLOCK 2.0V ANALOG DIMMING CONTROL VOLTAGE 0.5V DPWM SIGNAL 22.5Hz TO 440Hz BRIGHT PSYNC (OUTPUT) 22.5Hz TO 440Hz POSC RESISTOR TO SET THE DIMMING FREQUENCY POSC EXTERNAL DIMMING CLOCK 22.5Hz to 440Hz Figure 3. DPWM Source Configuration Options BRIGHT DPWM SIGNAL PSYNC (OUTPUT) 22.5Hz TO 440Hz POSC Figure 4. The DPWM Receiver Configuration To generate the DPWM signal internally, the DS3988 requires a clock (referred to as the dimming clock) to set the DPWM frequency. The user can supply the dimming clock by setting POSCS = 1 in CR1 and applying an external 22.5Hz to 440Hz signal at the POSC pin, or DS3988’s clock can be generated by the DS3988’s oscillator (set POSCS = 0 in CR1), in which case the frequency is set by an external resistor at the POSC pin. These two dimming clock options are shown in Figure 3. Regardless of whether the dimming clock is generated internally or sourced externally, the POSC1 and POSC2 bits in CR2 must be set to match the desired dimming clock frequency. When the DPWM signal is generated internally, its duty cycle (and, thus, the lamp brightness) is controlled by a user-applied analog voltage at the BRIGHT input. A BRIGHT voltage less than 0.5V will cause the DS3988 to operate with the minimum burst duty cycle, providing the lowest brightness setting, while any voltage greater than 2.0V will cause a 100% burst duty cycle (i.e., lamps always being driven), which provides the maximum brightness. For voltages between 0.5V and 2V the duty cycle will vary linearly between the minimum and 100%. The internally generated DPWM signal is available at the PSYNC I/O pin (set RGSO = 0 in CR1) for sourcing to other DS3988s, if any, in the circuit. This allows all DS3988s in the system to be synchronized to the same DPWM signal. The DS3988 that is generating the DPWM signal for other DS3988s in the system is referred to as the DPWM source. When the DPWM signal is provided by an external source, either from the PSYNC pin of another DS3988 or from some other user-generated source, it is input into the PSYNC I/O pin of the DS3988. In this mode, the BRIGHT and POSC inputs are disabled and should be grounded (see Figure 4). When multiple DS3988s are used in a design, DS3988s configured to use externally generated DPWM signals are referred to as DPWM receivers. Lamp Frequency Configuration The DS3988 can generate its own lamp frequency clock internally (set LFSS = 0 in CR1), which can then be sourced to other DS3988s if required, or the lamp clock can be supplied from an external source (set LFSS = 1 in CR1). When the lamp clock is internally generated, the frequency (40kHz to 80kHz) is set by an external resistor at the LOSC. In this case, the DS3988 can act as a lamp frequency source because the lamp clock is output at the LSYNC I/O pin for synchronizing any other DS3988s configured as lamp frequency receivers. The DS3988 acts as a lamp frequency receiver when the lamp clock is supplied externally. In this case, a 40kHz to 80kHz clock must be supplied at the LSYNC I/O. The external clock can originate from the LSYNC I/O of a DS3988 configured as a lamp frequency source or from some other source. ____________________________________________________________________ 11 DS3988 RESISTOR-SET DIMMING CLOCK DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller ANALOG BRIGHTNESS 2.0V 0.5V BRIGHT PSYNC RESISTOR-SET DIMMING FREQUENCY LSYNC POSC RESISTOR-SET LAMP FREQUENCY ANALOG BRIGHTNESS 0.5V ANALOG BRIGHTNESS RESISTOR-SET LAMP FREQUENCY LAMP FREQUENCY SOURCE DPWM SOURCE LAMP CLOCK (40kHz TO 80kHz) LSYNC POSC RESISTOR-SET DIMMING FREQUENCY BRIGHT PSYNC LAMP FREQUENCY RECEIVER DPWM SOURCE DS3988 DS3988 LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC LOSC ANALOG BRIGHTNESS 0.5V BRIGHT LSYNC POSC DS3988 LAMP FREQUENCY SOURCE DPWM SOURCE LOSC 2.0V LAMP CLOCK (40kHz TO 80kHz) DIMMING CLOCK (22.5Hz TO 440Hz) BRIGHT PSYNC LSYNC POSC DS3988 LAMP FREQUENCY RECEIVER DPWM SOURCE LOSC BRIGHT BRIGHT PSYNC DS3988 DS3988 LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC LOSC DPWM SIGNAL (22.5Hz TO 440Hz) BRIGHT PSYNC LSYNC POSC RESISTOR-SET LAMP FREQUENCY DS3988 LOSC BRIGHT PSYNC DPWM SIGNAL (22.5Hz TO 440Hz) BRIGHT PSYNC PSYNC PSYNC DIMMING CLOCK (22.5Hz TO 440Hz) DS3988 LOSC 2.0V 2.0V 0.5V DS3988 LAMP FREQUENCY SOURCE DPWM RECEIVER LAMP CLOCK (40kHz TO 80kHz) LSYNC POSC DS3988 LAMP FREQUENCY RECEIVER DPWM RECEIVER LOSC LOSC BRIGHT BRIGHT PSYNC BRIGHT PSYNC PSYNC DS3988 DS3988 LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LSYNC LAMP FREQUENCY RECEIVER POSC DPWM RECEIVER LOSC LOSC Figure 5. Frequency Configuration Options for Designs Using Multiple DS3988s Configuring Systems with Multiple DS3988s The source and receiver options for the lamp frequency clock and DPWM signal allow multiple DS3988s to be synchronized in systems requiring more than 8 lamps. The lamp and dimming clocks can either be generated 12 on board the DS3988 using external resistors to set the frequency, or they can be sourced by the host system to synchronize the DS3988 to other system resources. Figure 5 shows various multiple DS3988 configurations that allow both lamp and/or DPWM synchronization for all DS3988s in the system. ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller DS3988 DPWM SIGNAL 22.5Hz TO 440Hz LAMP CURRENT SOFT-START SOFT-START (EXPANDED) LAMP CYCLE GAn/GBn MOSFET GATE DRIVERS SOFT-START PROFILE REGISTER 1 2 3 4 SSP1. 4-7 SSP1. 0-3 5 6 SSP2. 0-3 7 8 SSP2. 4-7 9 10 SSP3. 0-3 11 12 SSP3. 4-7 13 14 SSP4. 0-3 15 16 SSP4. 4-7 PROGRAMMABLE SOFT-START PROFILE WITH INCREASING MOSFET PULSE WIDTHS OVER A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT. LAMP CURRENT Figure 6. Digital PWM Dimming and Soft-Start DPWM Soft-Start At the beginning of each lamp burst, the DS3988 provides a soft-start that slowly increases the MOSFET gate-driver duty cycle (see Figure 6). This minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. The soft-start length is fixed at 16 lamp cycles, but the soft-start ramp profile is programmable through the four Soft-Start Profile registers (SSP1/2/3/4) and can be adjusted to match the application. There are seven different driver duty cycles to select from to customize the soft-start ramp (see Table 1). The available duty cycles range from 0% to 19% in ~3% increments. In addition, the MOSFET duty cycle from the last lamp cycle of the previous burst can be used as part of the soft-start ramp by using the Most Recent Value duty-cycle code. Each programmed MOSFET gate duty cycle repeats twice to make up the 16 soft-start lamp cycles. ____________________________________________________________________ 13 DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Setting the Lamp and Dimming Clock (DPWM) Frequencies Using External Resistors Both the lamp and dimming clock frequencies can be set using external resistors. The resistance required for either frequency can be determined using the following formula: ROSC = VINV DS3988 R2 K fOSC SVM R1 where K = 1600kΩ•kHz for lamp frequency calculations. When calculating the resistor value for the dimming clock frequency, K will be one of four values as determined by the desired frequency and the POSCR0 and POSCR1 bit settings as shown in the Control Register 2 (CR2) table 4 in the Detailed Register Descriptions section. Example: Selecting the resistor values to configure a DS3988 to have a 50kHz lamp frequency and a 160Hz dimming clock frequency: For this configuration, POSCR0 and POSCR1 must be programmed to 1 and 0, respectively, to select 90Hz to 220Hz as the dimming clock frequency range. This sets K for the dimming clock resistor (RPOSC) calculation to 4kΩ•kHz. For the lamp frequency resistor (RLOSC) calculation, K = 1600kΩ•kHz, which allows the lamp frequency K value regardless of the frequency. The formula above can now be used to calculate the resistor values for RLOSC and RPOSC as follows: 1600kΩ • kHz = 32kΩ, 50kHz 4kΩ • kHz = 25.0kΩ RPOSC = 0.160kHz RLOSC = 2.0V EXAMPLE: R1 = 10kΩ, R2 = 40kΩ SETS AN SVM TRIP POINT OF 10V Figure 7. Setting the SVM Threshold Voltage problems. Proper use of the SVM can prevent these problems. If desired, the SVM can be disabled by connecting the SVM pin to VCC. R + R2 VTRIP = 2.0 1 R1 The VCC monitor is used as a 5V supply undervoltage lockout (UVLO) that prevents operation when the DS3988 does not have adequate voltage for its analog circuitry to operate or to drive the external MOSFETs. The VCC monitor features hysteresis to prevent VCC noise from causing spurious operation when VCC is near the trip point. This monitor cannot be disabled by any means. Fault Monitoring Supply Monitoring The DS3988 monitors both the transformer’s DC supply and its own VCC supply to ensure that both voltage levels are adequate for proper operation. The inverter’s transformer supply (VINV) is monitored using an external resistor-divider that is the input into a comparator (see Figure 7) with a 2V threshold. Using the equation below to determine the resistor values, the supply voltage monitor (SVM) trip point (VTRIP) can be customized to shut off the inverter when the transformer’s input voltage drops below any specified value. Operating with the transformer’s supply at too low of a level can prevent the inverter from reaching the strike voltage and could potentially cause numerous other 14 The DS3988 provides extensive fault monitoring for each channel. It can detect open-lamp, lamp overcurrent, failure to strike, and overvoltage conditions. The DS3988 can be configured to disable all channels if one or more channels enter a Fault State, or it can be configured to disable only the channel where the fault occurred. Once a Fault State has been entered, the FAULT output is asserted and the channel(s) remain disabled until either the DS3988 is power-cycled or the inverter’s DC supply is power-cycled. The DS3988 can also be configured to automatically attempt to clear a detected fault (except lamp overcurrent) by restriking the lamp, as explained in Step 4. Configuration bits for the fault monitoring options are located in CR1 and CR2. ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller 1) Supply Check—The lamps will not turn on unless the DS3988 supply voltage is ≥4.5V and the voltage at the supply voltage monitor (SVM) input is ≥2V. 2) Strike Lamp—When both the DS3988 and the DC inverter supplies are above the minimum values, the DS3988 will attempt to strike each enabled lamp for 768 lamp cycles [1 lamp cycle (seconds) = 1/lamp frequency (Hertz)]. If the lamp doesn’t strike during that time, the DS3988 will go into a fault-handling stage (step 4). The DS3988 detects that the lamp has struck by measuring the current flow through the lamp. Also, if an overvoltage event is detected during the strike attempt, the DS3988 will disable the MOSFET gate drivers and go to the fault-handling stage. If a lamp overcurrent is detected, the DS3988 will immediately enter a Fault State. 3) Run Lamp—Once the lamp is struck, the DS3988 adjusts the MOSFET gate duty cycle to optimize the lamp current. The lamp current sampling rate is userselectable with the LSR0 and LSR1 bits in CR2. If the lamp current ever drops below the Open Lamp reference point for 256 lamp cycles, the lamp is considered extinguished. If this occurs or if an overvoltage event is detected while the lamp is running, the DS3988 will disable the MOSFET gate drivers and go to the fault-handling stage. If a lamp overcurrent is detected, the DS3988 will immediately enter a Fault State. 4) Fault Handling—The DS3988 can be configured to automatically restrike the lamp(s) in an attempt to clear the detected fault condition (except for lamp overcurrent faults). The automatic retry will make up to 15 re-strike attempts before entering a Fault State. Between each of the 15 retries, the controller will wait 1024 lamp cycles. If after any of the retries the fault has cleared, normal operation will resume. In the case of a lamp overcurrent fault, the DS3988 will skip the automatic retry even if it is enabled and will immediately enter a Fault State. FAULT STATE [ACTIVATE FAULT OUTPUT] FAULT-HANDLING STAGE 4 1 DEVICE AND INVERTER SUPPLIES ABOVE MINIMUM LEVEL? YES YES RESET FAULT COUNTER AND FAULT OUTPUT FAULT WAIT [1024 LAMP CYCLES] NO NO YES FAULT COUNTER = 15? AUTORETRY ENABLED? [ARD BIT AT CR1.5] INCREMENT FAULT COUNTER 2 FAULT FAULT STRIKE LAMP LAMP STRIKE TIMEOUT [LAMP OUT FOR 768 LAMP CYCLES] FAULT OVERVOLTAGE [256 LAMP CYCLES] LAMP OVERCURRENT [INSTANTANEOUS RESPONSE IF ENABLED WITH THE LOC BIT AT CR1.0] LAMP STRIKES CORRECTLY FAULT FAULT RUN LAMP FAULT LAMP EXTINGUISHED [LAMP OUT FOR 256 LAMP CYCLES] 3 MOSFET GATE DRIVERS ENABLED Figure 8. Fault-Handling Flow Chart ____________________________________________________________________ 15 DS3988 Figure 8 shows a flowchart of how the DS3988 controls and monitors each lamp. The steps are as follows: DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Detailed Register Descriptions The DS3988’s Register Map is shown in Table 1. Detailed register and bit descriptions follow in the subsequent tables. Soft-Start Profile (SSPx) Registers—Each of the four soft-start profile registers (SSP1–4) contains two 4-bit codes that determine the MOSFET’s duty cycle (MDC) for two clock cycles each (see Figure 6) at the beginning of each DPWM burst. Table 2 shows the duty cycles that correspond to each code. Selecting the Most Recent Value instructs the DS3988 to use the MOSFET duty cycle that was used for the last lamp cycle of the previous burst. Table 2. MOSFET Duty Cycle (MDC) Codes for Soft-Start Settings MDC CODE (BINARY)* MOSFET DUTY CYCLE X000 Fixed at 0% X001 Fixed at 3% X010 Fixed at 6% X011 Fixed at 9% X100 Fixed at 13% X101 Fixed at 16% X110 Fixed at 19% X111 Most Recent Value *The most significant bit of each MDC code is ignored. Table 1. Register Map BYTE ADDRESS BYTE NAME FACTORY DEFAULT* BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 1 BIT 0 F0h SSP1 21h MDC code for soft-start lamp cycles 3, 4 MDC code for soft-start lamp cycles 1, 2 F1h SSP2 43h MDC code for soft-start lamp cycles 7, 8 MDC code for soft-start lamp cycles 5, 6 F2h SSP3 65h MDC code for soft-start lamp cycles 11, 12 MDC code for soft-start lamp cycles 9, 10 F3h SSP4 77h MDC code for soft-start lamp cycles 15, 16 MDC code for soft-start lamp cycles 13, 14 F4h CR1 00h DPD FRS ARD RGSO DPSS LFSS POSCS LOC F5h CR2 08h LD2 LD1 LD0 LSR1 LSR0 POSCR1 POSCR0 UMWP F6h CR3 00h F7h F8-FFh Reserved User Memory Do not modify. If it has been modified, restore to all zeros. — — — — — — — — — 00h EE EE EE EE EE EE EE EE *All the configuration settings are saved in nonvolatile (EEPROM) memory. 16 BIT 2 ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller DS3988 Table 3. Control Register 1 (CR1) BIT 0 1 NAME LOC FUNCTION Lamp Overcurrent. 0 = Lamp overcurrent detection disabled. 1 = Lamp overcurrent detection enabled. Note: Gate duty cycle changes during soft-start larger than 5% can cause false LOC fault. POSC Select. See POSCR0 and POSCR1 bits in Control Register 2 to select the oscillator range. POSCS 0 = Connect POSC to ground with a resistor to set the dimming frequency. 1 = Connect POSC to an external 22.5Hz to 440Hz dimming clock to set the dimming frequency. 2 LFSS Lamp Frequency Source Select. 0 = Lamp frequency source mode. The lamp frequency is generated internally and sourced at the LSYNC output for use by lamp frequency receivers. 1 = Lamp frequency receiver mode. The lamp frequency must be provided at the LSYNC input. 3 DPSS DPWM Signal Source Select. 0 = DPWM source mode. DPWM signal is generated internally, and can be output at PSYNC pin (see RGSO bit). 1 = DPWM receiver mode. DPWM signal is generated externally and supplied at the PSYNC input. 4 RGSO Ramp Generator Source Option. 0 = Sources DPWM at the PSYNC output. 1 = Sources the internal ramp generator at PSYNC output. 5 ARD Autoretry Disable. 0 = Autoretry function enabled. 1 = Autoretry function disabled. 6 FRS Fault Response Select. 0 = Disable only the malfunctioning channel. 1 = Disable all channels upon fault detection at any channel. 7 DPD DPWM Disable. 0 = DPWM function enabled. 1 = DPWM function disabled. DPWM set to 100% duty cycle. ____________________________________________________________________ 17 DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Table 4. Control Register 2 (CR2) BIT NAME 0 UMWP 1 POSCR0 2 FUNCTION User Memory Write Protect. 0 = User Memory Write Access Blocked 1 = User Memory Write Access Permitted DPWM Oscillator Range Select. When using an external source for the dimming clock, these bits must be set to match the external oscillator’s frequency. When using a resistor to set the dimming frequency, these bits plus the external resistor control the frequency. POSCR1 POSCR0 DIMMING CLOCK (DPWM) FREQUENCY RANGE (Hz) K (kΩ • kHz) 0 0 22.5 to 55.0 1 0 1 45 to 110 2 1 0 90 to 220 4 1 1 180 to 440 8 POSCR1 Lamp Sample Rate Select. Determines the feedback sample rate of the LCM inputs 3 4 LSR0 LSR1 LSR1 LSR0 SELECTED LAMP SAMPLE RATE EXAMPLE SAMPLE RATE IF LAMP FREQUENCY IS 50kHZ 0 0 4 Lamp Frequency Cycles 12500Hz 0 1 8 Lamp Frequency Cycles 6250Hz 1 0 16 Lamp Frequency Cycles 3125Hz 1 1 32 Lamp Frequency Cycles 1563Hz Lamp Disable. Used to disable channels if all 8 are not required for an application. 5 6 7 18 LD0 LD1 LD2 LD2 LD1 LD0 CHANNELS DISABLED NUMBER OF ACTIVE LAMP CHANNELS 0 0 0 All Channels Enabled 8 0 0 1 8 7 0 1 0 4/8 6 0 1 1 2/4/8 5 1 0 0 2/4/6/8 4 1 0 1 2/4/6/7/8 3 1 1 0 2/3/4/6/7/8 2 1 1 1 2/3/4/5/6/7/8 1 ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a nor- mal start condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 9). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 9) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 9) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 9. I2C Timing Diagram ____________________________________________________________________ 19 DS3988 I2C Definitions The following terminology is commonly used to describe I2C data transfers. DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte (Figure 10) contains the slave address in the most significant seven bits and the R/W bit in the least significant bit. The DS3988’s slave address is 101000A0 (binary), where A 0 is the value of the address pin (A 0). The address pin allows the device to respond to one of two possible slave addresses. By writing the correct slave address with R/W = 0, the master writes data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the DS3988 will assume the master is communicating with another I2C device and ignore the communications until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. 20 7-BIT SLAVE ADDRESS 1 MOST SIGNIFICANT BIT 0 1 0 0 0 A0 R/W A0 PIN VALUE DETERMINES READ OR WRITE Figure 10. DS3988’s Slave Address Byte I2C Communication Writing a Data Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. See Figure 11 for more detail. Acknowledge Polling: Any time EEPROM is written, the DS3988 requires the EEPROM write time (tW) after the stop condition to write the contents to EEPROM. During the EEPROM write time, the DS3988 will not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the DS3988, which allows the next byte of data to be written as soon as the DS3988 is ready to receive the data. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to write again to the DS3988. EEPROM Write Cycles: The number of times the DS3988’s EEPROM can be written before it fails is specified in the Nonvolatile Memory Characteristics table. This specification is shown at the worst-case write temperature. The DS3988 is typically capable of handling many additional write cycles when the writes are performed at room temperature. Reading a Data Byte from a Slave: To read a single byte from the slave the master generates a start condition, writes the slave address byte with R/W = 0, writes the memory address, generates a repeated start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. See Figure 11 for more detail. ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller DS3988 NOTES COMMUNICATIONS KEY S START A ACK WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA P STOP N NOT ACK SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA SR REPEATED START X X X X X X X X 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. 8-BITS ADDRESS OR DATA WRITE A SINGLE BYTE S 1 0 1 0 A0 0 A MEMORY ADDRESS A 0 A0 0 A MEMORY ADDRESS A 0 0 A DATA P READ A SINGLE BYTE S 1 0 1 0 0 SR 1 0 1 0 0 0 A0 0 A DATA N P Figure 11. I2C Communications Examples Applications Information Addressing Multiple DS3988s On a Common I2C Bus Each DS3988 responds to one of two possible slave addresses based on the state of the address input (A0). For information about device addressing see the I2C Communications section. Power-Supply Decoupling To achieve best results, it is recommended that each VCC pin is decoupled with a 0.01µF or a 0.1µF capacitor to GND. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize trace inductance. Setting the RMS Lamp Current Resistor R8 in the typical operating circuit (Figure 12) sets the lamp current. R8 = 140Ω corresponds to a 5mARMS lamp current as long as the current waveform is approximately sinusoidal. The formula to determine the resistor value for a given sinusoidal lamp current is: R8 = 1 2 × ILAMP(RMS) Component Selection External component selection has a large impact on the overall system performance and cost. The two most important external components are the transformers and n-channel MOSFETs. The transformer should be able to operate in the 40kHz to 80kHz frequency range of the DS3988, and the turns ratio should be selected so the MOSFET drivers run at 28% to 35% duty cycle during steady state operation. The transformer must be able to withstand the high open-circuit voltage that will be used to strike the lamp. Additionally, its primary/secondary resistance and inductance characteristics must be considered because they contribute significantly to determining the efficiency and transient response of the system. Table 5 shows a transformer specification that has been utilized for a 12V inverter supply, 438mm x 2.2mm lamp design. The n-channel MOSFET must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the nchannel MOSFET’s power dissipation, and a breakdown voltage high enough to handle the transient. The breakdown voltage should be a minimum of 3x the inverter voltage supply. Additionally, the total gate charge must be less than QG, which is specified in the Recommended DC Operating Conditions table. These specifications are easily met by many of the dual nchannel MOSFETs now available in SO-8 packages. Table 6 lists suggested values for the external resistors and capacitors used in the typical operating circuit. ____________________________________________________________________ 21 DS3988 8-Channel Cold-Cathode Fluorescent Lamp Controller Table 5. Transformer Specifications PARAMETER CONDITIONS Turns Ratio (Secondary/Primary) MIN (Notes 11, 12, 13) TYP MAX UNITS 80 kHz 6 W 40 Frequency 40 Output Power Output Current 5 Primary DCR Center tap to one end Secondary DCR 8 mA 200 mΩ 500 Ω Primary Leakage 12 µH Secondary Leakage 185 mH Primary Inductance 70 µH Secondary Inductance 500 mH Center Tap Voltage 10.8 Secondary Output Voltage 100ms minimum 2000 Continuous 1000 12 13.2 V VRMS Note 11: Primary should be Bifilar wound with center tap connection. Note 12: Turns ratio is defined as secondary winding divided by the sum of both primary windings. Note 13: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12V supply. Refer to AN3375 for more information. Table 6. Resistor and Capacitor Selection Guide 25°C TEMPERATURE TOLERANCE COEFFICIENT (%) DESIGNATOR QTY VALUE R1 1 10kΩ 1 — — R2 1 12.5kΩ to 105kΩ 1 — See the Setting the SVM Threshold Voltage section. R3 1 20kΩ to 40kΩ 1 ≤153ppm/°C 2% or less total tolerance. See the Lamp Frequency Configuration section to determine value. R4 1 18kΩ to 45kΩ 1 ≤153ppm/°C 2% or less total tolerance. See the Lamp Frequency Configuration section to determine value. R5 1 4.7kΩ 5 Any grade — R6 1 4.7kΩ 5 Any grade — R7 1 4.7kΩ 5 Any grade — R8 1/Ch 140Ω 1 — C1 1/Ch 100nF 10 X7R C2 1/Ch 10pF 5 ±1000ppm/°C C3 1/Ch 27nF 5 X7R 22 C4 1/Ch 33µF 20 Any grade C5 2/DS3988 0.1µF 10 X7R NOTES See the Setting the RMS Lamp Current section. Capacitor value will also affect LCM Bias voltage during power-up. A larger capacitor may cause a longer time for VDCB to reach its normal operating point. 2kV to 4kV breakdown voltage required. Capacitor value will also affect LCM Bias voltage during power-up. A larger capacitor may cause a longer time for VDCB to reach its normal operating point. — Place close to VCC and GND on DS3988. ____________________________________________________________________ 8-Channel Cold-Cathode Fluorescent Lamp Controller SUPPLY VOLTAGE (5V ±10%) C5 ANALOG BRIGHTNESS BRIGHT VCC EXTERNAL DIGITAL PWM INPUT/ INTERNAL DIGITAL PWM OUTPUT PSYNC SVM EXTERNAL LAMP FREQUENCY INPUT/ INTERNAL LAMP FREQUENCY OUTPUT LSYNC SUPPLY VOLTAGE (5V ±10% TO 24V ±10%) C4 R2 R1 DUAL POWER MOSFET TRANSFORMER LOSC CCFL LAMP GAn C2 C3 DS3988 POSC R8 GBn VCC R3 R4 R5 R6 R7 LAMP VOLTAGE MONITOR OVDn FAULT LAMP CURRENT MONITOR LCMn CONFIGURATION PORT SDA C1 SCL GND A0 SEE NOTES 14, 15. Figure 12. Typical Operating Circuit Note 14: Only one channel shown to simplify drawing. Note 15: See the Component Selection section for recommended external components. Chip Information TRANSISTOR COUNT: 70,200 SUBSTRATE CONNECTED TO: Ground Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. DS3988 Typical Operating Circuit