ON Semiconductor BCP68T1 NPN Silicon Epitaxial Transistor ON Semiconductor Preferred Device MEDIUM POWER NPN SILICON HIGH CURRENT TRANSISTOR SURFACE MOUNT This NPN Silicon Epitaxial Transistor is designed for use in low voltage, high current applications. The device is housed in the SOT-223 package, which is designed for medium power surface mount applications. • High Current: IC = 1.0 Amp • The SOT-223 Package can be soldered using wave or reflow. • SOT-223 package ensures level mounting, resulting in improved thermal conduction, and allows visual inspection of soldered joints. The formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die • Available in 12 mm Tape and Reel Use BCP68T1 to order the 7 inch/1000 unit reel. Use BCP68T3 to order the 13 inch/4000 unit reel. • The PNP Complement is BCP69T1 4 1 2 3 CASE 318E-04, STYLE 1 TO-261AA COLLECTOR 2,4 BASE 1 EMITTER 3 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter Voltage VCEO 25 Vdc Collector-Base Voltage VCBO 20 Vdc Emitter-Base Voltage VEBO 5 Vdc Collector Current IC 1 Adc Total Power Dissipation @ TA = 25°C(1) Derate above 25°C PD 1.5 12 Watts mW/°C TJ, Tstg –65 to 150 °C Symbol Max Unit RθJA 83.3 °C/W TL 260 10 °C Sec Operating and Storage Temperature Range DEVICE MARKING CA THERMAL CHARACTERISTICS Characteristic Thermal Resistance — Junction-to-Ambient (surface mounted) Maximum Temperature for Soldering Purposes Time in Solder Bath 1. Device mounted on a FR-4 glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.0625 in.; mounting pad for the collector lead = 0.93 sq. in. Preferred devices are ON Semiconductor recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 November, 2001 – Rev. 3 1 Publication Order Number: BCP68T1/D BCP68T1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristics Symbol Min Typ Max Unit Collector-Emitter Breakdown Voltage (IC = 100 µAdc, IE = 0) V(BR)CES 25 — — Vdc Collector-Emitter Breakdown Voltage (IC = 1.0 mAdc, IB = 0) V(BR)CEO 20 — — Vdc Emitter-Base Breakdown Voltage (IE = 10 µAdc, IC = 0) V(BR)EBO 5.0 — — Vdc Collector-Base Cutoff Current (VCB = 25 Vdc, IE = 0) ICBO — — 10 µAdc Emitter-Base Cutoff Current (VEB = 5.0 Vdc, IC = 0) IEBO — — 10 µAdc 50 85 60 — — — — 375 — OFF CHARACTERISTICS ON CHARACTERISTICS (2) DC Current Gain (IC = 5.0 mAdc, VCE = 10 Vdc) (IC = 500 mAdc, VCE = 1.0 Vdc) (IC = 1.0 Adc, VCE = 1.0 Vdc) hFE — Collector-Emitter Saturation Voltage (IC = 1.0 Adc, IB = 100 mAdc) VCE(sat) — — 0.5 Vdc Base-Emitter On Voltage (IC = 1.0 Adc, VCE = 1.0 Vdc) VBE(on) — — 1.0 Vdc fT — 60 — MHz DYNAMIC CHARACTERISTICS Current-Gain — Bandwidth Product (IC = 10 mAdc, VCE = 5.0 Vdc) 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% 300 200 100 f, T CURRENTGAINBANDWIDTH PRODUCT (MHz) hFE, DC CURRENT GAIN TYPICAL ELECTRICAL CHARACTERISTICS TJ = 125°C = 25°C = -55°C VCE = 1.0 V 10 1.0 10 100 IC, COLLECTOR CURRENT (mA) 1000 300 200 100 70 VCE = 10 V TJ = 25°C f = 30 MHz 50 30 10 Figure 1. DC Current Gain 100 200 IC, COLLECTOR CURRENT (mA) Figure 2. Current-Gain-Bandwidth Product http://onsemi.com 2 1000 BCP68T1 TYPICAL ELECTRICAL CHARACTERISTICS 80 TJ = 25°C 0.8 VBE(sat) @ IC/IB = 10 0.6 VBE(on) @ VCE = 1.0 V TJ = 25°C Cib, CAPACITANCE (pF) V, VOLTAGE (VOLTS) 1.0 0.4 0.2 0 60 50 40 VCE(sat) @ IC/IB = 10 1.0 70 30 10 100 1000 IC, COLLECTOR CURRENT (mA) 0 1.0 Figure 3. “On” Voltage RθVB, TEMPERATURE COEFFICIENT (mV/°C) 20 15 10 5.0 10 15 VR, REVERSE VOLTAGE (VOLTS) 20 -0.8 -1.2 -1.6 RθVB for VBE -2.0 -2.4 -2.8 1.0 Figure 5. Capacitance 10 100 IC, COLLECTOR CURRENT (mA) TJ = 25°C 0.8 0.6 0.4 = 1000 mA I C = 10 mA = 100 mA = 50 mA 0.2 0 0.01 1000 Figure 6. Base-Emitter Temperature Coefficient 1.0 VCE , COLLECTOR VOLTAGE (V) Cob, CAPACITANCE (pF) TJ = 25°C 0 5.0 Figure 4. Capacitance 25 5.0 2.0 3.0 4.0 VR, REVERSE VOLTAGE (VOLTS) = 500 mA 0.1 1.0 10 IB, BASE CURRENT (mA) Figure 7. Saturation Region http://onsemi.com 3 100 BCP68T1 INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection 0.15 3.8 0.079 2.0 SOT–223 0.091 2.3 0.248 6.3 0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 mm inches SOT–223 POWER DISSIPATION PD = TJ(max) – TA RθJA Board Material = 0.0625″ G10/FR4, 2 oz Copper 140 TA = 25°C 0.8 Watts 1.25 Watts* 1.5 Watts 100 θ 150°C – 25°C 83.3°C/W 160 ° 120 The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 1.5 watts. PD = doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RθJA versus collector pad area is shown in Figure 8. R JA , Thermal Resistance, Junction to Ambient (C/W) The power dissipation of the SOT–223 is a function of the pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SOT–223 package, PD can be calculated as follows. 80 0.0 = 1.50 watts *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 Figure 8. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical) The 83.3°C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 4 BCP68T1 SOLDER STENCIL GUIDELINES The stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. SOLDERING PRECAUTIONS • The soldering temperature and time should not exceed The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10°C. 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient should be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 7 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. http://onsemi.com 5 BCP68T1 STEP 1 PREHEAT ZONE 1 RAMP" 200°C 150°C STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" 205° TO 219°C PEAK AT SOLDER JOINT 170°C 160°C 150°C 140°C 100°C 100°C 50°C STEP 6 STEP 7 VENT COOLING SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES TMAX TIME (3 TO 7 MINUTES TOTAL) Figure 9. Typical Solder Heating Profile http://onsemi.com 6 BCP68T1 PACKAGE DIMENSIONS SOT–223 (TO–261) CASE 318E–04 ISSUE K A F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 S 1 2 3 B D L G J C 0.08 (0003) H M K STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR http://onsemi.com 7 INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0 10 S 0.264 0.287 MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0 10 6.70 7.30 BCP68T1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 BCP68T1/D