XR-T7295E
...the analog plus company
TM
) (
APPLICATIONS
FEATURES
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GENERAL DESCRIPTION
16 (1#' ,*++)
, 6 & !+ + & ! !<+ +
16 * 56 6 (1# 1& - Figure 10 = 16 * 6 + * )
!!+" ! 6 ,, ) >6
* ) ++!5 ,! , &!* !, ,+ +!
! ,! * 56 * + 6 &!! ++ Figure 1
6!5 6 +!2 & !, 6 16 ! 6 ,*! !, .*+/!
!
!+" *!&( !!+ 7 " +!2(!)
&" +!(!,(+ +!(!,(,.*)(
+!2 ! 16 + )& , *+(+"
56 ! *
!+ + + ! !*
* + 16
!(6
.*+/ ,! + +! !, ! '
16 (1#' &*,* ) * +
0- 6!+!) 16 (1#' ++ 6
(
+ ;4 ! (
+ -0? 2 ,!
*, &!* !&
+ ! ++
,! ;- ! -1-( +! 4+ , ! 6
(1#' 6
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
(1#'(4
+ 4;4
(
! @'
(1#'(A
? + ?; -0?
(
! @'
!
!!" # $! !" %&!" ' ' (# % ' (##
XR-T7295E
BLOCK DIAGRAM
4% 4% 3;; 78; 3;;; 78;; 3;;
C=
*!
8
7 B
.*+/
!!
%+
46
;
-+
'
3 0
4;1
' 8;1
42
;!
+!
0-
;+
!
;!
%.*) 46
.*! *
7
+!
0-
.*+/
1* 2
#
1
1 1 $ 0
Figure 1. Block Diagram
$
&
0-1>
78;
#
0-
XR-T7295E
PIN CONFIGURATION
78;
8
1 4%
4%
1 00
78;;
78;
#
'
'
#
78;
8
1 4%
4%
1 00
78;;
78;
3;;
0-1>
C=
1
4;1
8;1
$
$
3;;
3;;;
#
'
'
#
3;;
0-1>
C=
1
4;1
8;1
$
$
3;;
3;;;
20 Lead PDIP (0.300”)
20 Lead SOJ (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
78;
Type
Description
8
Receive Input. 9+ +! *
"
1 (1 Test Mode Control 1 and 2. + &! + 56 6 ) *
1 1 9 &* 6 ! 6 !* +
"'
4%(4%
PLL Filter 1 and 2. <+ ! % ± D ! 5 6
- Figure 3 #
0-
0
Receive Loss-of-Signal. 16 66 ! +! !, + 6 *
0
0
Receive PLL Loss-of-Lock. 16 66 ! +! !, 4 ,.*) +!2
78;;
Digital Ground for PLL Clock. 7!* + ,! ++ *) * )6!!*+) 56
4 +!2
78;
Digital Ground for EXCLK. 7!* + ,! ++ *) * )6!!*+) 56
$
3;;;
5V Digital Supply (± 10%) for PLL Clock. 4!5 ,! ++ *) * )6!!*+)
56 4 +!2
3;;
5V Digital Supply (± 10%) for EXCLK. 4!5 ,! ++ *) * )6!!*+) 56
$
Analog Ground.
$
External Reference Clock. + >/ ± & +!2 &* !
6 * 16 *) )+ !, $" , ! 3;;: ++" &* D(D
$
0
Receive Clock. ! +!2 + ! 6 &+ .*
&
'
8;1
0
Receive Negative Data. 8 *+ !*
* ! 6 &+ .*
&
4;1
0
Receive Positive Data. 4! *+ !*
* ! 6 &+ .*
&
#
1
Output In-Circuit Test Control (Active-Low). , 1 ,! +!5" ++ + !*
* $" 4;1" 8;1" 0-" 0 + 66(&
! ++!5
,! (* C=
Receive Equalization Bypass. 66 ! 6 ) 6 + .*+/ +!5
+ 6 .*+/ 6 6
0-1>
Loss-of-Signal Threshold Control. 16 !+ ,! ! 6 !!+ 6 *
+!(!,(+ 66!+ 16 ! ) ,! 78;" 3;;:" ! 3;; 0-1>
3;;
5 V Analog Supply (± 10%).
XR-T7295E
DC ELECTRICAL CHARACTERISTICS
Test Conditions: -40C TA +85C, VDD = 5V ± 10%
Typical values are for VDD = 5.0V, 25C, and random data. Maximum values for VDD = 5.5V at 85C all 1s
data.
Symbol
Parameter
Min.
Typ.
Max.
Unit
#
&
&
78;;
3;;;
('
'
3;;;
3
3
78;;
3;;;
('
3;;;
3
3
%
Conditions
Electrical Characteristics
;;
4!5 -*
+) *
C=E
C=E
Logical Interface Characteristics
3
3>
* 3!+
!5
>6
30
30>
0*
* 3!+
!5
>6
* ! * 2
%
(
('
'
('
&
('&
'&
(' ! 3;; @'3 ++ * <
#
3 #
3;; 78; Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
4!5 ;
! #&A
4!5 -*
+) ('3 ! @'3
-! 1&
* ( ! @'
3!+ ) 4 ('3 ! 3;; @'3
<&*& ++!5+ 3!+ 8
56 ! 78; ('3 ! @'3
XR-T7295E
-)& -)& =
= ( '=
(1#'
(1#
1&
(1#
1&
(1#'
#'
!<+ +
Figure 2. Application Diagram
)
++) % -0? 2 % ;4
2
SYSTEM DESCRIPTION
Receive Path Configurations
16 & Figure 2 6!5 )
+ )&
+! ,! 6 (1#' 6 + 6 Figure 1" 6 + .*+/ +* ) C=E ! )
) C=E 16 .*+/ )
!
! ++!5 )
, !, 6 (1#' ! )& +)
! <+ .*+/ Figure 3 ++* 6
6 !
! ,! 5! Pulse Mask at the 34.368 Mbps Interface
Table 2 6!5 6 *+ ,! 6 &
!*
* ! Figure 4 6!5 6 *+ &2
.*& ,! !&& 7#
Minimum Signal
" 6 + ,!& 6 !<+ + , +)
! 6 8 * 6 &!" 6 * 6!*+ C=E " 6 .*+/ 6 6 , 6
+ +! 6 = , 6 + +! + 6
=" 6 .*+/ )
) C=E
REQB
LOSTHR
SOJ2
DIP
'
&3 2
3;;:
'
&3 2
3;;
&3 2
" <+ + .*+/ 5!2
6 (1#' 6 &!" 6 +
8 +) .*+/" 6 !(6
.*+/
6!*+ )
) C= E !6 " 6 + 8 &* & 6 &
+*
+& Table 1
Unit3
'
&3 2
3;;:
'
&3 2
3;;
'
&3 2
Notes
1Maximum input amplitude under all conditions is 1.1 Vpk
2The SOJ device performance is enhanced by decreased
package parasitics.
3Although system designers typically use power in dBm to
describe input levels, the XR-T7295E responds to peak input
signal amplitude. Therefore, the XR-T7295E input signal
limits are given in mV pk.
16 !&& &! +! 6!5 Figure 3 16 #' ! & 6 !<+ +
56 6 &
Figure 3 " ,
6 ,< .*+/ +* 6 + &!" 6 #'
! ! .* 16 + !*
+ 6!*6
6 % ! ! 8 16 ; 8 ++) 16 * 6 8 Table 1. Receive Input Signal Amplitude
Requirements’
'
XR-T7295E
Line Termination and Input Capacitance
External Loop Filter Capacitor
16 !&& &! 6!5 Figure 3 16 #' ! & 6 !<+ +
56 6 &
16 % !
! 8 !*
+ 6 + ! 6 * 56!*
* 6 ++) ; ++ ! 8 16 * 6 8 % -0?
2 % ;4 2
Figure 3 6!5 6 !! ! <+ %
! 6 4%:4% 16 ! !,
6 4 ,+ !(
!+/" +!5(+2 !
6!*+ * & ! 56 6 +* %
± D +
(' ,
- F
;
C=
%
8
#'
- F
XR-T7295
4%
%
4%
<
0,,(6
85!2
(' ,
;
C=
%
%<
.*+/
' ,
=0
-
%
8
#'
4%
4%
XR-T7295
+! ,!
'G' ,
!, +
Figure 3. Receiver Configuration
!& H ! $ * !, H ! 6
!& + 16 < ! * 6 H
, 6" 566 6 +!6
5 * !*
* H -!" ! !*
56 6 (1#' ! ! !* 6 !*
+ ! 6 6!*6 6 !5 *
+ TIMING RECOVERY
Output Jitter
16 !+ H ! 6 $ !*
* *
!&+ !
! ! !, 5! !&
! %"
XR-T7295E
H ! $ 16 &* !, 6 ++)
H ,*! !, 6 4 56" 566
* ,*! !, 6 * ) %! 66 " 6 &!* !, H 7 H +! ! 6 .*+) !, 6 !5
*
+) )
5!2 * Figure 8 6!5 6
* )
5!2" Table 3 + 6
)
+ H ,!& 6+ 56 6
5!2
#
'' @ '
3
'
'' ( '
8!&+ *+
''
'
'' ( '
'
'' @ '
'' @ ''
11('
Figure 4. Pulse Mask at the 34.368 Mbit/s Interface
Parameter
Value
4*+ -6
8!&++) *+
++ &2 !, + + &* !,!& 56 6 &2 Figure 4" !, 6 4 6 ;!
0 !<+ 4
1 ! &
#' 8!&+ 42 3!+ !, 2 4*+
3
42 3!+ !, -
8! 4*+
3 ± 3
8!&+ 4*+ A6
''
! !, 6 &
+* !, 4! 8 4*+ 6 !, 4*+ +
' ! '
! !, 6 A6 !, 4! 8 4*+ 6
8!&+ >+, &
+*
' ! '
Table 2. E3 Pulse Specification at the Transmitter Output Port
#
XR-T7295E
Jitter Transfer Characteristic
Jitter Accommodation
16 H , 6 6 ,! !,
* H 6 6 6 $ !*
* ,*! !,
* H ,.*) Table 3 6!5 &
! H
, 6 & Figure 6 +! 6!5
)
+ 6" 56 6 !
!! Table 3 +6!*6 !*& !
! ,) H , 6 .*&" 6
(1#' ,!&! ! 6 ! +*! !, 6 9 ++ ++!5+ !
!!" 6 H
!&&!! !, 6 (1#' < 6
+& ,! !(, !
! = I ( 16 )
+
3;; E '3" 1 E ' " !&+ + ++ H
!&&!! !, 6 6!5 Figure 6
7 ?
++ ++(
Typ.
Max.
Unit
2(!(
2
'
2(!(
2
Magnitude Response (dB)
Parameter
? 1,
6
42
'
, =
=
'
2>/
4$ E '=
(
(
(
,= E ' 2>/
(
('
Notes
1Repetitive input data pattern at nominal E3 level with V
DD = 5V
TA = 25C.
2Repetitive 1000 input at nominal E3 level with V
DD = 5V, TA =
25C.
'
'$ $
'$ $
Frequency (Hz)
Figure 5. Typical PLL Jitter Transfer
Characteristics
Table 3. Generated Jitter and Jitter Transfer
Characteristics
Peak•to•Peak Jitter Amplitude (UI)
$
'
11 7 -$
4
'
''
4=G
#
'
2
2
2
'2 2 2 2 2 Jitter Frequency (Hz)
Figure 6. Lower Limit of Maximum Tolerable Input Jitter at 34.368 Mbit/s
'$
XR-T7295E
False-Lock Immunity
Data
Rate
%+(+!2 , 6 !! 56 4
! +!2 ! + 6(+!2 ,.*)
! .*+ ! 6 !& 16 (1#'
* !&! ,.*):
6(+!2
6* ! ,+(+!2 !(6
,.*)
!&
! !*!*+) !&
6 $ ,
! 6 4 +!2 , 6 ,.*) ,, 5 6
$ 4 +!2 < !<&+) ± 'D !,
$" !! *) ! ,! (.*! !,
6 !
,.*) 6
Threshold
REQB
LOSTHR
Unit
Min.
Max.
&3 2
3;;:
'
&3 2
3;;
'
&3 2
'
#'
&3 2
3;;:
'
&3 2
3;;
#
&3 2
Notes
• The RLOS alarm is an indication of the presence of an input
signal, not a bit error rate indication. Table 1 gives the
minimum input amplitude needed for error-free operation
(BER<1E -9). Independent of the RLOS state, the device will
attempt to recover correct timing and data.
• The RLOS low-to-high transition typically occurs 1dB below
the high-to-low transition.
Acquisition Time
Table 4. Analog Loss-of-Signal Thresholds
, + * + *& ! +) 8" 6 &<&*& & 5 6 +! !, !5 !(, !
! & , !5 6
+) +" 6 + 5 6 +!
!, + !(, !
! &
Loss-of-Signal Detection
Figure 1 6!5 6 +! + &6! !,
+!(!,(+ 0- ! !& ! 6
0- +& !*
* 0- , 6 6 +! !
+ ! *) 0- 6 !*
Analog Detection
Loss-of-Lock Indication
16 +! 0- ! &!! 6 2 * +
&
+* 0- &2 66(!(+!5 ! *
+ 56 6 * + &
+* <
6 +!(!, + 66!+ , Table 4 16 0+!5(!(66 ! * + +! !* ++
)
++) = +!5 6 66(!(+!5 ! ++ 16
6) 0- 6 0 " 6
0- +& & 66 ,! + +!2 )+"
++!5 ,! )& ! !, 0- !! 56!*
6 * !, <+ +& +6
!" 6 4 .*! *) &!!
6 4 +!2 ,.*) + ! 6 $ ,.*)
16 .*! * +! &!! 6 *& !
!+ 6(+!2 566 !* !, !&+
6 +& 16 0 +& , 6 !
!6 !, 6 ,!++!5 !! <F
( 16 ,, 5 6 4 +!2 6
$ %.*) < !<&+) ± 'D
( 16 & !* !, !&+ 6
+&
66 0 !*
* 6 6 .*! * 5!2 ! 6 4 ! !
,.*) +!2
0 & 66 *+ ,.*) +!2 6 !*J
6!5" 6 &&*& 0 *+ 56 +!2
)+
1! ++!5 ,! ) ++ !, ! !+2 ,, +!" 6 +!(!,(+ 66!+
++ * 6 0-1> -
0-1> E 3;; ! 6 +!5 +!(!,(+
66!+J 0-1> E 3;; : !* * 5!
'2 ± D ! !+ 5 3;;;
78;; ! &
66!+
0-1> E 78; ! 6 66 66!+ 16
0-1> &* ! +* !5 *
&* ! 6 * !
!
XR-T7295E
4=(
!! ,
@
4=(
= &<
*!
0 3!+
4!!
+
!
;!
(1#'
! =
# 2>/
Figure 7. Test Set-Up for Interference Immunity Requirements
Digital Detection
! ! 6 + &
+* &!! !, 6
+! 0- !" 6 + 0- ! &!!
6 ! ) 16 0- +& !
66 , ± ! &! !* !* 6
& 16 +& ! +!5 56 +
6 !* !, !* 16
6) &&/ 0- 6 * &&*& 0- *+ 56 !, +!2 )+
Parameter
Min.
Typ.
*!
(
(
Max.
Unit
=
Table 5. Interference Requirement
Interference Immunity
16 (1#' !&
+ 56 6 , + 6 Figure 7 Table 5 16 5! ! !()6!!*
Note
RLOS chatter can still occur. When REQB = 1, input signal
levels above the analog LOS threshold can still be low enough to
result in a high bit error rate. The resultant data stream
(containing errors) can temporarily activate the digital LOS
detector, and RLOS chatter can occur. Therefore, RLOS should
not be used as a bit error rate monitor. RLOS chatter can also
occur when RLOL is activated (high).
In-Circuit Test Capability
A6 *++ +!5" 6 1 ,! ++ + !*
*
*,, $" 4;1" 8;1" 0-" 0 !
+ 66 !*
* &
16 ,*
++!5 (* ! ! ! 6! 56!* ! ,! (1#' *,, &
A6 ,! 66" 6 1 ! ! ,, !
! + *++(*
!&++) ' 2 ! ! 6 J 6,!" * + 6 !
,! !&+ !
! 16 6 !+) ,! 566
+ *++(*
:
*++(!5 !
Phase Hits
! ! 6 6 6 * " 6
(1#' * ! !(, !
! + 6
&
;* 6 .*! &" 0- &)
&
!+) BOARD LAYOUT CONSIDERATIONS
Recovered Clock and Data Timing
Power Supply Bypassing
Table 6 Figure 9 *&&/ 6 & +!6
5 6 66(
+! + $" 4;1"
8;1 ++ *) )+ & +!6
, ! 3;;: 66!+ ++ 4;1 8;1 6 ! 6 !, $ +
* 6 ,++ !, $ ! *+ 8
66 ++ ! 4;1 +!5 ++ !
8;1 *+ 66 ++ !
8;1 +!5 ++ ! 4;1" /!
!* +!5 ++ ! !6 4;1 8;1
Figure 8 ++* 6 !&& !5 *
+)
)
5!2 % ! )
6
+ *
+ 16 +! *
+) 3;; )
)
* % ! 6+ 6 &!
, &!* !, 66(,.*) ! )
6 )& ) 6 +! 7!! .*+)"
66(,.*) +!5 + * ! 6!*+
* %++)" &! &
! 6 ++ !*
!! & ! +!5(&
!* +
XR-T7295E
Receive Input
16 !! ! 6 * " 8" &* ,*++) ! 8!(!*
+ &* &&/
+! 6 6 ,!& 6 + 6 ! ! 6
* ) ! !*
+ ! 6 (1#' *
+) 6 +(!(! ! !, 6 *
+
%
3;;
78;
XR-T7295E
- 8!
-6+ =
PLL Filter Capacitor
78;;
3;;
78;
3;;;
%
16 4 ,+ ! 5 4% 4%
&* + +! ! 6 6
!+ 16 4%
4% H" ++!5 ,! 6! +
+6 56 ! !! ! 6 <+ !
8!(!*
+ ! 6 4% 4% &)
4 ,!&
@'3
Note
Recommended shield beads are the Fair•Rite 2643000101
or the Fair•Rite 2743019446 (surface mount).
Handling Precautions
+6!*6 !! *) 6 ! 6
" !
*! 6!*+ 2 ! !
<
!* ! +! 6 -; *
6+ &!*
Figure 8. Recommended Power Supply
Bypassing Network
COMPLIANCE SPECIFICATIONS
!&
+ 56 CCITT Recommendations G.703,
G.775 and G.824" XR-T7295E
TIMING CHARACTERISTICS
Test Conditions: All timing characteristics are measured with 10pF loading, -40C TA +85C,
VDD = 5V ± 10%
Symbol
Parameter
Min.
Typ.
Max.
Unit
> >
+!2 1& D(D
'
+!2 %++ 1& D(D
'
;3 ; -(9
1&
''
;
; >!+ 1&
'
>;3
4!
! ;+) +!2 ;*) )+
'
'
#
''
D
Note
1 The total delay from R to the digital outputs RPDATA and RNDATA is three RCLK clocks.
IN
Table 6. System Interface Timing Characteristics (See Figure 9)
>;3
$
;3 4;1
0
8;1
;
;
Figure 9. Timing Diagram for System Interface
> >
XR-T7295E
3
OUTPUTS
RECEIVER
MONITOR
014
C 1
=
' # -
-A ;4(
0
8491
-78
=
#
0-1>
C=
1:
$
8;1
4;1
0
08
#'
#
#
$
8;1
4;1
'
'
'
$0
=1
%1 =;
40-
1 $
87
8K
18;1
187
#
14;1
%
87
14
78;;
4
;0
3
=43
#
%
; 0;-
#
$0
40-
'
87
RECEIVER
OUTPUTS
8K
@ %
TRANSMITER
MONITOR
OUTPUTS
=
1
;0
78;
=43
3
;
;
3
;
;
;
=1
'
#
#
187
4'
18-%0 L 49- 87887
4 '
4 '# 8 -9% 0981
%
4
3
%1 =; L % 1 %1 =;
%
Figure 10. Evaluation System Schematic
114
14;1
114
%
#
004
004
1:
1013
1
8 0;-
18;1
=
'
=
3 3
; ;
; ;
;
1 $
4%
3
;
;
-
'
-A ;4(
='
78;;
'
'
78;
78;
%
'
4
78;
4%
004
;-"-1-(::
10 1:
13
8 0;; 0;-
1 $
' 004
%
1 $
U2
XR-T7296
#
'
#'
18
0 $
=
' # $
U2
XR-T7295
3
' #
14
0
1
>
@
%
'
%
1
XR-T7295E
20 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
E1
E
D
A2
Seating
Plane
A
L
A1
B
B1
e
MILLIMETERS
INCHES
SYMBOL
eA
eB
MIN
MAX
MIN
MAX
'
'
'
#
#
'
'
'
=
'
#
#
#
;
'
'
'
#
#
=
=-
' =-
=-
# =-
=
##
'
'
'
Note: The control dimension is the inch column
C
XR-T7295E
20 LEAD SMALL OUTLINE J LEAD
(300 MIL JEDEC SOJ)
Rev. 1.00
D
E
H
A2
A
Seating
Plane
B
e
C
A1
R
E1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
'
'
'
(((
(((
'
'
=
'
;
'
#
#
#
'
' =-
MIN
MAX
# =-
>
'
#
'
#
Note: The control dimension is the inch column
'
XR-T7295E
801 !
!! 6 6 ! &2 6 ! 6 !* ! 6 *+! ! ! &(
! " ,!& ! ++) !
!! *& ! !+) ,! 6 * !, ) * (
6" !) ! + * ) ! !6 6" &2 ! ! 6 6 * , !, ,& 6 6*+ ! 6 !+) ,! ++*! *
! &) )
*
! *M , +! A6+ 6 ,!&! 6 *+! 6 ,*++) 62J
! !+)" 6!5" *& ,! *
!
!! ! ! !&& 6 * !, ) !, !* +, *
! +! 56 6 ,+* !
&+,*! !, 6 !* !+) <
! * ,+* !, 6 +, *
! )& ! ! ,+)
,, ,) ! ,, 4!* ! *6!/ ,! * *6 +! *+ !
!!
" 5" * ! ,! 6F 6 2 !, H*) ! & 6 &&/J 6
* *& ++ *6 2J !+ ++) !, !
!! .*+) ! * 6 *&(
!
)6 !
!!
;6 ) !*!" ! 56!+" 56!* 6 ! 5 ! !, !
!! !6