19-5115; Rev 1; 2/10 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions The MAX5968 soft-switch and ideal diode controller protects systems with redundant DC-DC converter modules against failure of the converter by controlling external n-channel MOSFETs at the input and output of the converter. Input short-circuit and overload current protection is provided by means of a current-sense amplifier connected to a sense resistor that resides at the source of the external protection MOSFET. If a failure occurs at the input of the associated converter, the MAX5968 protects the input supply by pulling the gate of the input protection MOSFET low and disconnecting the failed converter. Similarly, if there is a failure at the output of the redundant converter, the MAX5968 detects the reverse potential across the output MOSFET and pulls the gate low to disconnect the failed converter from the load. The MAX5968 features VariableSpeed/BiLevelK input circuit-breaker protection. The MAX5968 also integrates a 10-bit ADC that monitors converter input current, load voltage, and output MOSFET forward voltage. An analog input (ADCIN) is provided to monitor a temperature signal from the associated converter. The MAX5968 features two 10-bit circular buffers that contain a history of the 50 most recent input current and output load voltage digital conversion results. This data helps to diagnose and troubleshoot converter failures. All ADC results, including circular buffers and several configuration registers are accessible through a 400kHz I2C interface. Features S 10-Bit ADC for Temperature, Voltage, Output MOSFET Forward Voltage, and Input Current Monitoring S Circular Buffers Store 50 Most Recent Voltage and Current Values for Fault Transient Analysis S Input Circuit-Breaker Controller Drives External Low-Side n-Channel MOSFET S Output Reverse-Current Protection Controller Drives Parallel External n-Channel MOSFETs S Programmable VariableSpeed/BiLevel Fault Protection Provides Electronic Circuit-Breaker Function S Internal 4A Pulldown Current for Fast Shutdown of the Circuit Breaker S Internal 600mW Gate Drive for Fast On-Off Control of the ORing FETs S Minimum- and Maximum-Value Detection Registers for All Digitized Signals S Two GPIO Pins S 400kHz I2C Interface S Small, 5mm x 5mm, 28-Pin TQFN Package Applications Redundant DC-DC Converter Protection Digital limits for overvoltage and undervoltage warning are user programmable. An ALERT output notifies the system controller of any failure condition that arises or requires attention. When any of the measured signals violates digitally programmable limits, the ALERT output is asserted. Servers High-Reliability Systems A precision ON comparator input can be used to implement programmable undervoltage lockout for the input and output MOSFET drivers. An open-drain READY output can be used to enable the associated DC-DC converter by releasing the converter’s enable input when both the input and output MOSFETs are fully enhanced. Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5968ATI+ -40NC to +125NC 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Two general-purpose I/Os can be fully configured through the I2C interface to provide external indications or to control additional peripheral devices. The MAX5968 is available in a 28-pin thin QFN package and operates over the -40NC to +125NC temperature range. VariableSpeed/BiLevel is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5968 General Description MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions ABSOLUTE MAXIMUM RATINGS ADCIN, INM to AGND............................................-0.3V to +60V PWR to AGND........................................................-0.3V to +16V READY, ALERT to AGND.......................... -0.3V to (VDD + 0.3V) VDD, REG, SCL, SDA to AGND...............................-0.3V to +6V GOR to AGND..........................................-0.3V to (VREG + 0.3V) ON, GPS to AGND.................................. -0.3V to (VPWR + 0.3V) OUT, DOR, SOR, CB+, CB-, A1, A0, GPIO1, GPIO2 to AGND........................ -0.3V to (VDD + 0.3V) CB+ to CB -.................................................................-1V to +1V GPS to CB+.............................-0.3V to +8V (internally clamped) DOR to SOR..........................................................-0.3V to +3.3V PGND, DGND, OUTM to AGND............................-0.3V to +0.3V SDA, ALERT, READY, GPIO1, GPIO2 Current...-1mA to +100mA Input/Output Current (all other pins).................. +20mA (Note 1) Continuous Power Dissipation (TA = +70NC) 28-Pin TQFN (derate 34.5mW/NC above +70NC).....2758.6mW Thermal Resistance, BJA (Note 2)....................................29NC/W Thermal Resistance, BJC (Note 2)......................................2NC/W Operating Temperature Range......................... -40NC to +125NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: During GPS/GOR pulldown, GPS, GOR, REG, AGND, and PGND could carry 1.5A to 7A transient current for several microseconds. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VPWR = 12V, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL Operating Voltage Range VPWR Undervoltage Lockout VUVLO Undervoltage Lockout Hysteresis VUVLO_HYS CONDITIONS MIN TYP 9 Minimum voltage on VPWR to ensure operation, VPWR rising 7.9 VPWR falling Supply Current IPWR fSCL = 400kHz REG Regulator Output Voltage VREG With 5mA load 8.4 MAX UNITS 14 V 8.9 V 500 4.5 mV 3.5 6 mA 4.8 5.0 V REG Undervoltage Lockout VREGUV 3.5 V REG Undervoltage Lockout Hysteresis VREGUV_HYS 500 mV VDD Regulator Output Voltage VDD VDD Power-On Reset VPOR 3.5 V VPOR_HYS 500 mV VDD Power-On Reset Hysteresis Internal Oscillator Frequency fINT With 5mA load 4.5 3.6 5 4.0 5.5 V 4.4 MHz 1 %FS ANALOG-TO-DIGITAL CONVERTER Resolution 10 Total Unadjusted Error Integral Nonlinearity INL Differential Nonlinearity DNL Bits 1 LSB 1 LSB Offset Error -5 +5 LSB DC Gain Error -7 +7 LSB 2 _______________________________________________________________________________________ Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions (VPWR = 12V, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN ADC Total Monitoring Cycle Time ADCIN Input Full-Scale Voltage Conversion = 1023, LSB = 4.88mV ADCIN Measurement Accuracy ADCIN to INM OUT Full-Scale Voltage OUTM Leakage Current IOUT IOUTM OUT Measurement Accuracy VCB+ - VCB- Full-Scale Voltage Input Bias Current 300 MAX Fs 5 V 500 LV_range = 0, conversion = 1023, LSB = 1.955mV 2 LV_range = 1, conversion = 1023, LSB = 3.910mV 4 +7 LSB 700 kI V VOUT = 2.0V 10 25 40 VOUT = 4.0V 50 100 150 VOUT = 4.0V, VOUTM = 0V -150 -100 -50 VOUT = 2.0V, VOUTM = 0V -40 -25 -10 LV_range = 0 -7 +7 LV_range = 1 -7 +7 At code = 1023 40 At code = 0 -10 VCB+ = 40mV, VCB- = 0V 5 2 ICB- VCB+ = 40mV, VCB- = 0V 5 2 Input Current Measurement Accuracy VDOR - VSOR Range Voltage VDOR - VSOR Measurement Accuracy -1.2 FA FA LSB mV ICB+ VCB+ = 0V, VCB- = 0V, TA = -40°C to +25°C UNITS 100 -7 ADCIN Input Resistance OUT Leakage Current TYP FA +1.2 VCB+ = 0V, VCB- = 0V, TA = +25°C to +125°C -0.6 +0.6 VCB- = 0V, VCB+ = 5mV -1.2 +1.2 VCB- = 0V, VCB+ = 20mV -1.2 mV +1.2 At code = 1023 -40 At code = 0 10 mV VSOR = 0V, VDOR = -20mV -1.2 +1.2 VSOR = 0V, VDOR = -5mV -1.2 +1.2 mV SOR Input Bias Current ISOR VSOR = 0mV, VDOR = -40mV 2 5 FA DOR Input Bias Current IDOR VSOR = 0mV, VDOR = -40mV 2 5 FA Code = 255 40 INPUT CIRCUIT-BREAKER PROTECTION Fast Comparator Threshold Full Scale Circuit-Breaker Accuracy (Slow Comparator) VOS,CB_S VCB- = 0V, code = 191 or 15mV (typ) input referred, full scale = 200% -2.7 VCB- = 0V, code = 102 or 8mV (typ) input referred, full scale = 200% -2.7 mV +2.7 mV +2.7 _______________________________________________________________________________________ 3 MAX5968 ELECTRICAL CHARACTERISTICS (continued) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions ELECTRICAL CHARACTERISTICS (continued) (VPWR = 12V, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) Circuit-Breaker Accuracy (Fast Comparator) PARAMETER VOS,CB_F VCB- = 0V, code = 191 or 30mV (typ) input referred, full scale = 200% -1.5 +1.5 VCB- = 0V, code = 102 or 16mV (typ) input referred, full scale = 200% -1.0 +1.0 SYMBOL Fast Comparator Threshold Programming Resolution CONDITIONS mV MIN DAC resolution Slow Circuit-Breaker Response Time tSCD Fast Circuit-Breaker Response Time tFCD TYP MAX 8 VCB+ - VCB- = VTH,SC + 2mV 2.4 VCB+ - VCB- = VTH,SC + 4mV 1.2 VCB+ - VCB- = VTH,FC + 10mV 0.1 UNITS Bits ms Fs OUTPUT REVERSE-CURRENT PROTECTION Reverse-Current Detection Threshold VRCD VDOR relative to VSOR (when GOR turns off) 2.9 4 4.9 mV Forward-Current Detection Threshold VFCD VDOR relative to VSOR (when GOR turns on) 1 2 3.5 mV GOR Off Threshold Hysteresis VHCD Reverse-Current Blocking Response Time tRCD 2 mV VDOR - VSOR = VRCD + 1mV, CGOR = 10nF 2 Fs VDOR - VSOR = VRCD + 10mV, CGOR = 10nF 100 ns OUTPUT UNDERVOLTAGE FAST COMPARATOR (OUT) OUT UV Comparator Threshold VTHUVDAC OUT UV Comparator Threshold Programming Resolution LV_range = 0, code = 127 0.79 0.8 0.81 LV_range = 1, code = 127 1.58 1.6 1.62 DAC resolution OUT UV Comparator Propagation Delay tOUT With 10mV overdrive V 8 Bits 100 ns ON COMPARATOR INPUT (ON) ON Input Threshold VTHON ON Input Hysteresis Rising 1.209 Falling ON Input Current 1.228 -1 ION 1.246 62.5 V mV +1 FA INPUT MOSFET GATE DRIVE (GPS) GPS High Voltage VGPSH Relative to AGND 6.5 8 9.6 V GPS High Comparator Threshold VTHGPS VGPS - VCB+ 4.9 5 5.1 V 45 50 55 FA 2.5 A I GPS Pullup Current IGPSUP VGPS is 1V below VGPSH GPS Pulldown Current IGPSDN VGPS = 2V GPS Pulldown Resistance RDGPS 1.5 OUTPUT MOSFET GATE DRIVE (GOR) GOR High Voltage VGORH Relative to AGND 4.5 4.8 5.0 V GOR High Comparator Threshold VTHGOR VGOR - VSOR 2.9 3.0 3.1 V 4 _______________________________________________________________________________________ Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions (VPWR = 12V, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) GOR Pullup Resistance RUGOR 5 I GOR Pulldown Resistance RDGOR 2.5 I GOR Pullup Current IGORUP VGOR is 1V below VGORH GOR Pulldown Current IGORDN VGOR = 2V PARAMETER SYMBOL 2.5 A 7 CONDITIONS MIN TYP A MAX UNITS 0.4 V +1 FA 0.4 V +1 FA 1.4 V OUTPUTS (ALERT, READY, GPIO_) ALERT Voltage Low ISINK = 5mA ALERT Output Leakage (Open Drain) VALERT = VDD READY Voltage Low ISINK = 5mA READY Output Leakage (Open Drain) VREADY = VDD -1 -1 GPIO_ Input Logic-High Threshold GPIO_ Input Logic-Low Threshold 0.4 GPIO_ Voltage Low GPIO_ Weak Pullup Current V ISINK = 5mA IWKPU VGPIO_ = 2V -5 -10 0.4 V -20 FA 400 kHz I2C INTERFACE (SCL, SDA, A0, A1) (Figure 3) Serial-Clock Frequency fSCL Bus Free Time Between STOP and START Condition tBUF 1.3 Fs START Condition Setup Time tSU:STA 0.6 Fs START Condition Hold Time tHD:STA 0.6 Fs STOP Condition Setup Time tSU:STO 0.6 Fs Clock Low Period tLOW 1.3 Fs Clock High Period tHIGH 0.6 Fs Data Setup Time tSU:DAT 100 ns Data Hold Time tHD:DAT 0 ns tSP 50 ns Pulse Width of Spike Suppressed SDA, SCL Input Current SDA is not in pulldown, VSCL = VSDA = 5.5V -1 SDA, SCL Logic-Low SDA, SCL Logic-High 0.8 V V 15 ISINK = 5mA A0, A1 Low Voltage A0, A1 High Voltage A0, A1 Input Current FA 1.6 SDA, SCL Input Capacitance SDA Voltage Low +1 pF 0.4 V 0.4 V +1 FA 1.4 VA0 = VA1 = VDD -1 V Note 3: All devices 100% production tested at TA = +25°C and TA = +125°C. Limits at TA = -40°C are guaranteed by design. _______________________________________________________________________________________ 5 MAX5968 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VPWR = 12V, TA = +25NC, unless otherwise noted.) 8.08 8.07 3.5 3.25 3.20 8.05 VGPS (V) IPWR (mA) ISTANDBY INORMAL 3.4 3.10 3.2 3.05 3.1 8.01 8.00 7.99 7.98 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 VPWR (V) TEMPERATURE (NC) VPWR (V) GPS VOLTAGE vs. TEMPERATURE GPS DRIVE CURRENT vs. GPS VOLTAGE GPS DISCHARGE CURRENT vs. GPS VOLTAGE 50 8.2 6 5 40 8.0 7.9 7.8 7.7 4 IGPS (A) IGPS (µA) 8.1 30 -7 26 59 92 2 10 1 0 125 3 20 7.6 7.5 MAX5968 toc06 8.3 60 MAX5968 toc05 VPWR = 12V 8.4 MAX5968 toc04 8.5 0 1 2 3 4 5 6 7 8 0 9 0 4 2 8 6 TEMPERATURE (°C) VGPS (V) VGPS (V) GOR VOLTAGE vs. TEMPERATURE GOR DRIVE CURRENT vs. GOR VOLTAGE GOR DISCHARGE CURRENT vs. GOR VOLTAGE 5 4.855 10 9 8 7 IGOR (A) 4.845 4.840 IGOR (A) 4 4.850 MAX5968 toc09 4.860 6 MAX5968 toc08 VPWR = 12V MAX5968 toc07 4.870 4.865 8.03 -40 -25 -10 5 20 35 50 65 80 95 110 125 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 -40 8.04 8.02 3.3 3.15 VGPS (V) ISTANDBY 3.6 8.09 8.06 3.30 IPWR (mA) VPWR = 12V MAX5968 toc02 INORMAL 3.35 3.7 MAX5968 toc01 3.40 GPS VOLTAGE vs. PWR VOLTAGE PWR CURRENT vs. TEMPERATURE MAX5968 toc03 PWR CURRENT vs. PWR VOLTAGE IGOR (V) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions 3 6 5 4 2 4.835 4.830 3 2 1 4.825 1 4.820 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) 0 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VGOR (V) 0 1 2 VGOR (V) 6 _______________________________________________________________________________________ 3 4 5 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions 20mV THRESHOLD 4 2 32mV THRESHOLD 0 VON RISING 1.230 1.220 1.210 1.200 1.190 1.180 VON FALLING 1.170 1.160 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) TEMPERATURE (NC) OUT FAST COMPARATOR THRESHOLD vs. TEMPERATURE OUT FAST COMPARATOR THRESHOLD vs. LV_DAC CODE 1.600 OUT FAST COMPARATOR THRESHOLD (V) LV_DAC = 127 LV_RANGE = 1 1.400 1.200 1.000 LV_RANGE = 0 0.800 MAX5968 toc13 3.3 MAX5968 toc12 1.800 OUT FAST COMPARATOR THRESHOLD (V) ON INPUT THRESHOLD VOLTAGE (V) 8 6 1.240 MAX5968 toc11 10 ON INPUT THRESHOLD VOLTAGE vs. TEMPERATURE MAX5968 toc10 SLOW COMPARATOR THRESHOLD VOLTAGE ERROR (%) SLOW COMPARATOR THRESHOLD VOLTAGE ERROR vs. TEMPERATURE LV_RANGE = 1 2.2 1.1 0 0.600 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 50 100 150 200 TEMPERATURE (NC) LV_DAC CODE STARTUP WAVEFORM (0N FROM LOW TO HIGH) STARTUP WAVEFORM (PWR FROM 0V TO 16V) MAX5968 toc14 250 MAX5968 toc15 CH1 = VGPS CH2 = VGOR CH3 = VREADY CH4 = VALERT CH1 = VGPS CH2 = VGOR CH3 = VREADY CH4 = VALERT 5V/div 5V/div 5V/div 5V/div 20ms/div 1ms/div _______________________________________________________________________________________ 7 MAX5968 Typical Operating Characteristics (continued) (VPWR = 12V, TA = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (VPWR = 12V, TA = +25NC, unless otherwise noted.) TURN-OFF WAVFORM (SLOW COMPARATOR FAULT) TURN-OFF WAVFORM (FAST COMPARATOR FAULT) MAX5968 toc16 MAX5968 toc17 CH1 = VGPS CH2 = VGOR CH3 = VREADY CH4 = VALERT 5V/div CH1 = VGPS CH2 = VGOR CH3 = VREADY CH4 = VALERT 5V/div 5V/div 5V/div 5V/div 5V/div 5V/div 5V/div 1ms/div 1ms/div ORING FET OFF WAVEFORM 5V/div 5V/div CIRCULAR BUFFER CONTENT AT SLOW TRIP FAULT 4 CURRENT BUFFER (A) CH1 = VGPS CH2 = VGOR CH3 = VREADY CH4 = VALERT 5 MAX5968 toc19 CURRENT BUFFER vs. TIME MAX5968 toc18 3 2 1 5V/div 0 5V/div -1 1ms/div -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (Fs) REVERSE LOAD-VOLTAGE BUFFER vs. TIME 1.2 1.0 0.8 0.6 0.4 1.4 MAX5968 toc21 CIRCULAR BUFFER CONTENT AT SLOW TRIP FAULT 1.2 LOAD-VOLTAGE BUFFER (V) 1.4 MAX5968 toc20 LOAD-VOLTAGE BUFFER vs. TIME LOAD-VOLTAGE BUFFER (V) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions 1.0 0.8 0.6 0.4 0.2 0.2 0 0 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (Fs) -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (Fs) 8 _______________________________________________________________________________________ Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions VCB+ - VCB- ACCURACY vs. TEMPERATURE VADCIN - VINM ACCURACY vs. TEMPERATURE 0.4 0.2 0 -0.2 -0.4 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -15 10 35 60 85 110 -40 -15 10 35 60 85 110 TEMPERATURE (°C) TEMPERATURE (°C) VSOR - VDOR ACCURACY vs. TEMPERATURE LOAD-VOLTAGE ACCURACY vs. TEMPERATURE 1.0 MAX5968 toc24 1.0 VSOR - VDOR = 0mV 0.8 135 0.6 0.2 0 -0.2 -0.4 VOUT - VOUTM = 1V LV_RANGE = 2V 0.6 ACCURACY (%FS) 0.4 0.8 135 MAX5968 toc25 -40 ACCURACY (%FS) VADCIN = 2.5V 0.8 ACCURACY (%FS) ACCURACY (%FS) 0.6 MAX5968 toc23 VCB+ - VCB- = 0mV 0.8 1.0 MAX5968 toc22 1.0 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -40 -15 10 35 60 85 TEMPERATURE (°C) 110 135 -40 -15 10 35 60 85 110 135 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX5968 Typical Operating Characteristics (continued) (VPWR = 12V, TA = +25NC, unless otherwise noted.) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions ON READY INM ADCIN VDD PWR REG Pin Configuration 21 20 19 18 17 16 15 TOP VIEW AGND 22 14 N.C GPS 23 13 GOR CB+ 24 12 PGND CB- 25 11 DOR DGND 26 10 SOR N.C 27 9 OUTM 8 OUT MAX5968 *EP GPIO1 GPIO2 A0 4 5 6 7 SDA 3 SCL 2 ALERT 1 A1 + N.C 28 TQFN *CONNECT EXPOSED PAD TO GROUND. Pin Description PIN NAME 1 GPIO1 General-Purpose Input/Output 1. Configured by internal registers. 2 GPIO2 General-Purpose Input/Output 2. Configured by internal registers. 3 A0 I2C Address Selection Input 1 4 A1 I2C Address Selection Input 2 5 ALERT SCL 6 FUNCTION Active-Low Fault Status Open-Drain Output. Driven low if a failure condition is detected. I2C Clock Input 7 SDA I2C Serial-Data Input/Output 8 OUT Load-Voltage ADC Monitor Positive Input 9 OUTM 10 SOR Reverse-Current Protection External MOSFET Source Connection. Connect to the source of the output reverse-current protection n-channel MOSFETs and the load ground. 11 DOR Reverse-Current Protection External MOSFET Drain Connection. Connect to the drain of the reverse-current protection n-channel MOSFETs and to the converter negative output. 12 PGND 13 GOR Reverse-Current Protection External MOSFET Gate-Drive Output. Connect to gate of the reversecurrent protection n-channel MOSFETs. 14, 27, 28 N.C. No Connection. Not internally connected. 15 REG Internal Regulator Output External Bypass Capacitor Connection. Bypass to ground with a 10FF ceramic capacitor. 16 PWR Device Power Input 17 VDD Digital Supply. Bypass VDD to DGND with a 1FF capacitor. 18 ADCIN Load-Voltage ADC Monitor Negative Input. Connect to the load ground. Power Ground Converter Temperature and Fault Monitoring Input. Connect to converter temperature output signal. This input is multiplexed to the internal ADC for temperature monitoring. 10 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions PIN NAME FUNCTION 19 INM ADCIN Differential Amplifier Reference Input. Connect to the drain of the input protection low-side MOSFET to remove ground bias from the signal at ADCIN. 20 READY Active-Low Converter Enable Open-Drain Output. READY goes low when both GPS and GOR output voltages are high (or enhanced). 21 ON Enable Input. Precision enable input to adjust undervoltage lockout. Connect to PWR for enabled operation. 22 AGND 23 GPS Converter Input Power MOSFET Gate Drive. Connect to the gate of the external n-channel lowside power MOSFET. 24 CB+ Converter Input Current-Sense Amplifier Positive Input 25 CB- Converter Input Current-Sense Amplifier Negative Input 26 DGND — EP Analog Ground Digital Ground Exposed Pad. Connect to the ground plane. Functional Diagram OUTM GPS PWR FAST UV COMPARATOR AND 8-BIT DAC VD1 GSW DRIVER + CBS 1.228V REG - CBF GSW CNTL TIMER + VOUT VCF DAC CBF ON A/D 1.228V PWR REG VDD INM VOR + CSA - EN RST COR CIRCULAR BUFFER EN ADCIN VCS VTHS + CSA - 10mV + REGISTERS AND LOGIC 10mV + COR UV_GOR SOR DOR + 2mV + GOR CNTL CB+ CB- OSC OSCILLATOR UVLO POR VTHF - INTERNAL SUPPLY RAILS AND BIAS - OUT VDD - PWR GOR DRIVER REG GOR ALERT RST UV_GOR ADCINC SCALING AND HV PROTECT INMC ANALOG MUX READY I2C INTERFACE (ANALOG) VOR AGND, DGND, PGND GPIO 1O MAX5968 VCS VOUT A0 A1 SDA SCL GPIO1 GPIO2 ______________________________________________________________________________________ 11 MAX5968 Pin Description (continued) Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions MAX5968 Typical Application Circuit +OUT OUT Q1 ORING FET -OUT OUT+ OUT+ OUT- OUT+ OUT+ OUT+ OUT- OUT- Q2 ORING FET DC-DC CONVERTER LOW-SIDE ORING MOSFET ARRAY +40V VFB IN+ IN+ CM TM VC PC IN- IN- +12VSB +12VSB PC R5 10kI Q8 R2 10I Q4 ORING FET R4 10I Q Q5 ORING FET C4 1FF C1 10FF IN- 23 VDS R 50V 24 25 R6 0.006I 26 28 CB+ MAX5968 CBDGND N.C. N.C. N.C. 14 13 GOR 12 PGND 11 DOR 10 SOR 9 OUTM 8 OUT 7 SDA 6 SCL 5 ALERT 4 A1 3 A0 2 GPIO2 1 GPIO1 27 AGND GPS REG 22 Q6 ORING FET 15 C3 1FF 16 PWR 17 VDD 18 ADCIN 19 INM Q7 20 READY 21 ON LOW-SIDE CIRCUIT-BREAKER MOSFET Q3 ORING FET SDA SCL ALERT 12 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions The MAX5968 is a soft-switch and ideal diode controller that protects systems with redundant DC-DC converter modules by isolating failed modules from the common input and output power. During normal operation, both the input and output MOSFET switches are fully enhanced. The gate of the high-voltage MOSFET at GPS is driven to +8V (typ) to ensure low on-resistance and high-efficiency operation. The gate of the reverse-current blocking MOSFET at GOR is driven to 4.8V (typ) for fast on-off response, low on-resistance, and to stay within the gate-to-source voltage rating of the low-voltage MOSFETs used in this application. The MAX5968 provides input protection by means of a current-sense amplifier connected to a sense resistor that resides at the source of the input protection MOSFET. The current-sense signal is supplied to two precision analog comparators to implement circuit-breaker protection. One comparator has a lower threshold and a slow response time, while the other comparator has a higher threshold and a fast response. This provides good rejection of noise and brief load-current transients, while still protecting the system against slow-onset and short-circuit failures. If either the slow-comparator or fastcomparator threshold is exceeded for sufficient duration, the gate of the input protection MOSFET is pulled low with 1.5A peak current and latched off, disconnecting the converter input from the power supply bus. The fasttrip threshold is programmed through the I2C interface to a value from 0 to 40mV with an 8-bit DAC, and the slowtrip threshold can be set to 50%, 57%, 67%, or 80% of the fast-trip threshold. Converter output protection consists of a precision amplifier and comparator circuit that compares the voltage between the source and drain of an external MOSFET. If the drain rises above the source by 2mV (typ), a reverse-current condition is detected and the gate of the MOSFET immediately pulls low with 7A peak current, blocking the flow of current from the output bus back into the failed converter. As soon as the drain falls to within 1mV (typ) of source potential, the gate of the MOSFET pulls high again with 2.5A peak current to allow forward current flow. This fast, unlatched driver allows the converter module to quickly return to normal operation after a reverse-current transient. A 10-bit ADC is multiplexed to monitor the DC-DC converter input current, the voltage at an auxiliary input, the output MOSFET forward voltage drop, and the load voltage. All ADC results, including circular buffers and the configuration registers, are accessible through a 400kHz I2C interface. The auxiliary ADC input can be connected to a 0 to 5V signal from the converter, typically a combined temperature and fault signal. Two 10-bit circular buffers that contain a history of the 50 most recent input switching current and output loadvoltage digital conversion results help diagnose DC-DC converter faults. A precision on-comparator input can be used to enable or disable the input and output MOSFET drivers by connecting to an external voltage signal, allowing ON to be used as a programmable undervoltage threshold. All inputs are equipped with programmable warning comparators. If an input signal falls outside its digital thresholds, a warning condition is registered, and the ALERT output can be programmed to assert for any or all of these conditions. All monitored signals are equipped with resettable peak-detection registers that store the minimum and maximum values measured since they were last cleared. This peak-detection system reduces or eliminates the need for continuous polling of conversion results. A fast analog comparator continuously monitors OUT voltage and latches the UV_warn register that asserts ALERT. An open-drain READY output can be used to enable the associated DC-DC converter by driving the converter enable input when the input and output MOSFET drivers are fully enhanced, or it can be programmed through the I2C interface to arbitrarily disable the converter at any time. Two general-purpose I/Os can be fully configured through the I2C interface to provide external indications or to control additional peripheral devices. These outputs have sufficient sink-current capability to drive LED indicators. These pins have internal 10FA pullups and sufficient sink-current capability to directly drive LED indicators. SOR/DOR Comparator The SOR/DOR comparator monitors the VDS voltage of the external low-side ORing FET. When VDOR - VSOR exceeds the trip point (+4mV), this comparator trips and commands the ORing FET gate driver to pull GOR to ground, turning off the FET and blocking reverse current. When VDOR - VSOR falls below +2mV, the GOR driver immediately drives GOR high again. During normal operation, transient conditions cause temporary reversal of potential across the ORing FET. The MAX5968 ORing function is intended to block any ______________________________________________________________________________________ 13 MAX5968 Detailed Description MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions reverse current that could occur in this condition, while quickly returning the FET to the on state, immediately after the reverse potential condition is gone. There is a user-selectable timeout period for reverse-current blocking notification. If the GOR output remains low for longer than this timer period, a fault status indicator flag is set in bit 2 of register 0x27. This feature is intended to alert the system to a persistent reverse potential at the ORing FET that is indicative of a failure at the output of the associated converter module. The time delay can be programmed to 192Fs, 128Fs, 64Fs, or 32Fs by writing to the two bits of register 0x39. The default timer value is 192Fs. can be masked or overridden by the chxen register bits. See Figure 2. PWR UVLO and VDD Power-On Reset If the voltage at PWR is below 8.9V or VDD voltage is below +3.5V (typ), the MAX5968 enters power-on reset and all the registers are restored to their default states. For normal operation, the PWR input must be greater than or equal to +9V and VDD must be greater than or equal to +4.5V. A flag is set in register 0x27 whenever the MAX5968 exits the reset state to indicate that all registers are in their default states. CB+/CB- Current-Sense Amplifier The CB+/CB- current-sense amplifier feeds the differential voltage across a current-sense resistor to the internal ADC. The total conversion range is 50mV: the full-scale input voltage is 40mV, and there is an input offset added to allow measurement of reverse current as high as -10mV. SOR/DOR Voltage Amplifier The MAX5968 measures the ORing MOSFET forward voltage (VSOR - VDOR) and sends this value to the ADC for conversion and communication through the I2C bus. The total ADC conversion range is 50mV: full-scale input voltage is -40mV, and there is an offset added to the signal to allow ADC measurement of reverse potential as high as 10mV. GPS Fast Comparator The fast circuit-breaker comparator compares the output of the CB+/CB- current-sense amplifier to the threshold voltage generated by the 8-bit fast circuit-breaker threshold DAC. The DAC voltage is set by writing to register 0x25. This fast comparator commands a quick turn off of the GPS output as soon as its threshold is exceeded, and the fast-trip shutdown flag is set in register 0x27. GOR Gate Driver The GOR gate driver includes a 5I MOSFET driver that pulls up to +4.8V (typ) and pulls down to ground to allow forward current and block reverse current, respectively. The GOR driver is capable of 2.5A peak pullup and 7A peak pulldown currents. A coarse 3V comparator is used to indicate FET full enhancement and sets a GOR gatedrive good flag in register 0x29. GPS Slow Comparator The slow circuit-breaker comparator compares the output of the CB+/CB- current-sense amplifier to a threshold voltage generated by the combination of the fast circuitbreaker threshold DAC and the fast-to-slow threshold ratio setting in register 0x26; see Table 1. When the slow circuit-breaker threshold is exceeded, it starts an analog timer designed so that the timer duration is proportional to comparator overdrive voltage. When the timer expires, the GPS output is driven low and the slow-trip shutdown flag is set in register 0x27. ON Comparator The ON input enables and disables the MAX5968 GPS and GOR outputs. A comparator compares the ON voltage against the internal bandgap voltage with 62.5mV hysteresis. Upon system fault, the input FET pulls low and is latched off. In this situation, the user can toggle the ON input to reset the fault latch and reenable the FETs. In addition, the ON enabling/disabling functionality Table 1. Fast and Slow Circuit-Breaker Comparator Threshold Ranges FAST-TRIP COMPARATOR 8-BIT DAC RANGE (REGISTER 0x25) (mV) 0 to 40 F2S_RATIO[1:0] (REGISTER 0x26) FAST-TRIP TO SLOWTRIP RATIO (%) VALID SLOW-TRIP THRESHOLD RANGE (mV) SPECIFIED SLOW-TRIP THRESHOLD RANGE (mV) 00 125 0 to 32 12.8 to 32 01 150 0 to 26.67 10.67 to 26.67 10 175 0 to 22.86 9.14 to 22.86 11 200 0 to 20 8 to 20 14 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions VDD WEAK PULLUP = 10FA TYP STATUS1 REGISTER GPIO_ GPIO1, GPIO2 GPS Gate Driver Two general-purpose open-drain I/Os can be independently configured by output-enable register 0x37 and output-state register 0x38. The actual voltage state of these I/Os can be read through status register 0x28, regardless of whether they are configured as inputs or outputs. Upon power-on reset, both GPIOs are configured as inputs with 10FA weak pullups. When configured as outputs, both GPIOs have sufficient pulldown strength to directly drive LED indicators (Figure 1). OUT Undervoltage Fast Comparator and ADC Full-Scale Range ALERT Output ALERT is an active-low, open-drain output. The ALERT output defaults to only indicate a failure condition that includes either a circuit-breaker or reverse-current shutdown. A bit can be cleared to unmask the digital and analog warning (UV, OV, or OC) comparator inputs, allowing these conditions to also assert the ALERT output, if desired. ALERT has sufficient pulldown strength to directly drive an LED indicator. GPIO OUTPUT EN BIT DEFAULT = 0 GPIO STATE SET BIT DEFAULT = 0 Figure 1. GPIO Driver The GPS output is designed to drive the gate of a lowside external n-channel MOSFET. When commanded high, GPS is pulled up to an internal 8V rail with a 50FA current source. A 5V comparator is used to indicate full enhancement and set a gate-drive good flag in register 0x29. Upon turn-off, GPS is driven to ground with peak current of 1.5A. The output load voltage is monitored by the ADC. The load voltage is measured differentially between OUT and OUTM. The full-scale conversion voltage is set to either 2V or 4V by writing to the 1-bit register at address 0x18. See Table 2. The load-voltage monitoring amplifier is also connected to a precision fast comparator. The reference for this comparator is generated by an 8-bit DAC, programmed by register 0x24. This sets an undervoltage value from 0 to 1.6V for the 2V OUT range, or 3.2V for the 4V OUT range as shown in Table 2. If VOUT - VOUTM falls below READY Output An open-drain READY pin goes low after the input and output protection MOSFETs are fully enhanced, and remains low until a circuit-breaker fault occurs or until READY is set high impedance by writing to a register. READY can be used to provide an active-high enable signal to the associated converter by driving an external n-channel transistor, thus allowing high-voltage operation. READY has sufficient pulldown strength to directly drive an LED indicator. Table 2. OUT Undervoltage Fast Comparator LV_RANGE VALUE LOAD-VOLTAGE ADC CONVERSION RANGE (OUT RANGE) (V) LOAD-VOLTAGE FAST UNDERVOLTAGE COMPARATOR DAC RANGE (V) 0 0 P VOUT P 2.0 0 P VTHUVDAC P 1.6 1 0 P VOUT P 4.0 0 P VTHUVDAC P 3.2 ______________________________________________________________________________________ 15 MAX5968 QVDD + 0.3V the programmed comparator threshold, the UV warning register bit asserts in register 0x2A. This feature detects load-voltage glitches during fault-protection events that can occur when one of several redundant converters is disabled, causing the load to shift to the other converters. This analog comparator allows detection of fast glitches that are asynchronous to the ADC sample cycle. MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions Register Map If a register is less than 8 bits wide and writable, the nonexistent bits are ignored during a write operation. During a read operation they are read back as 0. Because the I2C protocol uses 8-bit data, the master must write 2 bytes to sequential registers to program the 10-bit settings of the MAX5968. To read 10-bit data, the master should perform a 2-byte burst read, starting on the MSB byte address. See Table 3 for the register address map. Table 3. Register Address Map NAME ADDR ACCESS BIT RANGE RESET VALUE CS_MSB 0x00 R [7:0] 0x00 CS_LSB ADCIN_MSB ADCIN_LSB 0x01 0x02 0x03 R R R [1:0] [7:0] [1:0] 0x00 0x00 0x00 ORFET_MSB 0x04 R [7:0] 0x00 Latest ADC results of output-MOSFET forward voltage, bits [9:2] ORFET_LSB 0x05 R [1:0] 0x00 Latest ADC results of output-MOSFET forward voltage, bits [1:0] LV_MSB LV_LSB min_CS_MSB min_CS_LSB max_CS_MSB max_CS_LSB min_ADCIN_MSB min_ADCIN_LSB max_ADCIN_MSB max_ADCIN_LSB min_ORFET_MSB min_ORFET_LSB max_ORFET_MSB max_ORFET_LSB min_LV_MSB min_LV_LSB max_LV_MSB max_LV_LSB LV_range buf_enable 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 R R R R R R R R R R R R R R R R R R R/W R/W ocw_CS_MSB ocw_CS_LSB 0x1A 0x1B R/W R/W [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0] [7:0] [1:0]  [2:0]    [7:0] [1:0] 0x00 0x00 0xFF 0x03 0x00 0x00 0xFF 0x03 0x00 0x00 0xFF 0x03 0x00 0x00 0xFF 0x03 0x00 0x00 0x00 0x05 1 1 1 0xFF 0x03 Latest ADC results of load voltage, bits [9:2] Latest ADC results of load voltage, bits [1:0] Minimum value of CS amplifier output, bits [9:2] Minimum value of CS amplifier output, bits [1:0] Maximum value of CS amplifier output, bits [9:2] Maximum value of CS amplifier output, bits [1:0] Minimum value of ADCIN, bits [9:2] Minimum value of ADCIN, bits [1:0] Maximum value of ADCIN, bits [9:2] Maximum value of ADCIN, bits [1:0] Minimum value of output-MOSFET forward voltage, bits [9:2] Minimum value of output-MOSFET forward voltage, bits [1:0] Maximum value of output-MOSFET forward voltage, bits [9:2] Maximum value of output-MOSFET forward voltage, bits [1:0] Minimum value of load voltage, bits [9:2] Minimum value of load voltage, bits [1:0] Maximum value of load voltage, bits [9:2] Maximum value of load voltage, bits [1:0] Load voltage ADC input range setting: 0 = 2V, 1 = 4V Selective enabling of circular buffer blocks Current-sense buffer enable bit Load-voltage buffer enable bit Load-voltage buffer stop upon persistent reverse-current fault Digital warning threshold value for overcurrent, bits [9:2] Digital warning threshold value for overcurrent, bits [1:0] uvw_ADCIN_MSB 0x1C R.W [7:0] 0x00 Digital warning undervoltage threshold value for ADCIN, bits [9:2] DESCRIPTION Latest ADC results of CB- amplifier output, bits [9:2] Latest ADC results of CB- amplifier output, bits [1:0] Latest ADC results of ADCIN, bits [9:2] Latest ADC results of ADCIN, bits [1:0] 16 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions NAME ADDR ACCESS BIT RANGE RESET VALUE uvw_ADCIN_LSB 0x1D R/W [1:0] 0x00 Digital warning undervoltage threshold value for ADCIN, bits [1:0] ovw_ADCIN_MSB 0x1E R/W [7:0] 0xFF Digital warning overvoltage threshold value for ADCIN, bits [9:2] ovw_ADCIN_LSB 0x1F R/W [1:0] 0x03 Digital warning overvoltage threshold value for ADCIN, bits [1:0] ovw_ORFET_MSB 0x20 R/W [7:0] 0xFF Digital warning overvoltage threshold value for outputMOSFET voltage, bits [9:2] ovw_ORFET_LSB 0x21 R/W [1:0] 0x03 Digital warning overvoltage threshold value for outputMOSFET voltage, bits [1:0] ovw_LV_MSB 0x22 R/W [7:0] 0xFF Digital warning overvoltage threshold value for load voltage, bits [9:2] ovw_LV_LSB 0x23 R/W [1:0] 0x03 Digital warning overvoltage threshold value for load voltage, bits [1:0] DAC_LV_fc 0x24 R/W [7:0] 0x00 DAC setting for the load-voltage fast undervoltage detection comparator DAC_CS_fc 0x25 R/W [7:0] 0xBF DAC setting for the circuit-breaker fast-trip comparator f2s_ratio 0x26 R/W [1:0] 0x03 Settings for circuit-breaker fast comparator to slow comparator ratio   [3:0]    1 1 0x08 — — — f2s_ratio f2s_ratio Fault shutdown event logging Fast-trip shutdown flag Slow-trip shutdown flag Persistent reverse-current fault flag  — — — — — — — — — — R R [2:0]    [3:0]     [2:0]   0x00 0 0 R/W  0 fault 0x27 R status1 0x28 R status2 0x29 R UV_warn 0x2A DESCRIPTION Default state indicator flag. This bit is set to 1 on initialization (coming out of UVLO). This bit clears to 0 after an I2C write to any writable register. External input status ON state GPIO1 state GPIO2 state External output status READY state ALERT flag GPS-GOOD state GOR-GOOD state Undervoltage warning comparators status ADCIN undervoltage warning flag Load-voltage fast undervoltage comparator warning flag Undervoltage warning flag ALERT unmask bit; 1 to unmask ALERT ______________________________________________________________________________________ 17 MAX5968 Table 3. Register Address Map (continued) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions Table 3. Register Address Map (continued) NAME ADDR OV_warn 0x2B OC_warn BIT RANGE RESET VALUE R R R [3:0]    0x00 0 0 0 R/W  0 R [1:0]  0x00 0 R/W  0 ACCESS 0x2C DESCRIPTION Digital overvoltage warning comparators status ADCIN overvoltage warning flag ORing FET forward overvoltage warning flag Load-voltage overvoltage warning flag Overvoltage warning flag ALERT unmask bit; 1 to unmask ALERT Digital overcurrent warning comparator status Overcurrent warning flag Overcurrent warning flag ALERT unmask bit;1 to unmask ALERT fokey foset 0x2D 0x2E R/W R/W [7:0] [2:0]    0x00 0x00 0 0 0 Key to allow force on function Force-on activation (valid only when fokey = 0xA5) Force-on for input switch (GPS output) Force-on for reverse-current protection switch (GOR output) Force reset on all registers, also resets itself chxen 0x2F R/W [3:0] 0x00 Channel activation bits (combinational functioning with ON comparator)    0 0 0   [0:0] [1:0]    [1:0]   0 0x00 0x00 0x00 0 0 0 GPS master enable GPS ON-enabling mask bit; 1 to mask ON-enabling GOR master enable GOR ON-enabling mask bit; 1 to mask ON-enabling Input overcurrent warning comparator deglitch on/off Deglitch setting bit for ADCIN undervoltage comparator Deglitch setting bits for overvoltage comparators ADCIN overvoltage warning deglitch on/off ORing FET forward overvoltage warning deglitch on/off Load-voltage overvoltage warning deglitch on/off Select 10-bit or 8-bit read-out from circular buffers Set to 1 for 8-bit read-out mode on current-sense buffer Set to 1 for 8-bit read-out mode on load-voltage buffer dgl_i dgl_uv dgl_ov 0x30 0x31 0x32 R/W R/W R/W buf_read_8bit 0x33 R/W buf_stp_dly 0x34 R/W [5:0] 0x19 Number of samples to be stored before stopping buffers (valid 0 to 63) peak_log_rst 0x35 R/W [3:0] 0x00 When a bit is 1 the related signal peak detection is cleared to startup values     0 0 0 0 0x00 0 0 Input current min/max clear ADCIN min/max clear ORing switch voltage min/max clear Load voltage min/max clear 18 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions NAME ADDR ACCESS BIT RANGE RESET VALUE peak_log_hold 0x36 R/W [3:0] 0x00 When a bit is 1 the related signal peak detection is held (no change allowed) R/W     [1:0] 0 0 0 0 0x00 Input current min/max hold ADCIN min/max hold ORing switch voltage min/max hold Load voltage min/max hold GPIO output enable  0 Set to 1 to enable GPIO1 as open-drain output (0 for CMOS input with weak pullup)  0 Set to 1 to enable GPIO2 as open-drain output (0 for CMOS input with weak pullup) [1:0] 0x00  0 Set to 0 to pull down GPIO1 when in output mode; set to 1 to allow GPIO1 to go high (internal weak pullup to VDD)  0 Set to 0 to pull down GPIO2 when in output mode; set to 1 to allow GPIO2 to go high (internal weak pullup to VDD) [1:0] 0x03  1  1 00 01 10 11 [7:0] [7:0] — — Base address for the input current circular buffer Base address for the load-voltage circular buffer GPIO_out_en GPIO_state_set or_fault_timer buf_base_CS buf_base_LV 0x37 0x38 0x39 0x3A 0x3B R/W R/W R R Setting Circuit-Breaker Thresholds To select and set the MAX5968 slow-trip and fast-trip comparator thresholds, use the following procedure: 1) S elect one of four ratios between the fast-trip threshold and the slow-trip threshold: 200%, 175%, 150%, or 125%. The ratio is set by writing to the f2s_ratio register (the default setting on power-up is 200%). 2) D etermine the slow-trip threshold VTH,ST based on the anticipated maximum continuous module input current during normal operation, and the value of the current-sense resistor. The slow-trip threshold should include some margin above the maximum input current to prevent spurious circuit-breaker shutdown and to accommodate passive component tolerances: VTH,ST = RSENSE x IINPUT,MAX x 120% 3) C alculate the necessary fast-trip threshold VTH,FT based on the ratio set in step 1: VTH,FT = VTH,ST x (fast-to-slow threshold ratio) DESCRIPTION GPIO output state ORing fault flag time delay setting. Default is 192Fs. = = = = 32Fs 64Fs 128Fs 192Fs 4) P rogram the fast-trip and slow-trip thresholds by writing an 8-bit value to the DAC_CS_fc register. This 8-bit value is determined from the desired VTH,ST value that was calculated in step 2, the threshold ratio from step 1, and the current-sense range of +40mV: DAC = VTH,ST x 255 x (fast-to-slow threshold ratio)/ (40mV) Table 1 shows the specified ranges for the fast-trip and slow-trip thresholds for all selections of the fast-to-slow threshold ratio. The fast-trip DAC can be programmed to values below 0x26 (40% of the current-sense range), but accuracy is not specified for operation below 40%. Force-On Bit When the force-on bit is set to 1, the input and output switches are enabled and do not shut down. The overcurrent and reverse current comparator outputs are ignored. The power-on reset value of this bit is 0. There is a Force-On Key register that must be set to 0xA5 for the force-on function to become active. If this register ______________________________________________________________________________________ 19 MAX5968 Table 3. Register Address Map (continued) MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions contains any value other than 0xA5, setting the force-on bit to 1 has no effect. The power-on default value of the Force-On Key register is 0x00. voltage value, the warning flag registers are set. Each group of warning flag registers has a mask bit that masks or unmasks ALERT bit response to these warning flags. ADC Result Registers The default value of the overvoltage and overcurrent thresholds is 0x3FF, and the default value for the undervoltage threshold is 0x000. These default values disable the associated digital comparator. When the values are programmed to some value other than the default, the comparator is active. Result registers contain the most recent ADC values. Because the ADC is multiplexed to four different channels sequentially, at any time the result registers can contain values from the current ADC cycle and the previous cycle. For example, if the conversion for channel 2 was just stored in the ADC Result register, registers for channels 0, 1, and 2 would contain values from the present scan and the registers for channel 3 would contain the values from the previous scan. The registers can be read at any time through the I2C interface. The registers are buffered so that reading any ADC result register does not interrupt or delay the ADC cycle, nor does it cause missed readings. Reading the under/over warning flag registers automatically clears the contents of the registers, eliminating the need for a second I2C write operation to clear the flags. See Table 4. Circular Buffer The circular buffer includes two banks—one for the voltage measurement across the input current-sense resistor, and another for the load-voltage measurement; each comprises 50 10-bit samples. Min/Max Registers Each ADC channel features a min and a max register; there are four min registers and four max registers. In each ADC cycle for each signal, the ADC reading is compared to the contents of the min register. If the current value is less than min register value, the current value is stored in the min register. If the current value is greater than the value in the max register, the current value is stored in the max register. The input current and load-voltage min/max registers do not update when the circular buffers are stopped because of a fault condition or shutdown. A block read is triggered by the I2C interface when a read operation is attempted from one of the circular buffer block base addresses. Readings can be either of the whole 10-bit samples or of the 8-bit upper bytes, according to the buf_read_8bit register. Internal writing to either or both of the buffers can be inhibited directly by the user through a dedicated register at 0x19. Writing to the buffers also stops when the input switch is shut down. When a buffer block is read through the I2C interface, new load voltage and input current measurements are not written into the circular buffer. The power-on reset value of the min registers is 0x3FF. To reset a min register, write 0x3FF. When a circular buffer is commanded to stop for any reason, the MAX5968 continues to write a number of samples equal to the digital value stored in register 0x34. This allows the buffer(s) to store data that precedes and follows the stop command, forming a complete picture of the conditions immediately before and after a fault or normal shutdown. The power-on reset value of the max registers is 0x000. To reset a max register, write 0x000. Control registers are provided to hold and clear the min and max registers independently for each signal. Digital Warning Comparators Each monitored signal is equipped with one or more programmable digital warning comparators. If the most recent conversion result exceeds the programmed overvoltage or overcurrent value, or is less than the under- If a reverse-current condition persists for more than the programmable ORing-fault timeout, the load-voltage buffer stops, and the load-voltage buffer-enable bit Table 4. Digital Warning Comparators Warnings TYPE CHANNEL 0: CURRENT SENSE Undervoltage CHANNEL 2: ORING VOLTAGE U CHANNEL 3: LOAD VOLTAGE Analog comparator U Overvoltage Overcurrent CHANNEL 1: ADCIN U U 20 ������������������������������������������������������������������������������������� U Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions GPS and GOR Enable/Disable Use the chxen register 0x2F to enable or disable the GOR and GPS driver logic in combination with (or regardless of) the ON comparator output, as shown in Figure 2. Bits 0 and 2 of register 0x2F are master enable bits for the GPS and GOR drivers, respectively. Bits 1 and 3 of register 0x2F mask the status of the ON com- chxen_0 ON + VTHON - chxen_1 EN_GPS chxen_3 EN_GOR chxen_2 Figure 2. Enable Logic for GPS and GOR Drivers parator. Note that the master-enable bits override the ON masking bits. I2C Serial Interface The MAX5968 features an I2C-compatible serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL allow bidirectional communication between the MAX5968 and the master device at clock rates from 100kHz to 400kHz. The I2C bus can have several devices (e.g., more than one MAX5968, or other I2C devices in addition to the MAX5968) attached simultaneously. The A0 and A1 inputs set one of four possible I2C addresses (see Table 6). The 2-wire communication is fully compatible with existing 2-wire serial interface systems. Figure 2 shows the interface timing diagram. The MAX5968 is a transmit/ receive slave-only device, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates with the MAX5968 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is a logic input/opendrain output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kI for most applications. Table 5. Circular Buffer Registers 0x19 INPUT CURRENT BUFFER LOAD-VOLTAGE BUFFER RECOVERY Input circuit-breaker fault X Stopped Stopped Toggle input switch enable off-on Clear 0x19 X Stopped Running Write 1 to 0x19 Clear 0x19 X Running Stopped Write 1 to 0x19 1 Running Stopped Write 1 to 0x19 0 Running Running None required Input switch disabled X Stopped Stopped Reenable input switch ORing switch disabled X Running Stopped Reenable ORing switch Reading load-voltage buffer base address X Running Stopped Read/write from any other register address Reading input current buffer X Stopped Running Read/write from any other register address CONDITION Persistent reverse-current fault flag set ______________________________________________________________________________________ 21 MAX5968 at 0x19 is cleared. This allows the user to read the contents of the circular buffer after a persistent reversecurrent condition, even if the condition clears. The buffer is then restarted by writing a 1 to bit 2 of 0x19. However, if this function is not desired, bit 3 of register 0x19 can be cleared to prevent a reverse-current fault condition from stopping the load-voltage buffer by blocking the logic that would otherwise clear the buffer enable bit 0x19. See Table 5. MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions Table 6. Slave Address Settings I2C ADDRESS BITS ADDRESS INPUT STATE A1 A0 ADDR 7 ADDR 6 ADDR 5 ADDR 4 ADDR 3 ADDR 2 ADDR 1 Low Low 0 1 1 1 1 0 0 R/W Low High 0 1 1 1 1 0 1 R/W High Low 0 1 1 1 1 1 0 R/W High High 0 1 1 1 1 1 1 R/W Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (see Figure 3), otherwise the MAX5968 registers a START or STOP condition (see Figure 4) from the master. SDA and SCL idle high when the bus is not busy. ADDR 0 START and STOP Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START condition (see Figure 5) by transitioning SDA from high to low while SCL is high. The master device issues a STOP condition (see Figure 4) by SDA tSU:DAT tBUF tSU:STA tHD:DAT tLOW tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION Figure 3. Serial-Interface Timing Details SDA SDA SCL SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID Figure 4. Bit Transfer S P START CONDITION STOP CONDITION Figure 5. START and STOP Conditions 22 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions WRITE WORD FORMAT SEND BYTE FORMAT S ADDRESS R/W 7 BITS 0 ACK DATA ACK S P 8 BITS DATA BYTE–PRESETS THE INTERNAL ADDRESS POINTER. SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. ADDRESS R/W 7 BITS 1 ADDRESS R/W 7 BITS 0 ACK COMMAND ACK DATA 8 BITS SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. RECEIVE BYTE FORMAT S Early STOP Conditions The MAX5968 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format. At least one clock pulse must separate any START and STOP condition. 8 BITS COMMAND BYTE– MSB OF THE EEPROM REGISTER BEING WRITTEN. ACK P 8 BITS DATA BYTE–FIRST BYTE IS THE LSB OF THE EEPROM ADDRESS. SECOND BYTE IS THE ACTUAL DATA. ACK ACK DATA P S 8 BITS DATA BYTE–READS DATA FROM THE REGISTER COMMANDED BY THE LAST READ BYTE OR WRITE BYTE TRANSMISSION. ALSO DEPENDENT ON A SEND BYTE. ADDRESS R/W 7 BITS 0 ACK COMMAND ACK R/W 7 BITS ACK COMMAND ACK SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. DATA BYTE 1 8 BITS 8 BITS 0 ACK ACK DATA BYTE ... 8 BITS COMMAND BYTE– PREPARES DEVICE FOR BLOCK OPERATION. ACK 8 BITS ACK P 8 BITS COMMAND BYTE– SELECTS REGISTER BEING WRITTEN. SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. BYTE COUNT= N DATA 8 BITS BLOCK WRITE FORMAT ADDRESS DATA WRITE BYTE FORMAT SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. S ACK DATA BYTE–DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE IF THE COMMAND IS BELOW 50h. IF THE COMMAND IS 80h, 81h, OR 82h, THE DATA BYTE PRESETS THE LSB OF AN EEPROM ADDRESS. DATA BYTE N ACK P 8 BITS DATA BYTE–DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE. BLOCK READ FORMAT S ADDRESS R/W 7 BITS ACK COMMAND ACK 8 BITS 0 SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. S = START CONDITION. P = STOP CONDITION. COMMAND BYTE– PREPARES DEVICE FOR BLOCK OPERATION. Sr ADDRESS R/W 7 BITS 1 SLAVE ADDRESS– EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. ACK BYTE COUNT= 16 10h ACK DATA BYTE ACK 1 8 BITS DATA BYTE ... 8 BITS ACK DATA BYTE ACK N P 8 BITS DATA BYTE–DATA GOES INTO THE REGISTER SET BY THE COMMAND BYTE. SHADED = SLAVE TRANSMISSION. Sr = REPEATED START CONDITION. Figure 6. SMBUS/I2C Protocols ______________________________________________________________________________________ 23 MAX5968 transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 5). MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions START CONDITION CLOCK PULSE FOR ACKNOWLEDGE 1 SCL 2 8 9 SDA BY TRANSMITTER S SDA BY RECEIVER Figure 7. Acknowledge REPEATED START Conditions A REPEATED START (Sr) condition can indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 5). Sr can also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5968 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed. If the master sends a STOP condition, the internal address pointer does not change. The send byte procedure is as follows: Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX5968 generates an ACK when receiving an address or data by pulling SDA low during the 9th clock period (see Figure 6). When transmitting data, such as when the master device reads data back from the MAX5968, the MAX5968 waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX5968 generates a NACK after the slave address during a software reboot or when receiving an illegal memory address. 4) The master sends an 8-bit data byte. Send Byte The send byte protocol allows the master device to send 1 byte of data to the slave device (see Figure 5). The 6) The master sends an 8-bit data byte. 1) The master sends a START condition. 2) T he master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a STOP condition. Write Byte The write byte/word protocol allows the master device to write a single byte in the register bank or to write to a series of sequential register addresses. The write byte procedure is as follows: 1) The master sends a START condition. 2) T he master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit command code. 5) The addressed slave asserts an ACK on SDA. 7) The addressed slave asserts an ACK on SDA. 24 ������������������������������������������������������������������������������������� Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions READ-OUT ORDER 1st OUT 2nd OUT … 48th OUT 49th OUT 50th OUT Chronological Number 1 2 … 48 49 0 8) T he addressed slave increments its internal address pointer. 9) T he master sends a STOP condition or repeats steps 6, 7, and 8. To write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The data byte is written to the register bank if the command code is valid. The slave generates a NACK at step 5 if the command code is invalid. The command code must be in the range of 0x00 to 0x3B. The internal address pointer returns to 0x00 after incrementing from the highest register address. Receive Byte The receive byte protocol allows the master device to read the register content of the MAX5968 (see Figure 6). The EEPROM or register address must be preset with a send byte protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure is as follows: 1) The master sends a START condition. 2) T he master sends the 7-bit slave address and a read bit (high). 3) The addressed slave asserts an ACK on SDA. 4) The slave sends 8 data bits. 0x00 to 0x3B, and the circular buffer addresses are 0x3A to 0x3B. Register addresses outside of this range result in a NACK being issued from the MAX5968. Circular Buffer Read The circular buffer read operation is similar to the receive byte operation. The read operation is triggered after any one of the circular buffer base addresses is loaded. During a circular buffer read, although all is transparent from the external world, internally the autoincrement function in the I2C controller is disabled. Thus, it is possible to read one of the circular buffer blocks with a burst read without changing the virtual internal address corresponding to the base address. Once the master issues a NACK, the circular reading stops, and the default functions of I2C slave bus controller are restored. In 8-bit read mode, every I2C read operation shifts out a single sample from the circular buffer. In 10-bit mode, two subsequent I2C read operations shift out a single 10-bit sample from the circular buffer, with the high-order byte read first, followed by a byte containing the rightshifted two least-significant bits. Once the master issues a NACK, the read circular buffer operation terminates and normal I2C operation returns. The data in the circular buffers is read back with the nextto-oldest sample first, followed by progressively more recent samples until the most recent sample is retrieved, followed finally by the oldest sample (see Table 7). Chip Information 5) The slave increments its internal address pointer. 6) T he master asserts an ACK on SDA and repeats steps 4 and 5 or asserts a NACK and generates a STOP condition. The internal address pointer returns to 0x00 after incrementing from the highest register address. Address Pointers Use the send byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE CODE DOCUMENT NO. 28 TQFN-EP T2855+6 21-0140 ______________________________________________________________________________________ 25 MAX5968 Table 7. Circular Buffer Readout Sequence MAX5968 Circuit-Breaker and Ideal Diode Controller with Digital Monitoring Functions Revision History REVISION NUMBER REVISION DATE 0 1/10 Initial release 1 2/10 Updated the Absolute Maximum Ratings and Electrical Characteristics. DESCRIPTION PAGES CHANGED — 2, 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 © 2010 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.