T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8223 The TQ8223 is extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream is demultiplexed into a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also available. The device generates byte-wise parity check bits for the demultiplexed data and provides associated clock outputs for the different modes. Parity checking is not required for normal device operation. The TQ8223 provides added flexibility through a selectable internal/external Voltage Controlled Oscillator(VCO) as well as a selectable internal Phase Locked Loop (PLL). If an external high frequency clock is utilized a singleended or differential AC coupled clock may be used. The internal PLL contains a NRZ phase detector which enables it to adjust the phase of the internal clock such that sampling of the incoming data stream occurs in the middle of the the data eye. An offset control allows adjustment ±125 pS around this nominal position. Operating from a single +5V supply, the TQ8223 provides fully compliant functionality and performance. PRELIMINARY DATA SHEET OC48/STM16 DEMUX/CDR with Differential Input TELECOM PRODUCTS The TQ8223 is a multi-configuration SONET/SDH OC48/STM16 CDR/ DEMUX that regenerates and re-times serial 2.48832 Gb/s data. It recovers the 2.48832 GHz clock from the data stream and frequency divides it to generate control signals and clocks used to perform the demultiplexing function. Features • Single-chip 1:32 Demultiplexer with integrated clock and data recovery • Differential Analog Data Input • SONET/SDH compliant for 2.48832 Gb/s jitter tolerance & transfer • Internal PLL with NRZ phase detector ensures sampling of incoming data stream occurs in center of data eye • Static phase adjustment on recovered clock position • High speed input data bit slipper for use in framing • External RC-based loop filter The TQ8223 is fully compliant with SONET/SDH jitter tolerance and transfer specifications. A TTL level LOCK signal is supplied to indicate when the frequency difference between the internal 38.88 MHz clock and the external 38.88 MHz clock is less than 488 ppm. • Four output clock rates at 311.04, 155.52, 77.76, and 38.88 MHz. • Internal byte-wise even/odd parity bit generator (mode programable) • Direct-coupled TTL low-speed outputs • 23mm 208-pin BGA package • 5V single supply • –40 to +125°C case operating temperature. 1 TQ8223 PRELIMINARY DATA SHEET Figure 1. TQ8223 Block Diagram MODE0 32 RQ1n-RQ4n MODE1 DEMUX DIN NDIN Data Regenerator Parity Generator and Output Register 4 RQPAR1-4 DATINV PARSEL SLIP RESET/RSTN CK311 VOSC NCK311 Clock Input Selector VTUNE VCO 1 CK155 Clock Divider CK78T 0 NCLKIN CLKIN CK39 CLKSEL 2.48832GHz Active Clock HINTCLK PPMSEL NRZ Phase Detector and LOCK Detect 50Ω Resistive Tap HCKOUT PHREF LOCKREF DCREF Charge Pump VTUNEO PHADJ LOCK Internal PLL 2 TQ8223 Data Regeneration The TQ8223 recovers and regenerates serial 2.48832 Gb/s data received at DIN and NDIN. The data recovery can be optimized by adjusting the input data re-timing clock phase at PHADJ. The PHADJ range is 2.5 +/0.5V. This corresponds to a centered sampling point when PHADJ is 2.5V and a -128 pS or +128 pS offset for 3V and 2V repectively. PHADJ must be externally supplied. See the figure below. PHADJ Operation PHADJ 3.0V 2.5V Time -128pS 0pS power supply pin, VOSC, is tied to VDD. CLKIN must be tied to VEE through a 10kΩ resistor when the internal clock is used. The internal PLL is comprised of a NRZ phase detector, a charge pump, and the internal VCO. This NRZ phase detector’s phase error signals are integrated by the Charge Pump block which then provides a VCO tune voltage at VTUNEO. See Table 5 for loop filter values. The internal PLL is completed by connecting VTUNEO to VTUNE. The purpose of the internal PLL is to adjust the phase of the internal VCO such that the negative edge of the internal sampling clock is in the center of the data eye. A phase offset can be added by adjusting the PHADJ input voltage. A 38.88 MHz PECL clock must be provided at HINTCLK to aid PLL acquisition. 2.0V 128pS The regenerated data is then re-synchronized by retiming it with the active 2.48832 GHz clock. (Negative edge triggered sampling is used.) The regenerated data can be inverted by tying the DATINV pin to VEE. Bit Slipper The TQ8223 can slip a bit on the incoming data stream. An active low PECL pin, SLIP, causes the TQ8223 to skip over one incoming data bit. This can be done for framing purposes. The internal PLL provides an active high LOCK signal if the frequency difference between the internal VCO and the 38.88 MHz hint clock remains less than 488 ppm. If the frequency difference becomes greater than 488 ppm then the LOCK signal deasserts low. The LOCK signal will assert high when the frequency difference is less then 122 ppm or 30 ppm. This hysteresis set point is programmable and is determined by PPMSEL. When PPMSEL is tied to VEE the LOCK set point is 30 ppm, when PPMSEL is tied to VDD the LOCK set point is 122 ppm. LOCK Signal Hysteresis Timing Generation HIGH LOCK The TQ8223 can receive an external 2.48832 GHz (nominal) reference clock or generate a 2.48832 GHz clock through an internal VCO. The output of the active clock can be monitored at HKCOUT which provides a 30mVpp output. LOW 30ppm 488ppm or 122ppm Clock Freq. Difference Internal Clock VCO and PLL Figure 8 contains a reference diagram of operation with the internal clock and PLL. The internal clock is selected if the CLKSEL is tied to VDD and the external 3 TELECOM PRODUCTS Function Description SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET TQ8223 PRELIMINARY DATA SHEET Figure 2. PLL and Lock Detector Block Diagram LOCKREF Up PHASE (N)DIN 2:1 DETECT VOSC Dn UP CHARGE PUMP VTUNEO VTUNE VCO HCKOUT DOWN HINTCLK PHASE Up FREQ DETECT 2:1 Dn PLLVDD CLOCK DIVIDER CK38 LOCK LOCK DETECT External Clock VCO and PLL The received clock can be either single-ended or differential and is an AC coupled input on CKIN and NCKIN. The external clock is selected as the active clock if CLKSEL is tied to VEE. VOSC and VTUNE must be tied to VEE when using an external VCO. If the external clock is single ended the unused input must be externally terminated through a capacitor to an AC ground. The internal NRZ phase detector generates 4 PHREF and DCREF which, when connected to an external integrator, may be used to tune the external VCO. TQ8223 See Figure 9 for a reference diagram of operation with the internal clock and external PLL. PHREF and DCREF must be connected to an external integrator. The output of the integrator is then connected to VTUNE, completing the PLL. Output Clocks The TQ8223 provides an internal Clock Divider which frequency divides the active 2.48832 GHz clock (internal or external source as selected by CLKSEL). The output of the Clock Divider supplies the internal clock signals necessary for the re-timing function and demultiplexing function. Clock Divider block also outputs four external clocks: a differential 311.04 MHz PECL clock at CK311 and NCK311, a 155.52MHz PECL clock at CK155, a 77.76 MHz TTL clock at CK78T, and a 38.88 MHz PECL clock at CK39. Note that the clock frequencies given above are dependant upon using the part at 2.48832 GHz. In a 1:32 demultiplexing application, the TQ8223 regenerates the serial 2.48832 Gb/s data stream and re-times it with the negative edge of the active 2.48832 GHz clock. The re-timed serial data stream is then 1:32 demultiplexed by the DEMUX block into an 32-bit wide 77.76 MHz data bus at RQ11-RQ48. A parity bit is generated for each byte, and transmitted in parallel to the data at RQPAR(1:4). The 32-bit wide data plus four parity bits are then clocked out on the falling edge of the internally generated 77.76 MHz clock. See Figure 6. Data Demultiplexer and Parity Generator The TQ8223 can be configured to run in one of two modes. The demultiplexing modes are set by fixing the MODE1 and MODE0 package pins according to the following table. MODE1 MODE0 VEE N.C. VEE VEE Demultiplexing Mode 1:32 ALL 1’s OUTPUTS For all modes the first high speed input bit in time appears on RQ11, which is the most significant bit. Subsequent input data is output sequentially to RQ12RQ48. Byte #1, RQ11-RQ18, is the most significant byte. Odd or even parity selection is programmable by PARSEL. If PARSEL is left open (N.C.) the parity is even. If PARSEL is tied to VEE the parity is odd. 5 TELECOM PRODUCTS Internal Clock VCO and External PLL SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET TQ8223 PRELIMINARY DATA SHEET Figure 3. TQ8223 Pinout - Top View 1 2 A B C D E F G H J K L M N P R T U 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VEE MODE0 VEE MODE1 IOVEE DATINV VDD VDD RQ48 IOVEE VDD RQ45 RQ46 VEE RQ43 RQ44 RQ47 RQ41 RQ42 IOVDD IOVEE VEE RQPAR4 RQPAR3 RQ37 RQ36 CVEE VDT1 VDT2 CVDD CVEE VDT1 VDT2 IOVDD VDT1 VDT2 IOVDD VEE PHREF DCREF IOVDD NCKIN VEE RESET IOVDD CKIN VDD VDD VDD VEE IOVEE VDD IOVDD VDD IOVDD VEE RSTN IOVDD PPMSEL TESTMODE SLIP LOCK CLKSEL VEE LOCKREF IOVDD TB_UPDN TQ8223 VDD PLLVDD PLLVEE RQ38 IOVDD VOSC PHADJ RQ35 IOVEE IOVDD VDD VDD VDD IOVEE VTUNEO IOVDD CK78T VEE HCKOUT VDD CK39 CK155 NCK311 VEE CK311 208-pin BGA Top View IOVDD IOVEE RQ33 IOVEE IOVDD VDD IOVDD VEE VEE VEE 1 2 CVDD IOVDD RQ34 VEE VDD NDIN VDD RQ31 RQ32 VDD DIN VDD VDD IOVDD VDD RQ26 RQ24 VEE RQ27 RQ28 RQ25 RQ23 VDD RQPAR1 RQ15 RQ12 IOVDD VEE VDD RQPAR2 RQ16 RQ13 IOVDD IOVEE VEE RQ22 VEE IOVDD VEE RQ14 IOVDD RQ21 IOVEE RQ18 RQ17 IOVEE RQ11 VEE VTUNE VDD PARSEL VEE VEE HINTCLK ID A B C D E F G H J K L M N P R T U 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 = NC (Do Not Connect) Note: Heat Spreader is at VDD volts. 6 TQ8223 SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET Table 1. Signal Description Pin No. Grid Ref. Signal Type & Freq/Bit Rate Description 50 49 A3 B3 MODE0 MODE1 Input DC Input DC (MODE1 = N.C., MODE0 = N.C.) = Do Not Use; (MODE1 = N.C., MODE0 = VEE) = 1:16 demultiplexing; (MODE1 = VEE, MODE0 = N.C.) = 1:32 demultiplexing; (MODE1 = VEE, MODE0 = VEE) = all 1’s output. Input AC 2.48832 Gb/s High speed differential data input. Must be AC coupled. The input is internally terminated by RT Ω to VTD1,2. 26,27,28 B9,C9,D9 VTD2 31,32,33 B8,C8,D8 VTD1 Input Analog DC Input Analog DC Input signal termination voltage, nominally at VDD-2.8V. 46 DATINV Input Analog DC DIN complement select signal. N.C. = true; VEE =complement TELECOM PRODUCTS Data Demultiplexing Configuration 2.5Gb/s Input Interface 30 29 A8 A9 B4 DIN NDIN 77.76Mb/s Interface 142 U12 RQ11 Output TTL 77.76 MHz Byte #1. Most significant Byte (MSB). Parallel data bit. RQ11 is the most significant bit. 141 P11 RQ12 Output TTL Parallel data bit 140 R11 RQ13 Output TTL Parallel data bit 139 T11 RQ14 Output TTL Parallel data bit 136 P10 RQ15 Output TTL Parallel data bit 135 R10 RQ16 Output TTL Parallel data bit 134 U10 RQ17 Output TTL Parallel data bit 133 U9 RQ18 Output TTL RQ18 is the least significant bit of the MSB (Byte #1) 131 P9 RQPAR1 Output TTL Parity bit signal for the 8-bit wide data at RQ11 to RQ18. The parity bit is simultaneous with the byte wide data at RQ11-RQ18 from which it was calculated. 125 U7 RQ21 Output TTL 77.76 MHz Byte #2 RQ21 is the most significant bit. 124 T7 RQ22 Output TTL Parallel data bit 123 U6 RQ23 Output TTL Parallel data bit 122 R7 RQ24 Output TTL Parallel data bit 119 U5 RQ25 Output TTL Parallel data bit 118 R6 RQ26 Output TTL Parallel data bit 117 T5 RQ27 Output TTL Parallel data bit 116 U4 RQ28 Output TTL RQ28 is the least significant bit of Byte#2 7 TQ8223 PRELIMINARY DATA SHEET Table 1. Signal Description (continued) Pin No. Grid Ref. Signal Type and Freq. or Bit Rate Description 130 R9 RQPAR2 Output TTL Parity bit signal for the 8-bit wide data at RQ21 to RQ28. The parity bit is simultaneous with the byte wide data at RQ21-RQ28 from which it was calculated. 90 L2 RQ31 Output TTL 77.76 Mb/s Byte #3 RQ31 is the most significant bit. 89 P1 RQ32 Output TTL Parallel data bit 88 N1 RQ33 Output TTLL Parallel data bit 87 M1 RQ34 Output TTL Parallel data bit 84 K3 RQ35 Output TTL Parallel data bit 83 K2 RQ36 Output TTL Parallel data bit 82 K1 RQ37 Output TTL Parallel data bit 81 J3 RQ38 Output TTL RQ38 is the least significant bit of Byte #3 79 J2 RQPAR3 Output TTL Parity bit signal for the 8-bit wide data at RQ31 to RQ38. The parity bit is simultaneous with the byte wide data at RQ31-RQ38 from which it was calculated. 73 G1 RQ41 Output TTL 77.76 Mb/s Byte #4 RQ41 is the most significant bit. 72 G2 RQ42 Output TTL Parallel data bit 71 F1 RQ43 Output TTL Parallel data bit 70 F2 RQ44 Output TTL Parallel data bit 67 E1 RQ45 Output TTL Parallel data bit 66 E2 RQ46 Output TTL Parallel data bit 65 F3 RQ47 Output TTL Parallel data bit 64 D1 RQ48 Output TTL RQ48 is the least significant bit of the LSB (Byte #4) 78 J1 RQPAR4 Output TTL Parity bit signal for the 8-bit wide data at RQ41 to RQ48. The parity bit is defined to be in parallel with the byte wide data at RQ41-RQ48 from which it was calculated. 170 P17 CK311 Output PECL 311.04 MHz 311.04 MHz differential clock output. Must be externally terminated by RTe Ω to VTTe. 171 N17 NCK311 Output PECL 311.04 MHz Complement of CK311 Must be externally terminated by RTe Ω to VTTe. 169 N16 CK155 Output PECL 155.52 MHz 155.52 MHz clock output. 168 M15 CK78T Output TTL 77.76 MHz 77.76 MHz clock output. 167 N15 CK39 Output PECL 38.88 MHz 38.88 MHz clock output. Phase-locked Loops Elements 182 J14 VOSC Analog Power Supply Analog power supply for the internal VCO. VEE = VCO OFF; VDD = VCO ON 181 K17 VTUNE Input Analog Frequency tune voltage for internal VCO. Negative tune slope. Must be tied to VEE when using an external VCO. 8 TQ8223 Table 1. Signal Description (continued) Grid Ref. Signal Type and Freq. or Bit Rate Description 8 C13 CKIN Input AC 2.48832 GHz High frequency clock input. The differential inputs must be AC coupled and externally terminated by RTe Ω to VTTe. Must be externally terminated by 10kΩ to VEE when internal VCO is used. 7 B15 NCKIN Input AC 2.48832 GHz Complement of CKIN. Must be left open when internal VCO is used. 164 T17 HINTCLK Input PECL 38.88 MHz PECL hint clock to aid PLL acquistion. 176 M17 HCKOUT Output AC 2.48832 GHz High speed clock monitor. 30mVpp with a 50Ω load. 199 F17 CLKSEL Input Clock select signal for choosing between external or internal clock source as the active clock. NC =Internal VCO; VEE = External VCO. When external VCO is chosen, the internal VCO is forced to a fixed logic state even if powered. 12 B12 PHREF Output Analog Phase detector output. Requires external pull-up resistor to VDD. 11 B13 DCREF Output Analog Phase detector reference output. Requires external pull-up resistor to VDD. 183 J15 PHADJ Input Analog Phase detector static offset. Nominally at 2.1V. The full range of 2.1 +/- 0.625 V produces a -/+125 ps offset between the center of the data eye and the falling edge of the sampling clock. PHADJ has an internal default of 2.1V. 180 L17 VTUNEO Output Analog Internal PLL charge pump output. 194 F16 LOCK Output TTL Internal PLL lock detector. Remains high when frequency difference between internal and external reference clocks is less than 488 ppm. Accuracy of LOCK detect circuitry is related to the accuracy of the external HINTCLK. Can be tied to LOCKREF. 195 G17 LOCKREF Input TTL Forces internal PLL to lock to external reference clock when LOCKREF is low. 200 E15 PPMSEL Input TTL LOCK signal lower hysterisis level. When PPMSEL=VDD the LOCK signal will return to a high state when the frequency difference between the internal and external reference clocks is less than 122 ppm from HINTCLK. When PPMSEL=VEE the LOCK will return to a high state when the frequency difference is less than 30 ppm from HINTCLK. DC TELECOM PRODUCTS Pin No. Power Pins and Test Pins 202 D17 RSTN Input PECL Chip reset (active low) Normally tied to RESET. When not used must be tied to VDD through RTeΩ 201 E17 SLIP PECL Slips demultiplexer 1 Bit at each negative edge, can be used once every 3ns. When not used must be tied to VTT. 162 R16 PARSEL TTL When PARSEL=N.C. parity bits generated are even. When PARSEL=VEE parity bits generated are odd. SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET 9 TQ8223 PRELIMINARY DATA SHEET Table 1. Signal Description (continued) Pin No. Grid Ref. Signal Type and Freq. or Bit Rate Description 14 C11 RESET Input PECL High speed reset allows for multiple demux synchronization. Normally tied to RSTN. When not used must be tied to VDD through RTeΩ 159 U17 ID Output Analog Part level identification. Voltage at ID indicates device type. ID=##. 197 F14 TB_UPDN Factory Test For testing purposes only. Must be tied to VEE. 198 E16 TESTMODE Factory Test For testing purposes only. Must be tied to VEE. 24,25 A10,B10 CVDD Analog Power Supply Differential Data Input positive supply voltage 35,36 B7,C7 CVEE Analog Power Supply Differential Data Input supply return 187 H14 PLLVDD Analog Power Supply PLL positive supply voltage 188 H15 PLLVEE Analog Power Supply PLL supply return. Signal Description Pin Number,Grid Reference VDD Positive rail supply voltage 6,C14 74,H4 157,P14 207,C15 9,D12 94,M4 161,N14 208,C16 42,C6 109,P5 172,L14 48,D5 113,R5 173,L15 54,C3 114,P6 178,K15 55,D3 126,P8 192,G14 53,D4 158,R15 206,D14 IOVDD I/O Positive supply voltage 5,D13 10,B14 91,L4 80,J4 166,M14 177,K14 13,C12 132,T9 191,G15 21,C10 104,P3 203,E14 20,D10 120,P7 204,D15 62,F4 143,T12 103,P4 68,G4 146,P12 147,R12 VEE Negative rail supply voltage 105,R3 155,T15 205,D16 76,H2 106,T2 156,T16 1,B16 137,T10 112,U3 163,P16 2,C17 115,T4 128,T8 174,M16 184,J16 43,D6 51,A2 153,P13 102,P2 52,B2 154,R14 193,G16 61,E3 IOVEE I/O Negative supply voltage 101,N3 63,C1 93,M3 60,D2 129,U8 77,H1 138,U11 85,K4 150,R13 175,L16 15,D11 NC DO NOT CONNECT 3,B17 40,B6 75,H3 99,R2 127,R8 47,C4 39,A5 179,K16 16,A15 41,B5 86,L1 100,N4 148,T13 160,P15 38,D7 190,A17 17,A14 56,A1 92,L3 107,U1 149,T14 34,A7 4,A16 18,A13 57,E4 95,R1 108,U2 151,U15 144,U13 44,C5 19,A12 58,B1 96,M2 110,R4 152,U16 145,U14 45,A4 22,B11 59,C2 97,T1 111,T3 165,R17 186,H17 37,A6 23,A11 69,G3 98,N2 121,T6 196,F15 185,J17 189,H16 10 TQ8223 PRELIMINARY DATA SHEET Symbol Min Max Unit Supply voltage VDD-VEE GND 7.0 V Internal VCO Supply voltage VOSC VEE-0.5 VDD+0.5 V DIN,NDIN termination voltage VTD VEE-0.5 VDD+0.5 V VEE-0.5 VDD+0.5 V -55 150 oC Maximum Case Operating Temperature, Tc 125 oC Maximum junction temperature Tj 150 oC Electrostatic Discharge (100 pF, 1.5 kΩ) 1000 V Inputs/Outputs Storage Temperature Tstg TELECOM PRODUCTS Parameter SONET/SDH/ATM PRODUCTS Table 2. Absolute Maximum Ratings Table 3. DC Operating Ranges Signal VDD-VEE (Note 1) VOSC (Note 1) PLLVDD-PLLVEE (Note 1) VTD (Note 1) CVDD-CVEE (Note 1) Tc Notes: 1. 2. Symbol VDD-VEE Parameter Supply voltage range Internal VCO supply Vosc Iosc Supply current for internal VCO PVDD-PVEE PLL supply voltage IPLL Supply current for internal VCO VTD supply voltage range VTD VTD termination supply current (Note 2) ITD RTD DIN/NDIN Termination resistance CVDD-CVEE Input Comparator supply voltage IPLL Supply current for internal VCO Case temperature Min 4.75 Typ 5.00 Max 5.25 Units V - VDD 14 VDD - V mA V mA V mA Ω V mA oC - 40 VDD-2.8 45 - 50 VDD -40 30 55 20 125 No special power up sequence is required. VEE ,VTD at operating range. Table 4. Power Dissipation Low Speed Outputs VDD (V) Typ Power (W) Max Power (W) Open 5.0 3.12 3.48 Open 5.25 3.80 4.24 Fully Loaded 5.0 3.22 3.59 11 TQ8223 PRELIMINARY DATA SHEET Table 5. Recommended External Loop Filter Values REFCLK Frequency (MHz) Resistor Value R1 (Ω) Capacitor Value C1 (µF) Capacitor Value C2 (pF) 38.88 68 0.33 133 VTUNEO C1 C2 R1 PLLVDD Table 6. VCO Control Signal Specifications Signal VTUNEO Symbol Vrange KVCO frange Parameter VTUNEO voltage range (Note 1) VCO VTUNE voltage gain VCO frequency range when using internal PLL Notes: 1. A VTUNEO voltage of 2.5V corresponds to approximatey a 2.5GHz center frequency. Min Typ 2.5 500 1950 - 2700 Max Units V MHz/V MHz Nom (Note 1) Max Units Table 7. High Speed Signal Specification Signal Symbol Description Min CLKIN NCLKIN tcki tckdc Vamp Input clock period Input clock duty cycle Input clock differential peak to peak voltage 370.4 ps 401.88 ps 250 ns 40 50 60 1000 1200 1400 % mV HCKOUT tcko Vamp RTe High speed output clock period High speed output clock peak-to-peak voltage High speed output clock output impedance 10 45 ps mVpp Ω Note 1: All NOM specifications apply under the following conditions. Input data pattern: 223 -1 PRBS Input data rate: 2.48832 Gbps Input clock frequency: 2.48832 GHz Input data rise/fall time (20 %/80 %) >100 p 12 401.88 50 55 TQ8223 Table 8. Jitter Generation Performance Jitter Generation Nom CK155 JPP JRMS 6.2 0.84 Max Note: The method used is outlined in a Jitter Bench Application Note available upon request. The values listed as nominal were performed under the following conditions: Data Rate = 2.48832 Gb/s VDD = 5 V Tcase = 60 C Units ps ps TELECOM PRODUCTS Signal Table 9. Jitter Tolerence Performance Symbol Description Jtolerence The TQ8223 CDR exceeds the SONET/SDH Jitter Tolerence Template according to the figure below. Note: The method used to measure Jitter Tolerence is outlined in a Jitter Bench application note available upon request. Figure 4. Jitter Tolerence 30 15 UIpp 3.0 1.5 TQ8223 CDR 0.3 SONET/SDH Template 0.15 100 600 SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET 6k 100k Frequency (Hz) 1M 13 TQ8223 PRELIMINARY DATA SHEET Table 10. Jitter Transfer Performance Symbol Description Nom Max Units Jpeaking Peak Gain in Transfer Curve 0.05 0.1 dB fc Corner Frequency Transfer Curve 1.76 2.0 MHz Note: Jitter Transfer measurments were performed with the PLL loop filter values specified in Table 5. The method used is outlined in a Jitter Bench application note available upon request. The values listed as nominal were performed under the following conditions: VDD = 5 V Tcase = 60 C Figure 5. Typical Jitter Transfer Curve 0 -5 -10 Gain (dB) -15 SONET/SDH Template Transfer, 5.0V, 50C -20 -25 -30 -35 -40 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Frequency (Hz) 14 1.E+06 1.E+07 1.E+08 TQ8223 Signal Symbol Description DIN NDIN Vdp-p Vsens (N)DIN outer eye differential pk-pk amplitude (N)DIN data rate Data channel sensitivity (Note 1) 40 Voff (N)DIN differential offset voltage -25 Tdead Data channel dead band (Note 2) 125 ps Vhys Data channel hysteresis (Note 3) 5 mV Note 1: Note 2: Note 3: Note 4: Min Nom Max Units 1000 2.48832 1600 mVpp Gb/s mV +25 mV Measured as the minimum inner eye amplitude of the data signal at DIN that can be correctly regenerated. Input clock/data phase and Data decision threshold optimized for sensitivity. All specifications apply under the following conditions. Input data pattern: 223 -1 PRBS Input data rate: 2.48832 Gbps Input clock frequency: 2.48832 GHz Input data rise/fall time (20 %/80 %) >100 ps Measured as the input clock/data phase range over which errors can be detected at RQ11-18 in 1:8 mode. Specification applies under the following conditions: - input data amplitude: < 375mV mean1-mean0 - Input data rise/fall time (20 %/80 %) >100 ps Hysteresis is the difference in the decision threshold that results in error free operation of the channel when the decision threshold is first increased and then decreased and vice versa starting from a level that results in error free operation of the channel. The hysteresis specification applies for both the ‘1’ and ‘0’ signal levels. The DIN input conditions are the same as those listed in note 1 above. All amplitudes are differential peak-peak voltage 15 TELECOM PRODUCTS Table 11. Data Channel Specifications (Note 4) SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET TQ8223 PRELIMINARY DATA SHEET Table 12. TTL Interface Specifications Signal Symbol Description Min Nom Max Units CK78T tckdc tckr tckf Voh Vol Cload Output clock duty cycle (Note 3) Output clock rise time (20% to 80%) Output clock fall time (20% to 80%) Output clock high level Output clock low level Output load capacitance 40 50 60 2000 2000 VDD 0.4 % ps ps V V pF Tpd1 Tpd2 Voh Vol Ioh Iol Cload Output data delay 1 (Note 1) Output data hold time (Note 1) Output high voltage (Note 2) Output low voltage (Note 2) Output high-level output current Output low-level output current Output load capacitance 1.8 0 VDD 0.4 ns ns V V mA mA pF VDD 0.8 V V RQ11-18 RQ21-28 RQ31-38 RQ41-48 RQPAR1 RQPAR2 RQPAR3 RQPAR4 LOCK LOCKREF Vih PPMSEL Vil MODE(0:1) PARSEL Notes: 16 Input high level Inputt low level 2.4 VEE 20 2.4 VEE 50 -20 20 2.0 VEE 1.See Figure 6. Tpd1 and Tpd2 are specified relative to the falling edge of the CK78T signal. Output data edge jitter is not included in the specifications. The output data streams are assumed to be free of any skewing in time. The specifications apply under the following conditions: Output data rise/fall time: <= 2000ps (20% to 80%) Output data: 223-1 PRBS, 32x78Mb/s Output clock frequency: 77.76MHz 2.Output data level requirements apply under the following conditions: Output data: 223-1 PRBS, 32x78Mbit/s Output clock frequency: 77.76MHz 3.Output clock duty cycle is measured at the mean voltage of the signal and nominal input clock frequency of 2.48832GHz. TQ8223 Signal Symbol Description Min Nom(Note 4) CK311 NCK311 CK155 CK39 (Note 1) tckdc tckr tckf Voh Vol Vamp Output clock duty cycle (Note 2) Output clock rise time (20% to 80%) Output clock fall time (20% to 80%) Output clock high level Output clock low level Output clock amplitude (Note 3) 40 50 VDD-1.0 VTTe +/-350 - SLIP RESET RSNT HINTCLK Vih Vil tif tif Input high level Input low level Input fall time (20% to 80%) Input fall time (20% to 80%) Notes: 1.All specifications apply with signals terminated with RTe Ω to VTTe. 2.Output clock duty cycle is measured at the mean voltage of the signal and nominal input clock frequency of 2.48832 GHz. 3.The CK155 and CK39 clock output amplitude is measured with respect to the mean voltage of the signal. 4.All NOM specifications apply under the following conditions. Input data pattern: 223 -1 PRBS Input data rate: 2.48832 Gbps Input clock frequency: 2.48832 GHz Input data rise/fall time (20 %/80 %) >100 p VDD-1.05 VTTe Max Units 60 750 750 VDD-0.6 VDD-1.6 - % ps ps V V mV VDD-0.4 VDD-1.55 750 750 V V ps ps Figure 6 AC Timing: 77.76 Mb/s TTL Interface CK78T Tpd2 Tpd1 RQ11-18 RQ21-28 RQ31-38 RQ41-48 Valid Valid Data Data 17 TELECOM PRODUCTS Table 13. PECL Interface Specifications SONET/SDH/ATM PRODUCTS PRELIMINARY DATA SHEET TQ8223 PRELIMINARY DATA SHEET Figure 7. Output Clock Timing Relationships CK311 TCK155 CK155 TCK78 CK78 TCK39 CK39 Table 14. Output Clock Timing Relationships Symbol Description Typ TCK155 TCK78 TCK39 CK311 to CK155 timing relation 230 pS CK311 to CK78 timing relation 1400 pS CK311 to CK39 timing relation 700 pS 18 Max Units TQ8223 PRELIMINARY DATA SHEET SONET/SDH/ATM PRODUCTS Typical Application +2.2V N.C. or VEE (GND) VTD1 VTD2 DATINV PHADJ Phase control from DAC VDD VOSC RQ1(1:8) RQPAR1 RQ2(1:8) RQPAR2 RQ3(1:8) RQPAR3 RQ4(1:8) RQPAR4 CK78T(0:3) 77.76Mb/s TTL Interface DIN NDIN 2.48832Gb/s from AGC TELECOM PRODUCTS Figure 8. 1:32 Demultiplexing with Internal PLL VTUNE VTUNE0 LOCK 38.88MHz clock HINTCLK CKIN A.C. Terminated +5.0V VEE NCKIN VDD VEE 2.5GHz clock monitor 38.88MHz PECL clock HCKOUT CK39 CLKSEL MODE1 MODE0 N.C. VEE N.C. 19 TQ8223 PRELIMINARY DATA SHEET Figure 9. 1:32 Demultiplexing with Internal VCO and External PLL DIN NDIN +2.2V N.C. or VEE (GND) Phase control from DAC VTD1 VTD2 DATINV PHADJ ∫ Φe RQ1(1:8) RQPAR1 RQ2(1:8) RQPAR2 RQ3(1:8) RQPAR3 RQ4(1:8) RQPAR4 CK78T(0:3) 77.76Mb/s TTL Interface 2.48832Gb/s from AGC PHREF DCREF VDD VOSC VTUNE HCKOUT CK39 2.5GHz clock monitor 38.88MHz clock CKIN A.C. Terminated 38.88MHz clock +5.0V VEE 20 NCKIN HINTCLK VDD VEE RSTN CLKSEL MODE1 MODE0 N.C. VEE (GND) N.C. TQ8223 PRELIMINARY DATA SHEET Bottom view D D1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 Ball Corner 1 A B C D E F G H J K L M N P R T U A1 Ball I.D. Mark E1 E 45o 0.5mm Chamfer e e Note: Heat Spreader is at VDD volts. b A1 C Side View Section A P aaa Table 15. 208-pin BGA Dimensions Symbol Parameter Min Nom Max A Overall Thickness 1.45 1.55 1.65 A1 Ball Height 0.60 0.65 0.70 22.80 23.00 23.20 D Body Size D1 Ball Footprint E Body Size E1 Ball Footprint b Ball Diameter 0.65 0.75 0.85 c Body Thickness 0.85 0.90 0.95 aaa Seating Plane Clearance e Ball Pitch P Encapsulation Clearance 20.32 (BSC.) 22.80 23.00 23.20 20.32 (BSC.) 0.15 1.27 TYP. 0.15 Note: All dimensions in millimeters (mm) 21 TELECOM PRODUCTS Top view SONET/SDH/ATM PRODUCTS Figure 10. 208-pin BGA Mechanical Dimensions TQ8223 PRELIMINARY DATA SHEET The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1999 TriQuint Semiconductor, Inc. All rights reserved. Revision 0.2.A 22 August 1999