TSH321 WIDE BANDWIDTH AND MOS INPUT SINGLE OPERATIONAL AMPLIFIER ■ ■ ■ ■ ■ ■ LOW DISTORTION GAIN BANDWIDTH PRODUCT : 300MHz GAIN OF 2 STABILITY SLEW RATE : 400V/µs VERY FAST SETTLING TIME : 60ns (0.1%) VERY HIGH INPUT IMPEDANCE DESCRIPTION The TSH321 is a wideband monolithic operational amplifier, requiring a minimum close loop gain of 2 for stability. The TSH321 features extremely high input impedance (typically greater than 1012Ω) allowing direct interfacing with high impedance sources. Low distortion, wide bandwidth and high linearity make this amplifier suitable for RF and video applications. Short circuit protection is provided by an internal current-limiting circuit. The TSH321 has internal electrostatic discharge (ESD) protection circuits and fulfills MILSTD883C-Class2. ORDER CODE Package Part Number D SO8 (Plastic Micropackage) PIN CONNECTIONS (top view) Offset Null 1 1 8 Inverting Input 2 7 VCC+ Non-inverting Input 3 6 Output 4 5 N.C. V CC Offset Null 2 Temperature Range D TSH321I -40°C, +125°C • D = Small Outline Package (SO) - also available in Tape & Reel (DT) October 2000 1/5 TSH321 SCHEMATIC DIAGRAM 7 VCC + Internal Vref non inverting input 3 6 output Cc 2 inverting input 1 Offset N1 8 Offset N2 4 VCC- INPUT OFFSET VOLTAGE NULL CIRCUIT TSH321 N2 N1 100kΩ V CC MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage ±7 V Vid Differential Input Voltage ±5 V Vi Input Voltage ±5 V Iin Current On Offset Null Pins ±20 V -40 to +125 °C Value Unit Toper Operating Free-Air Temperature range OPERATING CONDITIONS Symbol VCC Vic 2/5 Parameter Supply Voltage ±3 to ±6 V Common Mode Input Voltage Range - V + VCC to VCC -3 TSH321 ELECTRICAL CHARACTERISTICS VCC = ±5V, Tamb = 25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 0.5 10 12 mV Vio Input Offset Voltage Tmin. ≤ Tamb ≤ Tmax DVio Input Offset Voltage Drift Tmin. ≤ Tamb ≤ Tmax. 10 Iib Input Bias Current. 2 300 pA Iio Input Offset Current. 2 200 pA 23 21 25 30 28 40 32 µV/°C Supply Current, no load ICC Tmin. ≤ Tamb ≤ Tmax Avd Vicm VCC = VCC = VCC = VCC = ±5V ±3V ±6V ±5V Large Signal Voltage Gain Vo = ±2.5V RL = ∝ RL = 100Ω RL = 50Ω mA 800 300 200 1300 850 650 -5 to +2 -5.5 to +2.5 V 60 100 dB 50 70 dB RL = 100Ω ±3 RL = 50Ω ±2.8 +3.5 -3.7 +3.3 -3.5 RL = 100Ω RL = 50Ω ±2.9 ±2.7 CMR Input Common Mode Voltage Range Common-mode Rejection Ratio Vic = Vicm min. SVR Supply Voltage Rejection Ratio VCC = ±5V to ±3V V/V Output Voltage Vo Tmin. ≤ Tamb ≤ Tmax Io GBP SR Output Short Circuit Current Vid = ±1V, Vo = 0V Gain Bandwidth Product AVCL = 100, RL = 100Ω, CL = 15pF, f = 7.5MHz ±50 Slew Rate Vin = ±1V, AVCL = 2, RL = 100Ω, CL = 15pF 200 ±100 300 400 V mA MHz V/µs Equivalent Input Voltage Noise Rs = 50Ω fo = 1kHz fo = 1k0Hz fo = 100kHz fo = 1MHz en Kov Overshoot Vin = ±1V, AVCL = 2, RL = 100Ω, CL = 15pF 20 18.2 18.1 18.2 15 60 Rise and Fall Time (see note 1) Vin = ±100mV, AVCL = 2 2 Delay Time (see note 1) Vin = ±100mV, AVCL = 2 2 φm Phase Margin AVM = 2, RL = 100Ω, CL = 15pF 45 THD Total Harmonic Distortion AVCL = 10, f = 1kHz, Vo = ±2.5V, no load 0.02 FPB Full Power Bandwidth 2) Vo = 5Vpp, RL = 100Ω Vo = 2Vpp, RL = 100Ω tr, tf td % 1) Settling Time 0.1% Vin = ±1V, AVCL = -1 ts nV/√Hz 1. See test waveform figure 2. Full power bandwidth = 26 64 ns ns ns Degrees % MHz SR -------------------Π V opp 3/5 TSH321 TEST WAVEFORM EVALUATION CIRCUIT +5V 10µF 50Ω 10nF Input ts 90% 50% 50Ω 0.1% of edge amplitude Output 1kΩ 10nF td tr 10% Vin -5V 10µF 1kΩ CF PRINTED CIRCUIT LAYOUT As for any high frequency device, a few rules must be observed when designing the PCB to get the best performances from this high speed op amp. From the most to the least important points : ❑ Each power supply lead has to be bypassed to ground with a 10nF ceramic capacitor very close to the device and a 10µF tantalum capacitor. ❑ To provide low inductance and low resistance common return, use a ground plane or common point return for power and signal. ❑ All leads must be wide and as short as possible especially for op amp inputs. This is in 4/5 order to decrease parasitic capacitance and inductance. ❑ Use small resistor values to decrease time constant with parasitic capacitance. ❑ Choose component sizes as small as possible (SMD). ❑ On output, decrease capacitor load so as to avoid circuit stability being degraded which may cause oscillation. You can also add a serial resistor in order to minimise its influence. ❑ One can add in parallel with feedback resistor a few pF ceramic capacitor CF adjusted to optimize the settling time. TSH321 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) Millimeters Inches Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S Typ. Max. 0.65 0.35 0.19 0.25 1.75 0.25 1.65 0.85 0.48 0.25 0.5 4.8 5.8 5.0 6.2 0.1 Min. Typ. Max. 0.026 0.014 0.007 0.010 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.189 0.228 0.197 0.244 0.004 45° (typ.) 1.27 3.81 3.8 0.4 0.050 0.150 4.0 1.27 0.6 0.150 0.016 0.157 0.050 0.024 8° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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