ETC BUV48/D

ON Semiconductor
BUV48
BUV48A
SWITCHMODE II Series
NPN Silicon Power Transistors
The BUV48/BUV48A transistors are designed for high–voltage,
high–speed, power switching in inductive circuits where fall time is
critical. They are particularly suited for line–operated
SWITCHMODE applications such as:
•
•
•
•
•
•
•
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15 AMPERES
NPN SILICON
POWER TRANSISTORS
400 AND 450 VOLTS
V(BR)CEO
850–1000 VOLTS
V(BR)CEX
150 WATTS
Switching Regulators
Inverters
Solenoid and Relay Drivers
Motor Controls
Deflection Circuits
Fast Turn–Off Times
60 ns Inductive Fall Time — 25C (Typ)
120 ns Inductive Crossover Time — 25C (Typ)
Operating Temperature Range –65 to +175C
100C Performance Specified for:
Reverse–Biased SOA with Inductive Loads
Switching Times with Inductive Loads
Saturation Voltage
Leakage Currents (125C)
CASE 340D–02
TO–218 TYPE
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MAXIMUM RATINGS
Rating
Symbol
BUV48
BUV48A
Unit
VCEO(sus)
400
450
Vdc
Collector–Emitter Voltage (VBE = –1.5 V)
VCEX
850
1000
Vdc
Emitter Base Voltage
VEB
7
Vdc
Collector Current — Continuous
— Peak (1)
— Overload
IC
ICM
IOI
15
30
60
Adc
Base Current — Continuous
— Peak (1)
IB
IBM
5
20
Adc
Total Power Dissipation — TC = 25C
— TC = 100C
Derate above 25C
PD
150
75
1
Watts
TJ, Tstg
–65 to +175
C
Symbol
Max
Unit
RθJC
1
C/W
TL
275
C
Collector–Emitter Voltage
Operating and Storage Junction Temperature Range
W/C
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
Maximum Lead Temperature for Soldering Purposes:
1/8″ from Case for 5 Seconds
(1) Pulse Test: Pulse Width = 5 ms, Duty Cycle 10%.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 10
1
Publication Order Number:
BUV48/D
BUV48 BUV48A
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
400
450
—
—
—
—
—
—
—
—
0.2
2
—
—
—
—
0.5
0
5
3
IEBO
—
—
0.1
mAdc
V(BR)EBO
7
—
—
Vdc
OFF CHARACTERISTICS (1)
Collector–Emitter Sustaining Voltage (Table 1)
(IC = 200 mA
mA, IB = 0) L = 25 mH
VCEO(sus)
BUV48
BUV48A
Collector Cutoff Current
(VCEX = Rated Value, VBE(off) = 1.5 Vdc)
(VCEX = Rated Value, VBE(off) = 1.5 Vdc, TC = 125C)
Collector Cutoff Current
(VCE = Rated VCEX, RBE = 10 Ω)
Vdc
ICEX
mAdc
ICER
TC = 25C
TC = 125C
Emitter Cutoff Current
(VEB = 5 Vdc, IC = 0)
Emitter–Base Breakdown Voltage
(IE = 50 mA – IC = 0)
mAdc
SECOND BREAKDOWN
Second Breakdown Collector Current with Base Forward Biased
Clamped Inductive SOA with Base Reverse Biased
IS/b
See Figure 12
RBSOA
See Figure 13
ON CHARACTERISTICS (1)
DC Current Gain
(IC = 10 Adc, VCE = 5 Vdc)
(IC = 8 Adc, VCE = 5 Vdc)
hFE
8
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
5
2
1.5
5
2
—
—
—
—
—
—
—
—
1.6
1.6
1.6
1.6
Cob
—
—
350
pF
td
—
0.1
0.2
µs
BUV48
BUV48A
Collector–Emitter Saturation Voltage
(IC = 10 Adc, IB = 2 Adc)
(IC = 15 Adc, IB = 3 Adc)
(IC = 10 Adc, IB = 2 Adc, TC = 100C)
(IC = 8 Adc, IB = 1.6 Adc)
(IC = 12 Adc, IB = 2.4 Adc)
(IC = 8 Adc, IB = 1.6 Adc, TC = 100C)
VCE(sat)
BUV48
BUV48A
Base–Emitter Saturation Voltage
(IC = 10 Adc, IB = 2 Adc)
(IC = 10 Adc, IB = 2 Adc, TC = 100C)
(IC = 8 Adc, IB = 1.6 Adc)
(IC = 8 Adc, IB = 1.6 Adc, TC = 100C)
Vdc
VBE(sat)
BUV48
BUV48A
Vdc
DYNAMIC CHARACTERISTICS
Output Capacitance
(VCB = 10 Vdc, IE = 0, ftest = 1 MHz)
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
Rise Time
Storage Time
Fall Time
IC = 10 A
A, IB, = 2 A
IC = 8 A, IB, = 1.6 A
Duty Cycle 2%, VBE(off) = 5 V
Tp = 30 µs,
µs VCC = 300 V
BUV48
BUV48A
tr
—
0.4
0.7
ts
—
1.3
2
tf
—
0.2
0.4
tsv
—
1.3
—
tfi
—
0.06
—
tsv
—
1.5
2.5
tc
—
0.3
0.6
tfi
—
0.17
0.35
Inductive Load, Clamped (Table 1)
Storage Time
Fall Time
IC = 10 A
IB1 = 2 A
BUV48
IC = 8 A
IB1 = 1.6 A
BUV48A
(TC = 25C)
Storage Time
Crossover Time
(TC = 100C)
Fall Time
(1) Pulse Test: Pulse Width = 300 µs, Duty Cycle 2%.
Vcl = 300 V, VBE(off) = 5 V, Lc = 180 µH
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2
µs
BUV48 BUV48A
50
90%
hFE, DC CURRENT GAIN
30
20
10%
10
7
5
3
2
VCE = 5 V
1
2
1
3
5
8 10
20
IC, COLLECTOR CURRENT (AMPS)
30
50
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
DC CHARACTERISTICS
10
5
3
7.5 A
0.5
0.3
0.1
0.1
VBE, BASE-EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
90%
2
10%
1
0.7
0.5
0.3
0.2
0.1
1
2
3
5
7
10
20
30
50
2
3
4
βf = 5
2
TJ = 25°C
1
0.7
TJ = 100°C
0.5
0.3
0.3
1
3
IC, COLLECTOR CURRENT (AMPS)
IC, COLLECTOR CURRENT (AMPS)
Figure 3. Collector–Emitter Saturation Voltage
Figure 4. Base–Emitter Voltage
10
10 k
VCE = 250 V
Cib
103
C, CAPACITANCE (pF)
IC, COLLECTOR CURRENT (A)
µ
1
0.3
0.5
IB, BASE CURRENT (AMPS)
0.1
104
TJ = 150°C
102
101
TC = 25°C
Figure 2. Collector Saturation Region
βf = 5
3
15 A
IC = 5 A
1
Figure 1. DC Current Gain
5
10 A
125°C
100°C
REVERSE
FORWARD
75°C
1k
Cob
100
100
25°C
10-1
-0.4
TJ = 25°C
-0.2
0
0.2
0.4
VBE, BASE-EMITTER VOLTAGE (VOLTS)
10
0.6
1
10
100
VR, REVERSE VOLTAGE (VOLTS)
Figure 6. Capacitance
Figure 5. Collector Cutoff Region
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3
1000
BUV48 BUV48A
Table 1. Test Conditions for Dynamic Performance
INPUT
CONDITIONS
VCEO(sus)
+10 V
RBSOA AND INDUCTIVE SWITCHING
33
2W
1
20
220
100
Lcoil = 180 µH
Rcoil = 0.05 Ω
VCC = 20 V
D4
160
D3
SEE ABOVE FOR
DETAILED CONDITIONS
Rcoil
1N4937
OR
EQUIVALENT
IC(pk)
t1
VCE or
VCC = 300 V
RL = 83 Ω
Pulse Width = 10 µs
t2 ≈
Vclamp
t
t2
Lcoil (IC
TUT
)
pk
VCC
Lcoil (IC
RL
1
2
)
pk
VCC
VClamp
Test Equipment
Scope — Tektronix
475 or Equivalent
10
IC pk
IB2(pk) , BASE CURRENT (AMPS)
VCE(pk)
90% VCE(pk)
90% IC(pk)
trv
tfi
tti
tc
10% VCE(pk)
90% IB1
t
tf
TIME
VCE
t1 ≈
VCE
VCC
RS =
0.1 Ω
tsv
VCC
RESISTIVE TEST CIRCUIT
tf Clamped
Lcoil
Vclamp
TURN–OFF TIME
Use inductive switching
driver as the input to
the resistive test circuit.
2N6339
t1 Adjusted to
Obtain IC
IC
INPUT
IB1 adjusted to
obtain the forced
hFE desired
OUTPUT WAVEFORMS
TUT
2
IB
0.22 µF
Ib2 ADJUST
dTb ADJUST
dT
MR854
Vclamp = 300 V
RB ADJUSTED TO ATTAIN DESIRED IB1
INDUCTIVE TEST CIRCUIT
IC
22
2N3763
33
2W
Lcoil = 25 mH, VCC = 10 V
Rcoil = 0.7 Ω
1
Ib1 ADJUST
0.1 µF
2
IB1
22
680 pF
680 pF
1
MR854
D1D2D3D4 1N4934
PULSES
δ = 3%
TURN–ON TIME
2N6438
D3
680 pF
PW Varied to Attain
IC = 200 mA
TEST CIRCUITS
160
MM3735
0
2
CIRCUIT
VALUES
100
+10 V
22 µF
D1
RESISTIVE SWITCHING
10%
IC pk
2% IC
6
4
2
0
TIME
βf = 5
IC = 10 A
8
0
1
2
3
4
5
VBE(off), BASE-EMITTER VOLTAGE (VOLTS)
Figure 7. Inductive Switching Measurements
Figure 8. Peak–Reverse Current
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4
6
BUV48 BUV48A
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
tsv
trv
tfi
tti
tc
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN–222:
PSWT = 1/2 VCCIC(tc) f
In general, trv + tfi tc. However, at lower test currents
this relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive
switching speeds (tc and tsv) which are guaranteed at 100C.
= Voltage Storage Time, 90% IB1 to 10% Vclamp
= Voltage Rise Time, 10–90% Vclamp
= Current Fall Time, 90–10% IC
= Current Tail, 10–2% IC
= Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the inductive switching
waveforms is shown in Figure 7 to aid in the visual identity
of these terms.
INDUCTIVE SWITCHING
1
5
3
0.5
2
t, TIME (s)
µ
t, TIME (s)
µ
TC = 25°C
1
0.7
0.5
0.3
TC = 100°C
TC = 25°C
0.2
0.1
TC = 25°C
0.05
0.03
0.2
2
1
tc
tfi
0.02
βf = 5
0.1
TC = 100°C
0.3
TC = 100°C
3
5
7
10
20
IC, COLLECTOR CURRENT (AMPS)
0.01
50
30
βf = 5
1
2
Figure 9. Storage Time, tsv
3
2
tsv
1
1
0.5
0.5
0.3
0.2
tc
0.1
tfi
0.05
0.01
TC = 25°C
IC = 10 A
VBE(off) = 5 V
0
1
2
3
6
4
5
βf, FORCED GAIN
7
50
8
9
TC = 25°C
IC = 10 A
βf = 5 V
tsv
0.3
0.2
tc
0.1
tfi
0.05
0.03
0.02
30
Figure 10. Crossover and Fall Times
t, TIME (s)
µ
t, TIME (s)
µ
3
2
3
5
7
10
20
IC, COLLECTOR CURRENT (AMPS)
0.03
0.02
0.01
10
0
Figure 11. Turn–Off Times versus Forced Gain
1
2
3
4
5
Ib2/Ib1
6
7
8
9
Figure 12. Turn–Off Times versus Ib2/Ib1
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5
10
BUV48 BUV48A
IC, COLLECTOR CURRENT (AMPS)
The Safe Operating Area figures shown in Figures 12 and 13
are specified for these devices under the test conditions
shown.
30
10
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC – VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 13 is based on TC = 25C; TJ(pk) is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when TC 25C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 13 may be found at
any case temperature by using the appropriate curve on
Figure 15.
TJ(pk) may be calculated from the data in Figure 11. At
high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations
imposed by second breakdown.
1 ms
5
DC
2
1
0.5
0.2
TC = 25°C
0.1
LIMIT ONLY
FOR TURN ON
0.05
tr ≤ 0.7 µs
0.02
0.01
1
2
500 1000
5
10 20
50
100 200
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 13. Forward Bias Safe Operating Area
REVERSE BIAS
For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage current conditions during reverse
biased turn–off. This rating is verified under clamped
conditions so that the device is never subjected to an
avalanche mode. Figure 14 gives RBSOA characteristics.
40
30
BUV48
BUV48A
20
VBE(off) = 5 V
10
0
TC = 100°C
IC/IB ≥ 5
0
200
400
600
800
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
1000
Figure 14. Reverse Bias Safe Operating Area
100
POWER DERATING FACTOR (%)
IC, COLLECTOR CURRENT (AMPS)
50
SECOND BREAKDOWN
DERATING
80
60
THERMAL DERATING
40
20
0
0
40
80
120
TC, CASE TEMPERATURE (°C)
Figure 15. Power Derating
http://onsemi.com
6
160
200
BUV48 BUV48A
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
1
D = 0.5
0.5
0.2
0.2
0.1
0.1
RθJC(t) = r(t) RθJC
θJC = 1°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RθJC(t)
0.05
0.02
0.05
0.01
SINGLE PULSE
0.02
0.01
0.02
0.1
0.05
0.2
0.5
1
2
5
10
t, TIME (ms)
20
50
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
100
200
500
1000
2000
Figure 16. Thermal Response
OVERLOAD CHARACTERISTICS
100
OLSOA
OLSOA applies when maximum collector current is
limited and known. A good example is a circuit where an
inductor is inserted between the transistor and the bus, which
limits the rate of rise of collector current to a known value.
If the transistor is then turned off within a specified amount
of time, the magnitude of collector current is also known.
Maximum allowable collector–emitter voltage versus
collector current is plotted for several pulse widths. (Pulse
width is defined as the time lag between the fault condition
and the removal of base drive.) Storage time of the transistor
has been factored into the curve. Therefore, with bus voltage
and maximum collector current known, Figure 17 defines
the maximum time which can be allowed for fault detection
and shutdown of base drive.
OLSOA is measured in a common–base circuit (Figure
19) which allows precise definition of collector–emitter
voltage and collector current. This is the same circuit that is
used to measure forward–bias safe operating area.
IC, COLLECTOR CURRENT (AMPS)
TC = 25°C
80
BUV48A
60
tp = 10 µs
40
BUV48
20
0
200
100
300
400 450
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
500
Figure 17. Rated Overload Safe Operating Area
(OLSOA)
5
IC (AMP)
4
3
500 µF
500 V
RBE = 100 Ω
RBE = 2.2 Ω
RBE = 10 Ω
2
1
Notes:
• VCE = VCC + VBE
• Adjust pulsed current source
for desired IC, tp
RBE = 0
0
2
4
6
dV/dt (KV/µs)
8
VCC
VEE
10
Figure 19. Overload SOA Test Circuit
Figure 18. IC = f(dV/dt)
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7
BUV48 BUV48A
PACKAGE DIMENSIONS
SOT–93 (TO–218)
CASE 340D–02
ISSUE B
C
Q
B
U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
E
4
DIM
A
B
C
D
E
G
H
J
K
L
Q
S
U
V
A
L
1
K
2
3
D
J
H
MILLIMETERS
MIN
MAX
--20.35
14.70
15.20
4.70
4.90
1.10
1.30
1.17
1.37
5.40
5.55
2.00
3.00
0.50
0.78
31.00 REF
--16.20
4.00
4.10
17.80
18.20
4.00 REF
1.75 REF
INCHES
MIN
MAX
--0.801
0.579
0.598
0.185
0.193
0.043
0.051
0.046
0.054
0.213
0.219
0.079
0.118
0.020
0.031
1.220 REF
--0.638
0.158
0.161
0.701
0.717
0.157 REF
0.069
V
G
SWITCHMODE is a registered trademark of Semiconductor Components Industries, LLC (SCILLC)
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BUV48/D