DATA SHEET MOS INTEGRATED CIRCUIT µPD780065 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD780065 is a product of the µPD780065 Subseries in the 78K/0 Series. It is ideal for controlling CDTEXT supporting audio equipment. Since it incorporates 5 KB of RAM, it is also ideal for control operations that require memory. A flash memory version (µPD78F0066) that can be operated using the same power supply voltage range as that of the mask ROM version as well as a variety of development tools are also available. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780065 Subseries User’s Manual: U13420E 78K/0 Series User’s Manual Instructions: U12326E FEATURES • • • • • • • • Internal ROM: 40 KB Internal high-speed RAM: 1024 bytes Internal expansion RAM: 4096 bytes Buffer RAM: 32 bytes Minimum instruction execution time can be changed from high speed (0.24 µ s) to ultra-low speed (122 µs). I/O ports: 60 8-bit resolution A/D converter: 8 channels Serial interface: 4 channels • 3-wire serial I/O mode: 1 channel • 3-wire serial I/O mode (a maximum 32-byte automatic transmit/receive function is incorporated.): 1 channel • 2-wire serial I/O mode: 1 channel • UART mode: 1 channel • Timer: 5 channels • 16-bit timer/event counter: 1 channel • 8 bit timer/event counter: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel • Power supply voltage: VDD = 2.7 to 5.5 V APPLICATIONS CD-TEXT supported car audios The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13732EJ1V0DS00 (1st edition) Date Published April 2001 N CP(K) Printed in Japan The mark shows major revised points. 1998 µPD780065 ORDERING INFORMATION Part Number Package µ PD780065GC-×××-8BT 80-pin plastic QFP (14 × 14) Remark ××× indicates ROM code suffix. 2 Data Sheet U13732EJ1V0DS µPD780065 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin µ PD78075B µ PD78078 µ PD78070A 100-pin 80-pin 80-pin µ PD780058 µ PD78058F 80-pin µPD78054 µPD780065 64-pin µ PD780078 64-pin 64-pin 64-pin µ PD780034A µ PD780024A µPD78014H 64-pin 42-/44-pin µPD78018F µ PD78083 64-pin µPD780988 80-pin EMI-noise reduced version of the µPD78078 µPD78078Y µPD78054 with added timer and enhanced external interface µ PD78070AY ROM-less version of the µPD78078 µPD78078Y with enhanced serial I/O and limited function µ PD780018AY µ PD780058Y µ PD78058FY µPD78054 with enhanced serial I/O EMI-noise reduced version of the µ PD78054 µPD78018F with added UART and D/A converter and enhanced I/O RAM capacity of the µ PD780024A increased µPD780034A with added timer and enhanced serial I/O µ PD780078Y µ PD780034AY µPD780024A with enhanced A/D converter µ PD780024AY µPD78018F with enhanced serial I/O EMI-noise reduced version of the µPD78018F µ PD78054Y µ PD78018FY Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control On-chip inverter controller and UART. EMI-noise reduced. VFD drive 78K/0 Series 100-pin µ PD780208 µPD78044F with enhanced I/O and VFD C/D. Display output total: 53 80-pin µ PD780232 µPD78044H For panel control. On-chip VFD and C/D. Display output total: 53 80-pin 80-pin µPD78044F Basic subseries for VFD drive. Display output total: 34 µPD78044F with added N-ch open-drain I/O. Display output total: 34 LCD drive 120-pin µ PD780338 120-pin µ PD780328 µPD780318 µ PD780308 µPD78064B µPD78064 120-pin 100-pin 100-pin 100-pin µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. µPD780308Y µ PD78064 with enhanced SIO, and increased ROM, RAM capacity EMI-noise reduced version of the µ PD78064 µ PD78064Y Basic subseries for LCD drive, on-chip UART Bus interface supported 100-pin 80-pin µ PD780948 µ PD78098B On-chip D-CAN controller µPD78054 with added IEBusTM controller. EMI-noise reduced. 80-pin µ PD780701Y On-chip D-CAN/IEBus controller 80-pin µ PD780833Y On-chip controller compliant with J1850 (Class 2) Meter control 100-pin µPD780958 For industrial meter control 80-pin µPD780852 µPD780824 On-chip automobile meter controller/driver For automobile meter driver. On-chip D-CAN controller 80-pin Remark VFD (Vacuum Fluorescent Display) is referred to as FIP™ (Fluorescent Indicator Panel) in some documents, but the functions of the two are same. Data Sheet U13732EJ1V0DS 3 µPD780065 The major functional differences between the subseries are listed below. Function Subseries Name Control Timer ROM Capacity 8-Bit 10-Bit 8-Bit 8-Bit 16-Bit Watch WDT A/D µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch µPD78078 µPD78070A A/D — Serial Interface D/A 2 ch 3 ch (UART: 1 ch) I/O VDD External MIN. Expansion Value 88 1.8 V 48 K to 60 K 61 2.7 V µPD780058 24 K to 60 K 2 ch 3 ch (time division UART: 1 ch) 68 1.8 V µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 2.7 V µPD78054 √ — 69 16 K to 60 K 2.0 V µPD780065 40 K to 48 K — µPD780078 48 K to 60 K 2 ch µPD780034A 8 K to 32 K 1 ch — µPD780024A 8 ch 8 ch 4 ch (UART: 1 ch) 60 2.7 V 3 ch (UART: 2 ch) 52 1.8 V 3 ch (UART: 1 ch) 51 2 ch 53 1 ch (UART: 1 ch) 33 — µPD78014H µPD78018F 8 K to 60 K µPD78083 Inverter control 8 K to 16 K — µPD780988 16 K to 60 K 3 ch Note — — 1 ch — VFD drive µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch µPD780232 16 K to 24 K 3 ch — — 8 ch — 3 ch (UART: 2 ch) 47 4.0 V √ — — 2 ch 74 2.7 V — 40 4.5 V 1 ch 68 2.7 V 54 1.8 V 4 ch µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch µPD78044F 16 K to 40 K 2 ch LCD drive µPD780338 48 K to 60 K 3 ch 2 ch 1 ch 1 ch — 10 ch 1 ch 2 ch (UART: 1 ch) µPD780328 70 µPD780308 48 K to 60 K 2 ch 1 ch 8 ch — — µPD78064B 32 K 2.0 V 16 K to 32 K µPD780958 48 K to 60 K 4 ch 2 ch — 1 ch — Dash board µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch control µPD780824 32 K to 60 K — — 3 ch (UART: 1 ch) 2 ch 79 4.0 V √ 69 2.7 V — — — 2 ch (UART: 1 ch) 69 2.2 V — — — 3 ch (UART: 1 ch) 56 4.0 V — 2 ch (UART: 1 ch) 59 Note 16-bit timer: 2 channels 10-bit timer: 1 channel 4 3 ch (Time division UART: 1 ch) 57 2 ch (UART: 1 ch) Bus interface µPD780948 60 K 2 ch 2 ch 1 ch 1 ch 8 ch supported µPD78098B 40 K to 60 K 1 ch Meter control — 62 µPD780318 µPD78064 — Data Sheet U13732EJ1V0DS µPD780065 OVERVIEW OF FUNCTIONS Item Internal memory Function ROM 40 KB High-speed RAM 1024 bytes Expansion RAM 4096 bytes Buffer RAM 32 bytes Memory space 64 KB General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time On-chip minimum instruction execution time variable function When main system clock selected 0.24 µs/0.48 µ s/0.95 µ s/1.91 µs/3.81 µ s (at 8.38 MHz operation) When subsystem clock selected 122 µs (at 32.768 kHz operation) Instruction set • • • • I/O ports CMOS I/O: 60 A/D converter 8-bit resolution × 8 channels Serial interface • 3-wire serial I/O mode: 1 channel • 3-wire serial I/O mode (MAX. 32-byte on-chip automatic transmission/ reception function): 1 channel • 2-wire serial I/O mode: 1 channel • UART mode: 1 channel Timer • • • • Timer outputs 3 (8-bit PWM output capable: 2) Clock output 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (main system clock: at 8.38 MHz operation) 32.768 kHz (subsystem clock: at 32.768 kHz operation) Vectored interrupt Maskable sources Non-maskable Internal: 14, external: 4 Software 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD correction, etc. 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 channel channels channel channel Internal: 1 1 Power supply voltage VDD = 2.7 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package 80-pin plastic QFP (14 × 14) Data Sheet U13732EJ1V0DS 5 µPD780065 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................ 7 2. BLOCK DIAGRAM ........................................................................................................................... 9 3. PIN FUNCTIONS .............................................................................................................................. 10 3.1 Port Pins .................................................................................................................................................. 10 3.2 Non-Port Pins .......................................................................................................................................... 11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 13 4. MEMORY SPACE .............................................................................................................................. 15 5. FEATURES OF PERIPHERAL HARDWARE .................................................................................... 16 5.1 Ports ......................................................................................................................................................... 16 5.2 Clock Generator ...................................................................................................................................... 16 5.3 Timer/Event Counter ............................................................................................................................... 17 5.4 Clock Output Controller ......................................................................................................................... 21 5.5 A/D Converter .......................................................................................................................................... 22 5.6 Serial Interface ........................................................................................................................................ 23 6. INTERRUPT FUNCTIONS ............................................................................................................... 28 7. EXTERNAL DEVICE EXPANSION FUNCTION .............................................................................. 31 8. STANDBY FUNCTION ..................................................................................................................... 31 9. RESET FUNCTION .......................................................................................................................... 31 10. INSTRUCTION SET ......................................................................................................................... 32 11. ELECTRICAL SPECIFICATIONS .................................................................................................... 34 12. PACKAGE DRAWING...................................................................................................................... 54 13. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 55 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 56 APPENDIX B. RELATED DOCUMENTS .............................................................................................. 59 6 Data Sheet U13732EJ1V0DS µPD780065 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14) AVSS P84/SI1 P83/SO1 P82/SCK1 P81/BUSY P80/STB P77 P76 P75/SDIO30 P74/SCK30 P73/RxD0 P72/TxD0 P71/ASCK0 P70/PCL P64/RD P65/WR P66/WAIT P67/ASTB P40/AD0 P41/AD1 µPD780065GC-×××-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 AVREF RESET XT1 XT2 IC X1 X2 VDD1 VSS1 P90/SCK31 P91/SO31 P92/SI31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VDD0 VSS0 P37 P36 P35 P34 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04 P05 P06 P07 P20/TI00/TO0 P21/TI01 P22/TI50/TO50 P23/TI51/TO51 P24 P25 P26 P27 P30 P31 P32 P33 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Cautions 1. Connect the IC (internally connected) pin directly to V SS0 or VSS1. 2. Connect the AV SS pin to VSS0 . Remark When the µPD780065 is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting V SS0 and VSS1 to different ground lines, is recommended. Data Sheet U13732EJ1V0DS 7 µPD780065 A8 to A15: Address bus PCL: Programmable clock AD0 to AD7: Address/data bus RD: Read strobe ANI0 to ANI7: Analog input RESET: Reset ASCK0: Asynchronous serial clock RxD0: Receive data ASTB: Address strobe SCK1, SCK30, SCK31: Serial clock AVREF: Analog reference voltage SDIO30: Serial data input/output AVSS : Analog ground SI1, SI31: Serial input BUSY: Busy SO1, SO31: Serial output IC: Internally connected STB: Strobe INTP0 to INTP3: External interrupt input TI00, TI01, TI50, TI51: Timer input P00 to P07: Port 0 TO0, TO50, TO51: Timer output P20 to P27: Port 2 TxD0: Transmit data P30 to P37: Port 3 VDD0, V DD1: Power supply P40 to P47: Port 4 VSS0 , VSS1 : Ground P50 to P57: Port 5 WAIT: Wait P64 to P67: Port 6 WR: Write strobe P70 to P77: Port 7 X1, X2: Crystal (main system clock) P80 to P84: Port 8 XT1, XT2: Crystal (subsystem clock) P90 to P92: Port 9 8 Data Sheet U13732EJ1V0DS µPD780065 2. BLOCK DIAGRAM TI00/TO0/P20 TI01/P21 16-bit timer/ event counter Port 0 P00 to P07 TI50/TO51/P22 8-bit timer/ event counter 50 Port 2 P20 to P27 TI51/TO51/P23 8-bit timer/ event counter 51 Port 3 P30 to P37 Watchdog timer Port 4 P40 to P47 Watch timer Port 5 P50 to P57 Port 6 P64 to P67 Port 7 P70 to P77 Port 8 P80 to P84 Port 9 P90 to P92 SI1/P84 SO1/P83 SCK1/P82 BUSY/P81 STB/P80 SDIO30/P75 SCK30/P74 78K/0 CPU core ROM (40 KB) Serial interface 1 Serial interface 30 SI31/P92 SO31/P91 SCK31/P90 Serial interface 31 RxD0/P73 TxD0/P72 ASCK0/P71 UART0 RAM (5 KB) AD0/P40 to AD7/P47 External access RD/P64 WR/P65 WAIT/P66 ASTB/P67 ANI0 to ANI7 AVSS AVREF INTP0/P00 to INTP3/P03 PCL/P70 A/D converter Interrupt control System control Clock output control A8/P50 to A15/P57 VDD0 VDD1 VSS0 VSS1 RESET X1 X2 XT1 XT2 IC Data Sheet U13732EJ1V0DS 9 µPD780065 3. PIN FUNCTIONS 3.1 Port Pins Pin Name P00 to P03 I/O I/O P04 to P07 P20 I/O Function After Reset Alternate Function Port 0 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software. Input INTP0 to INTP3 — Port 2 Input TI00/TO0 P21 8-bit I/O port. TI01 P22 Input/output can be specified in 1-bit units. TI50/TO50 Use of an on-chip pull-up resistor can be specified by software. P23 TI51/TO51 P24 to P27 — P30 to P37 I/O Port 3 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software. Input — P40 to P47 I/O Port 4 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software. Input AD0 to AD7 P50 to P57 I/O Port 5 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by software. Input A8 to A15 P64 I/O Port 6 Input RD P65 4-bit I/O port. WR P66 Input/output can be specified in 1-bit units. WAIT Use of an on-chip pull-up resistor can be specified by software. P67 P70 I/O Port 7 ASTB Input PCL P71 8-bit I/O port. ASCK0 P72 Input/output can be specified in 1-bit units. TxD0 Use of an on-chip pull-up resistor can be specified by software. P73 RxD0 P74 SCK30 P75 SDIO30 P76, P77 P80 — I/O Port 8 Input STB P81 5-bit I/O port. BUSY P82 Input/output can be specified in 1-bit units. SCK1 Use of an on-chip pull-up resistor can be specified by software. P83 SO1 P84 P90 SI1 I/O Port 9 Input SCK31 P91 3-bit I/O port. SO31 P92 Input/output can be specified in 1-bit units. SI31 Use of an on-chip pull-up resistor can be specified by software. 10 Data Sheet U13732EJ1V0DS µPD780065 3.2 Non-Port Pins (1/2) Pin Name I/O Function After Alternate Reset Function INTP0 to INTP3 Input External interrupt request input by which the valid edge (rising edge, falling edge, or both rising edge and falling edge) can be specified Input P00 to P03 TI00 Input External count clock input to 16-bit timer/event counter 0 Capture trigger signal input to capture register (CR01) of 16-bit timer/event counter Input P20/TO0 TI01 Capture trigger signal input to capture register (CR00) of 16-bit timer/event P21 counter TI50 External count clock input to 8-bit timer/event counter 50 P22/TO50 TI51 External count clock input to 8-bit timer/event counter 51 P23/TO51 TO0 Output 16-bit timer/event counter 0 output Input P20/TI00 TO50 8-bit timer/event counter 50 output (can be used for 8-bit PWM output) P22/TI50 TO51 8-bit timer/event counter 51 output (can be used for 8-bit PWM output) P23/TI51 SI1 Input Serial interface SIO1 serial data input Input P84 SI31 Input Serial interface SIO31 serial data input SO1 Output Serial interface SIO1 serial data output SO31 Output Serial interface SIO31 serial data output SDIO30 I/O Serial interface SIO30 serial data input/output Input P75 SCK1 I/O P92 Input P83 P91 Serial interface SIO1 serial clock input/output Input P82 SCK30 Serial interface SIO30 serial clock input/output Input P74 SCK31 Serial interface SIO31 serial clock input/output Input P90 Busy input for serial interface SIO1 automatic transmission/reception BUSY Input Input P81 STB Output Strobe output for serial interface SIO1 automatic transmission/reception Input P80 RxD0 Input Input P73 TxD0 Output Serial data output for asynchronous serial interface Input P72 ASCK0 Input Input P71 PCL Output Clock output (for trimming of main system clock and subsystem clock) Input P70 AD0 to AD7 I/O Input P40 to P47 A8 to A15 Output Higher address bus for expanding memory externally Input P50 to P57 RD Output Strobe signal output for read operation of external memory Input P64 WR Output Strobe signal output for write operation of external memory Input P65 WAIT Input Input P66 ASTB Output Strobe output which externally latches address information output to port 4 and port 5 to access external memory Input P67 ANI0 to ANI7 Input Serial data input for asynchronous serial interface Serial clock input for asynchronous serial interface Lower address/data bus for expanding memory externally Inserting wait for accessing external memory A/D converter analog input Data Sheet U13732EJ1V0DS Input — 11 µPD780065 3.2 Non-Port Pins (2/2) Pin Name AVREF AVSS After Reset Alternate Function — — A/D converter ground potential. Make this pin the same potential as VSS0 or VSS1. — — I/O Function Output A/D converter reference voltage input (can be used for analog power supply) — RESET Input System reset input — — X1 Input Connecting crystal resonator for main system clock oscillation — — X2 — — — XT1 Input XT2 — VDD0 — VDD1 VSS0 — — — — Positive power supply for ports — — — Ground potential of ports — — — Positive power supply (except ports) — — VSS1 — Ground potential (except ports) — — IC — Internally connected. Connect this pin directly to V SS0 or VSS1 . — — 12 Connecting crystal resonator for subsystem clock oscillation Data Sheet U13732EJ1V0DS µPD780065 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins Pin Name P00/INTP0 to P03/INTP3 I/O Circuit Type 8-C I/O I/O Recommended Connections of Unused Pins Input: Independently connect to VSS0 via a resistor. P04 to P07 Output: Leave open. P20/T100/TO0 Input: Independently connect to VDD0 or VSS0 via a resistor. P21/T101 Output: Leave open. P22/TI50/TO50 P23/TI51/TO51 P24 to P27 P30 to P37 P40/AD0 to P47/AD7 5-H Input: Independently connect to VDD0 via a resistor. Output: Leave open. P50/A8 to P57/A15 Input: Independently connect to VDD0 or VSS0 via a resistor. P64/RD Output: Leave open. P65/WR P66/WAIT P67/ASTB P70/PCL P71/ASCK0 8-C P72/TxD0 5-H P73/RxD0 8-C P74/SCK30 P75/SDIO30 5-H P76, P77 8-C P80/STB 5-H P81/BUSY 8-C P82/SCK1 P83/SO1 5-H P84/SI1 8-C P90/SCK31 P91/SO31 5-H P92/SI31 8-C ANI0 to ANI7 7-B XT1 16 Input Independently connect to VDD0 or VSS0. Connect to VDD0. XT2 — RESET 2 AVREF — Leave open. Input — — Connect to VSS0 or VSS1. AVSS IC Directly connect to VSS0 or VSS1. Data Sheet U13732EJ1V0DS 13 µPD780065 Figure 3-1. Pin I/O Circuits Type 2 Type 8-C VDD0 Pull-up enable P-ch VDD0 Data IN P-ch IN/OUT Output disable N-ch Schmitt-triggered input with hysteresis characteristics Type 5-H Type 16 VDD0 Pull-up enable VSS0 Feedback cut-off P-ch P-ch VDD0 Data P-ch IN/OUT Output disable N-ch VSS0 XT1 Input enable Type 7-B IN Comparator P-ch N-ch + – AVSS VREF (Threshold voltage) 14 Data Sheet U13732EJ1V0DS XT2 µPD780065 4. MEMORY SPACE Figure 4-1 shows the memory map of the µ PD780065. Figure 4-1. Memory Map FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits 9FFFH FB00H FAFFH Program area Reserved Data memory space FAE0H FADFH FAC0H FABFH Internal buffer RAM 32 × 8 bits 1000H 0FFFH CALLF entry area Reserved F800H F7FFH E800H E7FFH Internal expansion RAM 4096 × 8 bits Program area External memory 18432 × 8 bits Program memory space 0800H 07FFH 0080H 007FH CALLT table area A000H 9FFFH Internal ROM 40960 × 8 bits 0040H 003FH Vector table area 0000H 0000H Data Sheet U13732EJ1V0DS 15 µPD780065 5. FEATURES OF PERIPHERAL HARDWARE 5.1 Ports There are 60 CMOS I/O ports. Table 5-1. Port Functions Name Pin Name Function Port 0 P00 to P07 I/O port. Input/output can be specified in 1-bit units. Port 2 P20 to P27 Use of an on-chip pull-up resistor can be specified by software. Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P64 to P67 Port 7 P70 to P77 Port 8 P80 to P84 Port 9 P90 to P92 5.2 Clock Generator A system clock generator is incorporated. The minimum instruction execution time can be changed. • 0.24 µ s/0.48 µs/0.95 µs/1.91 µs/3.81 µs (main system clock: at 8.38 MHz operation) • 122 µs (subsystem clock: at 32.768 kHz operation) Figure 5-1. Block Diagram of Clock Generator XT1 XT2 Subsystem clock oscillator fXT Watch timer, clock output function Prescaler 1 X1 X2 Main system clock oscillator STOP 16 Prescaler fX fX 2 fX 22 fX 23 2 fXT 2 Clock to peripheral hardware fX 24 Selector Data Sheet U13732EJ1V0DS Standby controller Wait controller CPU clock (fCPU) µPD780065 5.3 Timer/Event Counter Five timer/event counter channels are incorporated. • 16-bit timer/event counter: 1 channel • 8-bit timer/event counter: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel Table 5-2. Operations of Timer/Event Counter 16-Bit Timer/ Event Counter 0 8-Bit Timer/ Event Counter 50, 51 Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 1 channelNote 1 1 channelNote 2 External event counter 1 channel 2 channels — — Timer output 1 output 2 outputs — — PWM output — 2 outputs — — PPG output 1 output — — — Pulse width measurement 2 inputs — — — Square wave output 1 output 2 outputs — — 2 2 2 1 Operation mode Function Interrupt source Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or the interval timer function. Data Sheet U13732EJ1V0DS 17 µPD780065 Figure 5-2. Block Diagram of 16-bit Timer/Event Counter 0 TI01/P21 Selector Noise eliminator Selector Internal bus 16-bit capture/compare register 00 (CR00) INTTM00 fX fX/22 fX/26 TI00/TO0/P20 16-bit timer counter 0 (TM0) Output controller TO0/TI00/P20 Match Noise eliminator Noise eliminator 16-bit capture/compare register 01 (CR01) Internal bus 18 Clear Selector fX/23 Selector Match Data Sheet U13732EJ1V0DS INTTM01 µPD780065 Figure 5-3. Block Diagram of 8-bit Timer/Event Counter 50 Internal bus Selector S Q INV 8-bit timer OVF counter 50 (TM50) R INTTM50 Selector Match Selector TI50/TO50/P22 fX fX/22 fX/24 fX/26 fX/28 fX/210 Mask circuit 8-bit compare register 50 (CR50) TO50/TI50/P22 Clear S 3 Invert level R Selector TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Timer mode control register 50 (TMC50) TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50) Internal bus Figure 5-4. Block Diagram of 8-bit Timer/Event Counter 51 Internal bus Selector S Q INV OVF 8-bit timer counter 51 (TM51) R INTTM51 Selector Match Selector TI51/TO51/P23 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Mask circuit 8-bit compare register 51 (CR51) TO51/TI51/P23 Clear S 3 R Selector TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51) Invert level TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer mode control register 51 (TMC51) Internal bus Data Sheet U13732EJ1V0DS 19 µPD780065 Figure 5-5. Block Diagram of Watch Timer Clear 7 Selector fX/2 fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 INTWT Clear Selector fXT 5-bit counter 9-bit prescaler fW INTWTI WTM7 WTM6 WTM5 WTM4 0 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus Figure 5-6. Block Diagram of Watchdog Timer fX 8 fX/2 Clock input controller Divided clock select circuit Divider Output controller INTWDT RESET RUN Division mode select circuit 3 WDT mode signal OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) WDCS2 WDCS1 WDCS0 Watchdog timer clock select register (WDCS) RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus 20 Data Sheet U13732EJ1V0DS µPD780065 5.4 Clock Output Controller A clock output controller (CKU) is incorporated. Clocks with the following frequencies can be output as a clock output. • 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (main system clock: at 8.38 MHz operation) • 32.768 kHz (subsystem clock: at 32.768 kHz operation) Figure 5-7. Block Diagram of Clock Output Controller CKU fX Prescaler 8 Selector fX to fX/27 fXT Clock controller PCL/P70 CLOE CLOE CCS3 CCS2 CCS1 CCS0 Clock output select register (CKS) Internal bus Data Sheet U13732EJ1V0DS 21 µPD780065 5.5 A/D Converter An A/D converter of 8-bit resolution × 8 channels is incorporated. Figure 5-8. Block Diagram of A/D Converter Series resistor string Sample & hold circuit ANI0 ANI1 AVREF (can be used for analog power supply) Voltage comparator ANI2 Tap selector ANI3 ANI4 Selector ANI5 ANI6 ANI7 Succesive approximation register (SAR) INTAD0 Controller A/D conversion result register 0 (ADCR0) Internal bus 22 AVSS Data Sheet U13732EJ1V0DS µPD780065 5.6 Serial Interface Four serial interface channels are incorporated. • Serial interface UART0: 1 channel • Serial interface SIO1: 1 channel • Serial interface SIO30: 1 channel • Serial interface SIO31: 1 channel (1) Serial interface UART0 Serial interface UART0 has two modes, asynchronous serial interface (UART) mode and infrared data transfer mode. • Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. The on-chip dedicated UART baud rate generator enables communication using a wide range of selectable baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin. The dedicated UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 Kbps). • Infrared data transfer mode This mode enables pulse output and pulse reception in data format. This mode can be used for office equipment applications such as personal computers. Figure 5-9. Block Diagram of Serial Interface UART0 Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive buffer RXB0 register 0 RxD0/P73 RX0 Receive shift register 0 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0 Asynchronous serial interface status register 0 (ASIS0) TXS0 Transmit shift PE0 FE0 OVE0 register TxD0/P72 Receive controller (parity check) Transmit INTSER0 controller INTSR0 (parity addition) INTST0 Baud rate generator Data Sheet U13732EJ1V0DS P71/ASCK0 fX/2 to fX/27 23 µPD780065 (2) Serial interface SIO1 Serial interface SIO1 has a 3-wire serial I/O mode and a 3-wire serial I/O mode with an auto-transmit/receive function. • 3-wire serial I/O mode (MSB/LSB-first switching is possible) This mode performs 8-bit data transfer via 3 lines: a serial clock line (SCK1), serial output line (SO1), and serial input line (SI1). This mode can transmit and receive data simultaneously and allows the processing time of data transfer to be reduced. Since MSB-first or LSB-first is supported for the first bit of the 8-bit data for serial transfer, it is possible to connect the µ PD780065 to both MSB-first devices and LSB-first devices. 3-wire serial I/O mode is effective when connecting to a peripheral I/O that incorporates a clock synchronous serial interface or a display controller, etc. • 3-wire serial I/O mode with auto-transmit/receive function This mode has the same functions as the 3-wire serial I/O mode above, but with an added auto transmit/ receive function. A maximum of 32 bytes of data can be transmitted/received in this mode. This function allows hardwarebased data transmission/reception to and from devices for OSD (On Screen Display) and devices that incorporate display controllers/drivers independently from the CPU. This mode, therefore, can reduce the burden on software. 24 Data Sheet U13732EJ1V0DS µPD780065 Figure 5-10. Block Diagram of Serial Interface SIO1 Internal Bus Automatic data transmit/receive address pointer (ADTP) Serial I/O shift register 1 (SIO1) SI1/P84 Automatic data transmit/receive interval specification register (ADTI) Buffer RAM Match SO1/P83 5-bit counter STB/P80 Handshake controller BUSY/P81 Serial clock counter Serial clock controller Data Sheet U13732EJ1V0DS Interrupt request signal generator Selector SCK1/P82 INTCSI1 fX/23 to fX/25 25 µPD780065 (3) Serial interface SIO30 Serial interface SIO30 has a 2-wire serial I/O mode. • 2-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using two lines: a serial clock line (SCK30) and a data I/O line (SDIO30). The first bit in 8-bit data in the serial transfer is fixed as MSB. The 2-wire serial I/O mode is useful for connection to a peripheral I/O that incorporates a clocked serial interface, a display controller, etc. Figure 5-11. Block Diagram of Serial Interface SIO30 Internal bus 8 Serial I/O shift register 30 (SIO30) SDIO30/P75 SCK30/P74 26 Serial clock counter Interrupt request signal generator Serial clock controller Selector Data Sheet U13732EJ1V0DS INTCSI30 fX/25 fX/26 fX/27 µPD780065 (4) Serial interface SIO31 Serial interface SIO31 has a 3-wire serial I/O mode. • 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK31), serial output line (SO31), and serial input line (SI31). Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in 8-bit data in the serial transfer is fixed as MSB. The 3-wire serial I/O mode is useful for connection to a peripheral I/O device that incorporates a clocked serial interface, a display controller, etc. Figure 5-12. Block Diagram of Serial Interface SIO31 Internal bus 8 SI31/P92 Serial I/O shift register 31 (SIO31) SO31/P91 SCK31/P90 Serial clock counter Interrupt request signal generator Serial clock controller Selector Data Sheet U13732EJ1V0DS INTCSI31 fX/23 fX/24 fX/25 27 µPD780065 6. INTERRUPT FUNCTIONS The interrupt function consists of 20 interrupt sources and three interrupt types, as shown below. • Non-maskable: 1 • Maskable: 18 • Software: 1 Table 6-1. Interrupt Source List Interrupt Default Type PriorityNote 1 Nonmaskable — INTWDT Watchdog timer overflow (watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (interval timer mode selected) 1 INTP0 Pin input edge detection 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTSER0 Generation of serial interface UART0 reception error 6 INTSR0 End of serial interface UART0 reception 0010H 7 INTST0 End of serial interface UART0 transmission 0012H 8 INTCSI30 End of serial interface SIO30 transfer 0014H 9 INTCSI31 End of serial interface SIO31 transfer 0016H 10 INTCSI1 End of serial interface SIO1 transfer 0018H 11 INTTM00 Match of TM0 and CR00 (when CR00 is specified as compare register) or TI01 pin valid edge detection (when CR00 is specified as capture register) 001AH 12 INTTM01 Match of TM0 and CR01 (when CR01 is specified as compare register) or TI00 pin valid edge detection (when CR01 is specified as capture register) 001CH 13 INTTM50 Match of TM50 and CR50 001EH 14 INTTM51 Match of TM51 and CR51 0020H 15 INTWTI Reference time interval signal from watch timer 0022H 16 INTWT Watch timer overflow 0024H 17 INTAD0 End of conversion by A/D converter 0026H — BRK BRK instruction execution Software Interrupt Source Name Trigger Internal/ Vector Table External Address Internal 0004H Basic Configuration TypeNote 2 (A) (B) External Internal — 0006H 000EH 003EH (C) (B) (D) Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 17 is the lowest. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 6-1, respectively. Remark Two watchdog timer interrupt sources (INTWDT): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected. 28 Data Sheet U13732EJ1V0DS µPD780065 Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Priority controller Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Vector table address generator Priority controller IF Standby release signal (C) External maskable interrupt (INTP0 to INTP3) Internal bus External interrupt edge enable register (EGP, EGN) Interrupt request Edge detector MK IE IF PR Priority controller ISP Vector table address generator Standby release signal Data Sheet U13732EJ1V0DS 29 µPD780065 Figure 6-1. Basic Configuration of Interrupt Function (2/2) (D) Software interrupt Internal bus Interrupt request Priority controller IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag 30 Data Sheet U13732EJ1V0DS Vector table address generator µPD780065 7. EXTERNAL DEVICE EXPANSION FUNCTION The external device expansion function is for connecting external devices to areas other than the internal ROM, RAM, and SFRs. Ports 4 to 6 are used for external device connection. 8. STANDBY FUNCTION The following two standby modes are available for further reduction of system current consumption. • HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. • STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. This can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). Figure 8-1. Standby Function CSS = 1 Main system clock operation Interrupt request CSS = 0 HALT instruction STOP instruction HALT instruction Interrupt request STOP mode Main system clock operation is stopped Note Subsystem clock operationNote Interrupt request HALT mode HALT modeNote Clock supply for CPU is stopped, oscillation is maintained Clock supply for CPU is stopped, oscillation is maintained The current consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 9. RESET FUNCTION The following two reset methods are available. • External reset by RESET signal input • Internal reset by watchdog timer program loop time detection Data Sheet U13732EJ1V0DS 31 µPD780065 10. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second operand [HL + byte] #byte First operand A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None [HL + C] A r ADD MOV MOV MOV MOV ADDC XCH XCH SUB ADD XCH XCH ADD ADD SUBC ADDC ADDC AND SUB SUB MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD RORC ADDC ADDC ADDC ROLC SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP DBNZ B, C sfr MOV MOV saddr MOV ADD MOV DBNZ INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note 32 Except r = A Data Sheet U13732EJ1V0DS µPD780065 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second operand First operand AX #word rpNote AX MOVW ADDW SUBW CMPW MOVW MOVWNote sfrp MOVW MOVW saddrp MOVW MOVW !addr16 Note MOVW saddrp !addr16 MOVW MOVW SP None MOVW XCHW rp SP sfrp INCW, DECW PUSH, POP MOVW MOVW MOVW Only when rp = BC, DE or HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second operand First operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY MOV1 AND1 MOV1 AND1 MOV1 AND1 MOV1 AND1 MOV1 AND1 SET1 CLR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 NOT1 (4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second operand First operand Basic instruction AX BR !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ Compound instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Data Sheet U13732EJ1V0DS 33 µPD780065 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Supply voltage Conditions VDD AVREF AVSS Input voltage VI Output voltage VO P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P84, P90 to P92, X1, X2, XT1, XT2, RESET Analog input pin Ratings Unit –0.3 to +6.5 V –0.3 to V DD + 0.3 V –0.3 to +0.3 V –0.3 to V DD + 0.3 V –0.3 to V DD + 0.3 V AVSS – 0.3 to AVREF0 + 0.3 and – 0.3 to V DD + 0.3 V Analog input voltage VAN ANI0 to ANI7 Output current, high I OH Per pin –10 mA Total for P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P80 to P84, P90 to P92 –15 mA Total for P70 to P77 –15 mA Output current, low I OL Note Per pin for P00 to P07, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P70 to P77, P80 to P84, P90 to P92 Peak value 20 mA rms value 10 mA Per pin for P50 to P57 Peak value 30 mA rms value 15 mA Total for P00 to P07, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P80 to P84, P90 to P92 Peak value 50 mA rms value 20 mA Total for P70 to P77 Peak value 20 mA rms value 10 mA 100 mA Total for P50 to P57 Peak value rms value Operating ambient temperature TA Storage temperature Tstg 70 mA –40 to +85 °C –65 to +150 °C Note The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 34 Data Sheet U13732EJ1V0DS µPD780065 Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V. I/O capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V. P00 P30 P50 P70 P90 to to to to to MIN. P07, P37, P57, P77, P92 P20 P40 P64 P80 to to to to TYP. P27, P47, P67, P84, MAX. Unit 15 pF 15 pF Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V) Resonator Ceramic resonator Recommended Circuit X1 C1 Crystal resonator X1 C1 External clock X1 X2 IC C2 X2 IC C2 X2 µ PD74HCU04 Parameter Conditions Oscillation frequency (fX)Note 1 VDD = 4.5 to 5.5 V Oscillation stabilization timeNote 2 After VDD reaches oscillation voltage range MIN. Oscillation frequency (fX)Note 1 VDD = 4.5 to 5.5 V Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V X1 input frequency (fX)Note 1 VDD = 4.5 to 5.5 V X1 input high-/low-level width (tXH, tXL) VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 1.0 8.38 MHz 1.0 5.0 4 ms 1.0 8.38 MHz 1.0 5.0 10 ms 30 1.0 8.38 MHz 5.0 50 500 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS1. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Data Sheet U13732EJ1V0DS 35 µPD780065 Subsystem Clock Oscillator Characteristics (T A = –40 to +85 °C, V DD = 2.7 to 5.5 V) Resonator Crystal resonator Recommended Circuit XT2 XT1 IC R C4 C3 Parameter Conditions Oscillation frequency (fXT) Note 1 Oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.5 to 5.5 V stabilization timeNote 2 External clock XT2 XT1 µPD74HCU04 10 XT1 input frequency (fXT) Note 1 32 38.5 kHz XT1 input high-/low-level width (tXTH , t XTL) 5 15 µs Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after V DD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as V SS1. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 36 Data Sheet U13732EJ1V0DS µPD780065 Recommended Oscillator Constant Main system clock: Ceramic resonator (TA = –40 to +85°C) Manufacturer Murata Mfg. Co., Ltd. Caution Part Number Frequency Recommended Circuit Constant (MHz) C1 (pF) C2 (pF) Oscillation Voltage Range MIN. (V) MAX. (V) CSB1000J 1.00 100 100 2.7 5.5 CSA2.00MG040 2.00 100 100 2.7 5.5 CST2.00MG040 2.00 On-chip On-chip 2.7 5.5 CSA3.58MG 3.58 30 30 2.7 5.5 CST3.58MGW 3.58 On-chip On-chip 2.7 5.5 CSA4.19MG 4.19 30 30 2.7 5.5 CST4.19MGW 4.19 On-chip On-chip 2.7 5.5 CSA5.00MG 5.00 30 30 2.7 5.5 CST5.00MGW 5.00 On-chip On-chip 2.7 5.5 CSA8.00MTZ 8.00 30 30 2.7 5.5 CST8.00MTW 8.00 On-chip On-chip 2.7 5.5 CSA8.00MTZ093 8.00 30 30 2.7 5.5 CST8.00MTW093 8.00 On-chip On-chip 2.7 5.5 CSA8.38MTZ 8.38 30 30 2.7 5.5 CST8.38MTW 8.38 On-chip On-chip 2.7 5.5 CSA8.38MTZ093 8.38 30 30 2.7 5.5 CST8.38MTW093 8.38 On-chip On-chip 2.7 5.5 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, contact directly the manufacturer of the resonator used. Data Sheet U13732EJ1V0DS 37 µPD780065 DC Characteristics (TA = –40 to +85 °C, V DD = 2.7 to 5.5 V) Parameter Symbol Output current, high I OH Output current, low IOL Conditions MIN. TYP. MAX. Unit Per pin –1 mA All pins –15 mA Per pin for P00 to P07, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P70 to P77, P80 to P84, P90 to P92 10 mA Per pin for P50 to P57 15 mA Total for P00 to P07, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P80 to P84, P90 to P92 20 mA Total for P50 to P57 70 mA Total for P70 to P77 Input voltage, high Input voltage, low 10 mA VIH1 P04 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70, P72, P76, P77, P80, P81, P83, P91 0.7VDD VDD V VIH2 P00 to P03, P71, P73 to P75, P82, P84, P90, P92, RESET 0.8VDD VDD V VIH3 X1, X2 VDD – 0.5 VDD V VIH4 XT1, XT2 0.8VDD VDD V 0.9VDD VDD V VDD = 4.5 to 5.5 V VIL1 P04 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70, P72, P76, P77, P80, P81, P83, P91 0 0.3VDD V VIL2 P00 to P03, P71, P73 to P75, P82, P84, P90, P92, RESET 0 0.2VDD V VIL3 X1, X2 0 0.4 V VIL4 XT1, XT2 0 0.2VDD V 0 0.1VDD V Output voltage, high VOH1 VDD = 4.5 to 5.5 V, I OH = –1 mA VDD – 1.0 VDD V IOH = –100 µA VDD – 0.5 VDD V Output voltage, low VOL1 2.0 V 0.4 V 0.5 V P50 to P57 P00 P30 P64 P80 VOL2 VDD = 4.5 to 5.5 V to to to to P07, P37, P67, P84, VDD = 4.5 to 5.5 V, I OL = 15 mA P20 P40 P70 P90 to to to to P27, P47, P77, P92 VDD = 4.5 to 5.5 V, I OL = 1.6 mA IOL = 400 µA 0.4 Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 38 Data Sheet U13732EJ1V0DS µPD780065 DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V) Parameter Input leakage current, high Symbol I LIH1 Conditions VIN = VDD I LIH2 Input leakage current, low I LIL1 VIN = 0 V I LIL2 MAX. Unit 3 µA X1, X2, XT1, XT2 20 µA P00 P30 P50 P70 P90 –3 µA –20 µA P00 P30 P50 P70 P90 to to to to to to to to to to MIN. P07, P37, P57, P77, P92, P07, P37, P57, P77, P92, TYP. P20 to P27, P40 to P47, P64 to P67, P80 to P84, RESET P20 to P27, P40 to P47, P64 to P67, P80 to P84, RESET X1, X2, XT1, XT2 Output leakage current, high I LOH VOUT = VDD 3 µA Output leakage current, low I LOL VOUT = 0 V –3 µA Software pull-up resistance R VIN = 0 V, P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P84, P90 to P92 90 kΩ 15 30 Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U13732EJ1V0DS 39 µPD780065 DC Characteristics (TA = –40 to +85 °C, V DD = 2.7 to 5.5 V) Parameter Power supply current Note 1 Symbol IDD1 IDD2 Conditions 8.38 MHz crystal oscillation operating mode VDD = 5.0 V ± 10% Note 2 5.00 MHz crystal oscillation operating mode VDD = 3.0 V ± 10% Note 2 8.38 MHz crystal oscillation HALT mode VDD = 5.0 V ± 10% Note 2 5.00 MHz crystal oscillation HALT mode VDD = 3.0 V ± 10% Note 2 TYP. MAX. Unit When A/D converter is stopped 5.5 11 mA When A/D converter is operating 6.5 13 mA When A/D converter is stopped 2 4 mA When A/D converter is operating 3 6 mA When peripheral functions are stopped 1.1 2.2 mA 4.7 mA 0.7 mA 1.7 mA When peripheral functions are operating When peripheral functions are stopped 0.35 When peripheral functions are operating IDD3 32.768 kHz crystal oscillation operating modeNote 3 IDD4 32.768 kHz crystal oscillation HALT modeNote 3 IDD5 MIN. XT1 = V DD STOP mode When feedback resistor is not used VDD = 5.0 V ± 10% 40 80 µA VDD = 3.0 V ± 10% 20 40 µA VDD = 5.0 V ± 10% 30 60 µA VDD = 3.0 V ± 10% 6 18 µA VDD = 5.0 V ± 10% 0.1 30 µA VDD = 3.0 V ± 10% 0.05 10 µA Notes 1. Total current through the internal power supply (VDD0 , VDD1 ), including the peripheral operation current (except the current through pull-up resistors of ports and the AVREF pin). 2. When the processor clock control register (PCC) is set to 00H. 3. When main system clock operation is stopped. 40 Data Sheet U13732EJ1V0DS µPD780065 AC Characteristics (1) Basic Operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Cycle time (Minimum instruction execution time) TCY TI00, TI01 input high-/low-level width t TIH0, tTIL0 Conditions Operating with main system clock fTI5 TI50, TI51 input high-/low-level width t TIH5, tTIL5 Interrupt request input high-/low-level width t INTH, t INTL RESET low-level width t RSL TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 0.24 16 µs 2.7 V ≤ VDD < 4.5 V 0.4 16 µs 125 µs Operating with subsystem clock TI50, TI51 input frequency MIN. 103.9Note 1 122 3.5 V ≤ V DD ≤ 5.5 V 2/fsam + 0.1Note 2 µs 2.7 V ≤ V DD < 3.5 V 2/fsam + 0.2Note 2 µs 0 INTP0 to INTP3 4 MHz 100 ns 1 µs 10 µs Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.). 2. Selection of f sam = f X , fX /4, fX /64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes f sam = fX /8. Data Sheet U13732EJ1V0DS 41 µPD780065 TCY vs. V DD (main system clock operation) 16.0 Cycle time T CY [ µ s] 10.0 Operation guaranteed range 5.0 2.0 1.0 0.4 0.24 0.1 0 1.0 2.0 3.0 4.0 4.5 5.0 5.5 6.0 2.7 Supply voltage V DD [V] 42 Data Sheet U13732EJ1V0DS µPD780065 (2) Read/Write Operation (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width t ASTH 0.3t CY ns Address setup time tADS 20 ns Address hold time t ADH 6 ns Data input time from address t ADD1 (2 + 2n) t CY – 54 ns t ADD2 (3 + 2n) t CY – 60 ns 100 ns Address output time from RD↓ tRDAD 0 Data input time from RD↓ t RDD1 (2 + 2n) t CY – 87 ns t RDD2 (3 + 2n) t CY – 93 ns Read data hold time t RDH 0 ns RD low-level width t RDL1 (1.5 + 2n) t CY – 33 ns t RDL2 (2.5 + 2n) t CY – 33 ns Input time from RD↓ to WAIT↓ Input time from WR↓ to WAIT↓ t RDWT1 t CY – 43 ns t RDWT2 t CY – 43 ns tWRWT t CY – 25 ns (2 + 2n) tCY ns WAIT low-level width t WTL (0.5 + n) tCY + 10 Write data setup time t WDS 60 ns Write data hold time t WDH 6 ns WR low-level width t WRL1 (1.5 + 2n) t CY – 15 ns Delay time from ASTB↓ to RD↓ tASTRD 6 ns Delay time from ASTB↓ to WR↓ tASTWR 2tCY – 15 ns Delay time from RD↑ to ASTB↑ at external fetch tRDAST 0.8t CY – 15 1.2t CY ns Address hold time from RD↑ at external fetch t RDADH 0.8t CY – 15 1.2t CY + 30 ns Write data output time from RD↑ t RDWD 40 Write data output time from WR↓ t WRWD 10 60 ns Address hold time from WR↑ t WRADH 0.8t CY – 15 1.2t CY + 30 ns Delay time from WAIT↑ to RD↑ tWTRD 0.8t CY 2.5t CY + 25 ns Delay time from WAIT↑ to WR↑ tWTWR 0.8t CY 2.5t CY + 25 ns ns Remarks 1. t CY = T CY /4 2. n indicates the number of waits. 3. C L = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) Data Sheet U13732EJ1V0DS 43 µPD780065 (2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 4.5 V) (2/2) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3t CY ns Address setup time t ADS 30 ns Address hold time tADH 10 ns Input time from address to data tADD1 (2 + 2n) tCY – 108 ns tADD2 (3 + 2n) tCY – 120 ns 200 ns Output time from RD↓ to address t RDAD 0 Input time from RD↓ to data tRDD1 (2 + 2n) tCY – 148 ns tRDD2 (3 + 2n) tCY – 162 ns Read data hold time t RDH 0 ns RD low-level width t RDL1 (1.5 + 2n) tCY – 40 ns t RDL2 (2.5 + 2n) tCY – 40 ns Input time from RD↓ to WAIT↓ Input time from WR↓ to WAIT↓ t RDWT1 t CY – 75 ns t RDWT2 t CY – 60 ns t WRWT t CY – 50 ns (2 + 2n) tCY ns WAIT low-level width tWTL (0.5 + 2n) tCY + 10 Write data setup time tWDS 60 ns Write data hold time t WDH 10 ns WR low-level width t WRL1 (1.5 + 2n) tCY – 30 ns Delay time from ASTB↓ to RD↓ t ASTRD 10 ns Delay time from ASTB↓ to WR↓ t ASTWR 2tCY – 30 ns Delay time from RD↑ to ASTB↑ at external fetch t RDAST 0.8t CY – 30 1.2tCY ns Hold time from RD↑ to address at external fetch t RDADH 0.8t CY – 30 1.2tCY + 60 ns Write data output time from RD↑ tRDWD 40 Write data output time from WR↓ tWRWD 20 120 ns Hold time from WR↑ to address t WRADH 0.8t CY – 30 1.2tCY + 60 ns Delay time from WAIT↑ to RD↑ t WTRD 0.5t CY 2.5tCY + 50 ns Delay time from WAIT↑ to WR↑ t WTWR 0.5t CY 2.5tCY + 50 ns ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. 3. CL = 100 pF (C L indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and ASTB pins.) 44 Data Sheet U13732EJ1V0DS µPD780065 (3) Serial Interface (TA = –40 to +85°C, VDD = 2.7 to 5.5 V) (a) SIO3n 3-wire serial I/O mode (SCK3n... Internal clock output) Parameter SCK3n cycle time Symbol t KCY1 SCK3n high-/ low-level width t KH1, tKL1 SI3n setup time (to SCK3n↑) t SIK1 SI3n hold time (from SCK3n↑) t KSI1 Delay time from SCK3n↓ to SO3n output t KSO1 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 954 ns 1600 ns t KCY1/2 – 50 ns tKCY1/2 – 100 ns 100 ns 150 ns 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is the load to SO3n output capacitance of the SCK3n and SO3n output lines. (b) SIO3n 3-wire serial I/O mode (SCK3n... External clock input) Parameter Symbol Conditions SCK3n cycle time t KCY2 VDD = 4.5 to 5.5 V SCK3n high-/ low-level width t KH2, tKL2 VDD = 4.5 to 5.5 V SI3n setup time (to SCK3n↑) MIN. TYP. 800 ns 1600 ns 400 ns 800 ns t SIK2 100 ns SI3n hold time (from SCK3n↑) t KSI2 400 ns Delay time from SCK3n↓ to SO3n output t KSO2 C = 100 pFNote 300 ns Note C is the load capacitance of the SO3n output line. Remark n = 0, 1 Data Sheet U13732EJ1V0DS 45 µPD780065 (3) Serial Interface (TA = –40 to +85°C, VDD = 2.7 to 5.5 V) (c) SIO1 3-wire serial I/O mode (SCK1... Internal clock output) Parameter Symbol SCK1 cycle time tKCY3 SCK1 high-/ low-level width tKH3, tKL3 SI1 setup time Conditions MIN. TYP. MAX. Unit 800 ns tKCY1/2 – 50 ns tSIK3 100 ns SI1 hold time (from SCK1↑) tKSI3 400 ns Delay time from SCK1↓ to SO1 output tKSO3 (to SCK1↑) C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of the SCK1 and SO1 output lines. (d) SIO1 3-wire serial I/O mode (SCK1... External clock input) Parameter Symbol Conditions MIN. TYP. SCK1 cycle time tKCY4 800 ns SCK1 high-/ tKH4, tKL4 400 ns SI1 setup time (to SCK1↑) tSIK4 100 ns SI1 hold time (from SCK1↑) tKSI4 400 ns Delay time from SCK1↓ to SO1 output tKSO4 SCK1 rise/fall time tR, tF low-level width C = 100 pFNote Note C is the load capacitance of the SO1 output line. 46 Data Sheet U13732EJ1V0DS 300 ns 1 µs µPD780065 (e) UART mode (dedicated baud-rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. VDD = 4.5 to 5.5 V MAX. Unit 131031 bps 78125 bps MAX. Unit (f) UART mode (external clock input) Parameter ASCK0 cycle time ASCK0 high-/low-level width Symbol tKCY5 tKH5, Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL5 Transfer rate MIN. TYP. 800 ns 1600 ns 400 ns 800 ns VDD = 4.5 to 5.5 V 39063 bps 19531 bps MAX. Unit (g) UART mode (infrared data transfer mode) Parameter Symbol Conditions MIN. TYP. Transfer rate VDD = 4.5 to 5.5 V 131031 bps Bit rate allowable error VDD = 4.5 to 5.5 V ±0.87 % Output pulse width VDD = 4.5 to 5.5 V 1.2 0.24/fbrNote µs Input pulse width VDD = 4.5 to 5.5 V 4/fX µs Note fbr: Specified baud rate Data Sheet U13732EJ1V0DS 47 µPD780065 AC Timing Measurement Points (Excluding X1, XT1 Inputs) 0.8VDD 0.2VDD 0.8VDD Point of measurement 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 input 1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.) XT1 input TI Timing tTIL0 tTIH0 TI00, TI01 1/fT5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL INTP0 to INTP3 48 Data Sheet U13732EJ1V0DS tINTH µPD780065 RESET Input Timing tRSL RESET Read/Write Operation External fetch (no wait): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS t ADH Instruction code tRDAD tRDD1 tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (wait insertion): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH tRDAD Instruction code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL Data Sheet U13732EJ1V0DS tWTRD 49 µPD780065 External data access (no wait): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Hi-Z tRDAD tRDD2 Lower 8-bit address tADS tADH tASTH Hi-Z Write data Read data tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRADH tWRWD WR tASTWR tWRL1 External data access (wait insertion): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH tASTH Hi-Z Read data Hi-Z Write data tRDAD tRDH tRDD2 ASTB tASTRD RD tRDWD tRDL2 tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT 50 Data Sheet U13732EJ1V0DS tWTWR µPD780065 Serial Transfer Timing SIO3n 3-wire serial I/O mode: tKCY1, 2 tKL1, 2 tKH1, 2 SCK3n tKSI1, 2 tSIK1, 2 Input data SI3n tKSO1, 2 SO3n Output data Remark n = 0, 1 SIO1 3-wire serial I/O mode: tKCY3, 4 tR tKL3, 4 tKH3, 4 tF SCK1 tSIK3, 4 tKSI3, 4 Input data SI1 tKSO3, 4 SO1 Output data Data Sheet U13732EJ1V0DS 51 µPD780065 UART mode (external clock input): t KCY5 t KL5 t KH5 ASCK0 A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution Overall MIN. TYP. MAX. Unit 8 8 8 bit ±0.6 %FSR errorNote Conversion time tCONV 19 96 µs Analog input voltage VIAN 0 AVREF V Resistance between AVREF and AVSS RREF When A/D converter not operating 20 40 kΩ Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value. Analog input pin input impedance [Equivalent circuit] R1 C1 R2 C2 C3 [Parameter value] [TYP.] 52 AVDD [V] R1 [kΩ] R2 [kΩ] C1 [pF] C2 [pF] C3 [pF] 2.7 12 8.0 3.0 3.0 2.0 4.5 4 2.7 3.0 1.4 2.0 Data Sheet U13732EJ1V0DS µPD780065 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention power supply voltage VDDDR Data retention power supply current IDDDR Release signal set time tSREL Oscillation stabilization time tWAIT Conditions MIN. TYP. 1.6 Subsystem clock stop (XT1 = VDD) and feedback resistor disconnected 0.1 MAX. Unit 5.5 V 30 µA µs 0 Release by RESET 217/fX s Release by interrupt request Note s Note Selection of 212/fX and 2 14/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP Instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U13732EJ1V0DS 53 µPD780065 12. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G H I M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.20±0.20 B 14.00±0.20 C 14.00±0.20 D 17.20±0.20 F 0.825 G 0.825 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.60±0.20 L 0.80±0.20 M 0.17 +0.03 −0.07 N P Q R S 0.10 1.40±0.10 0.125±0.075 3° +7° −3° 1.70 MAX. P80GC-65-8BT-1 Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version. 54 Data Sheet U13732EJ1V0DS µPD780065 13. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 13-1. Surface Mounting Type Soldering Conditions µ PD780065GC-×××-8BT: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Caution — Do not use different soldering methods together (except for partial heating). Data Sheet U13732EJ1V0DS 55 µPD780065 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for developing systems using the µPD780065 Subseries. Refer to (5) Cautions on using development tools. (1) Language processing software RA78K0 Assembler package common to the 78K/0 Series CC78K0 C compiler package common to the 78K/0 Series DF780066 Device file for the µPD780065 Subseries CC78K0-L C compiler library source file common to the 78K/0 Series (2) Flash memory writing tools Flashpro III Dedicated flash programmer for microcontrollers incorporating flash memory (Part number: FL-PR3, PG-FP3) FA-80GC Adapter for flash memory writing (3) Debugging tools • When using IE-78K0-NS in-circuit emulator IE-78K0-NS In-circuit emulator common to the 78K/0 Series IE-70000-MC-PS-B Power supply unit for the IE-78K0-NS IE-78K0-NS-PA Performance board to enhance/extend the functions of the IE-78K0-NS IE-70000-98-IF-C Adapter necessary when a PC-9800 series computer (except notebook-type PC) is used as the host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable necessary when a PC-9800 series notebook-type PC is used as the host machine (PCMCIA socket supported) IE-70000-PC-IF-C Adapter necessary when an IBM PC/ATTM compatible is used as the host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when a PC incorporating a PCI bus is used as the host machine IE-780066-NS-EM4Note Emulation board to emulate the µPD780065 Subseries IE-78K0-NS-P01 I/O board necessary when emulating the µPD780065 Subseries NP-80GC Emulation probe for an 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the board of the target system for an 80-pin plastic QFP (GC-8BT type) and NP-80GC ID78K0-NS Integrated debugger for the IE-78K0-NS SM78K0 System simulator common to the 78K/0 Series DF780066 Device file for the µPD780065 Subseries Note Under development 56 Data Sheet U13732EJ1V0DS µPD780065 • When using IE-78001-R-A in-circuit emulator IE-78001-R-A In-circuit emulator common to the 78K/0 Series IE-70000-98-IF-C Adapter necessary when a PC-9800 series computer (except notebook-type PC) is used as the host machine (C bus supported) IE-70000-PC-IF-C Adapter necessary when an IBM PC/AT compatible is used as the host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when a PC incorporating a PCI bus is used as the host machine IE-78000-R-SV3 Interface adapter and cable necessary when an EWS is used as the host machine IE-780066-NS-EM4Note Emulation board to emulate the µPD780065 Subseries IE-78K0-NS-P01 I/O board necessary when emulating the µ PD780065 Subseries IE-78K0-R-EX1 Emulation probe conversion board necessary when the IE-780066-NS-EM4 + IE-78K0-NS-P01 is used in the IE-78001-R-A EP-78230GC-R Emulation probe for an 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the board of the target system for an 80-pin plastic QFP (GC-8BT type) and EP-78230GC-R ID78K0 Integrated debugger for the IE-78001-R-A SM78K0 System simulator common to the 78K/0 Series DF780066 Device file for the µPD780065 Subseries Note Under development (4) Real-time OS RX78K0 Real-time OS for the 78K/0 Series MX78K0 OS for the 78K/0 Series Data Sheet U13732EJ1V0DS 57 µPD780065 (5) Cautions on using development tools • The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780066. • The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780066. • FL-PR3, FA-80GC, and NP-80GC are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-8223813). • Refer to the Single-chip Microcontroller Development Tool Selection Guide (U11069E) for information on third party development tools. • Host machines and OSs compatible with the software are as follows: Host Machine [OS] Software PC PC-9800 series [Japanese WindowsTM] IBM PC/AT compatibles [Japanese/English Windows] EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] RA78K0 √Note √ CC78K0 √Note √ ID78K0-NS √ — ID78K0 √ √ SM78K0 √ — RX78K0 √Note √ MX78K0 √ √ Note Note DOS based software 58 Data Sheet U13732EJ1V0DS µPD780065 APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name µPD780065 Subseries User’s Manual Document No. Under preparation µPD780065 Data Sheet This document µPD78F0066 Data Sheet Under preparation 78K/0 Series User’s Manual Instruction U12326E Documents Related to Development Tools (User’s Manuals) Document Name RA78K0 Assembler Package CC78K/0 C Compiler Document No. Operation U11802E Language U11801E Structured Assembly Language U11789E Operation U11517E Language U11518E IE-78K0-NS In-Circuit Emulator U13731E IE-78001-R-A In-Circuit Emulator To be prepared IE-780066-NS-EM4 Emulation Board To be prepared EP-78230 Emulation Probe EEU-1515 SM78K0S, SM78K0 System Simulator Ver. 2.10 or Operation U14611E Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications To be prepared ID78K0-NS Integrated Debugger Ver. 2.00 or Later Operation U14379E ID78K0-NS, ID78K0S-NS Integrated Ver. 2.20 or Later Windows Based Operation U14910E ID78K0 Integrated Debugger EWS Based Reference — ID78K0 Integrated Debugger Windows Based Reference U11539E Guide U11649E Windows Based Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U13732EJ1V0DS 59 µPD780065 Documents Related to Embedded Software (User’s Manuals) Document Name 78K/0 Series Real-time OS OS for 78K/0 Series MX78K0 Document No. Basics U11537E Installation U11536E Basics U12257E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products & Packages - (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 60 Data Sheet U13732EJ1V0DS µPD780065 [MEMO] Data Sheet U13732EJ1V0DS 61 µPD780065 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS and Solaris are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 62 Data Sheet U13732EJ1V0DS µPD780065 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U13732EJ1V0DS 63 µPD780065 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of January, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4