DATA SHEET MOS INTEGRATED CIRCUIT µPD78F9046 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78F9046 is a µPD789046 Subseries product (small-scale package, general-purpose applications) of the 78K/0S Series. The µPD78F9046 has flash memory in place of the internal ROM of the µPD789046. Because flash memory allows the program to be written and erased with the device mounted on the target board, this product is ideal for development trials, small-scale production, or for applications that require frequent upgrades. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. U13600E µPD789046 Subseries User’s Manual: 78K/0S Series User’s Manual — Instruction: U11047E FEATURES • • • • • • • • Pin-compatible with mask ROM version (except VPP pin) Flash memory: 16 Kbytes Internal high-speed RAM: 512 bytes Minimum instruction execution time can be changed from high-speed (0.4 µs; @5.0-MHz operation with main system clock) to ultra-low-speed (122 µs: @32.768-kHz operation with subsystem clock) I/O ports: 34 Serial interface: 1 channel 3-wire serial I/O mode/UART mode can be selected Timer: 4 channels 1 channel • 16-bit timer: • 8-bit timer/event counter: 1 channel 1 channel • Watch timer: 1 channel • Watchdog timer: Power supply voltage: VDD = 1.8 to 5.5 V APPLICATIONS Cordless phones, etc. ORDERING INFORMATION Part Number µPD78F9046GB-8ES Package 44-pin plastic LQFP (10 × 10 mm) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13546EJ1V0DSJ1 (1st edition) Date Published October 2000 N CP(K) Printed in Japan The mark shows revised points. © 1998, 1999 µPD78F9046 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Product in mass production Product under development Y subseries products support the SMB (System Management Bus) Small-scale package, general-purpose applications µ PD789026 with subsystem clock 44-pin µ PD789046 42/44-pin µ PD789026 µ PD789014 with enhanced timer. Expanded ROM and RAM 28-pin µ PD789014 On-chip UART. Capable of low-voltage (1.8-V) operation Small-scale package, general-purpose applications + A/D 78K/0S Series 44/48-pin µ PD789217AY RC oscillation version of µPD789197AY 44/48-pin µ PD789197AY µPD789177 with on-chip EEPROMTM and SMB 44-pin µ PD789177 µ PD789177Y µ PD789167 with enhanced A/D 44-pin µ PD789167 µ PD789167Y µ PD789104A with enhanced timer 30-pin µ PD789156 µ PD789146 with enhanced A/D 30-pin 30-pin µ PD789146 µ PD789134A µ PD789104A with EEPROM µ PD789124A with enhanced A/D 30-pin µ PD789124A RC oscillation version of µ PD789104A 30-pin µ PD789114A µ PD789104A with enhanced A/D 30-pin µ PD789104A µ PD789026 with A/D and multiplier Inverter control µ PD789842 44-pin On-chip inverter control circuit and UART LCD drive 88-pin µ PD789830 80-pin µ PD789417A µ PD789407A with enhanced A/D 80-pin 64-pin µ PD789407A µ PD789456 with enhanced I/O µ PD789456 µPD789446 with enhanced A/D 64-pin µ PD789446 RC oscillation version of µ PD789426 64-pin µ PD789436 µ PD789426 with enhanced A/D 64-pin µ PD789426 µ PD789306 with A/D 64-pin µ PD789316 RC oscillation version of µ PD789306 64-pin µ PD789306 Basic subseries for LCD drive 44-pin µ PD789800 For PC keyboard. On-chip USB function 44-pin µ PD789840 For keypad. On-chip POC 20-pin µ PD789861 RC oscillation version of µ PD789860 20-pin µ PD789860 For keyless entry. On-chip POC and key return circuit On-chip UART, dot LCD ASSP 2 Data Sheet U13546EJ1V0DS00 µPD78F9046 The major functional differences among the subseries are listed below. Function Subseries Name ROM Capacity Small-scale µPD789046 16 K package, µPD789026 4 K to 16 K generalµPD789014 2 K to 4 K purpose applications Smallscale package, generalpurpose applications + A/D Timer 8-bit 16-bit Watch WDT 1 ch 1 ch 1 ch 1 ch 8-Bit A/D 10-Bit A/D Serial Interface I/O VDD MIN. Value — — 1 ch (UART:1 ch) 34 1.8 V — — 2 ch 22 — µPD789177 16 K to 24 K — 8 ch 8 ch — — 4 ch 4 ch — — 4 ch µPD789124A 4 ch — µPD789114A — 4 ch µPD789104A 4 ch — µPD789167 µPD789156 8 K to 16 K Remark 1 ch — µPD789146 µPD789134A 2 K to 8 K 1 ch (UART: 1 ch) 31 — On-chip EEPROM 20 RC oscillation version — Inverter control µPD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch — 1 ch (UART: 1 ch) 30 4.0 V — LCD drive µPD789830 24 K 1 ch 1 ch 1 ch 1 ch — — 1 ch (UART: 1 ch) 30 2.7 V — µPD789417A 12 K to 24 K 3 ch 43 1.8 V 7 ch µPD789407A 7 ch — — 6 ch µPD789446 6 ch — µPD789436 — 6 ch µPD789426 6 ch — µPD789456 12 K to 16 K 2 ch µPD789316 8 K to 16 K 1 ch (UART: 1 ch) 40 2 ch (UART: 1 ch) — 30 RC oscillation version 23 µPD789306 ASSP µPD789800 8 K — 2 ch 1 ch µPD789840 µPD789861 4 K — 1 ch — — 4 ch — — µPD789860 2 ch (USB: 1 ch) 31 4.0 V 1 ch 29 2.8 V 14 1.8 V — — RC oscillation version — Note 10-bit timer: 1 channel Data Sheet U13546EJ1V0DS00 3 µPD78F9046 OVERVIEW OF FUNCTIONS Item Internal memory Flash memory 16 Kbytes High-speed RAM 512 bytes Minimum instruction execution time 0.4 µs/1.6 µs (@ 5.0-MHz operation with main system clock) 122 µs (@32.768-kHz operation with subsystem clock) General-purpose registers 8 bits × 8 registers Instruction set • 16-bit operation • Bit manipulation (set, reset, test), etc. I/O ports • CMOS I/O: 34 Serial interface • 3-wire serial I/O mode/UART mode selectable: 1 channel Timer • • • • Timer outputs 2 Vectored interrupt sources 4 Function 16-bit timer: 8-bit timer/event counter: Watch timer: Watchdog timer: Maskable Internal: 7, External: 4 Non-maskable Internal: 1 1 channel 1 channel 1 channel 1 channel Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = −40 to +85°C Package 44-pin plastic LQFP (10 × 10 mm) Data Sheet U13546EJ1V0DS00 µPD78F9046 CONTENTS 1. PIN CONFIGURATION (TOP VIEW)................................................................................................ 6 2. BLOCK DIAGRAM ........................................................................................................................... 7 3. PIN FUNCTIONS .............................................................................................................................. 8 3.1 Port Pins ................................................................................................................................................ 8 3.2 Non-Port Pins ........................................................................................................................................ 9 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.................................................... 10 4. MEMORY SPACE ............................................................................................................................. 12 5. 6. PROGRAMMING FLASH MEMORY............................................................................................... 13 5.1 Selecting Communication Mode......................................................................................................... 13 5.2 Function of Flash Memory Programming .......................................................................................... 14 5.3 Connecting Flashpro III ...................................................................................................................... 14 5.4 Example of Settings for Flashpro III (PG-FP3)................................................................................... 16 INSTRUCTION SET OVERVIEW .................................................................................................... 17 6.1 Conventions ......................................................................................................................................... 17 6.2 Operations ............................................................................................................................................ 19 7. ELECTRICAL SPECIFICATIONS ................................................................................................... 24 8. CHARACTERISTICS CURVES....................................................................................................... 36 9. PACKAGE DRAWINGS .................................................................................................................. 37 10. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 38 APPENDIX A DIFFERENCES BETWEEN µPD78F9046 AND MASK ROM VERSIONS.................... 39 APPENDIX B DEVELOPMENT TOOLS .............................................................................................. 40 APPENDIX C RELATED DOCUMENTS.............................................................................................. 42 Data Sheet U13546EJ1V0DS00 5 µPD78F9046 1. PIN CONFIGURATION (TOP VIEW) • 44-pin plastic LQFP (10 × 10 mm) P03 P02 P01 P00 VDD1 VSS1 P17 P16 P15 P14 P13 µPD78F9046GB-8ES 44 43 42 41 40 39 38 37 36 35 34 P12 1 33 P04 P11 2 32 P05 P10 3 31 P06 P47/KR07 4 30 P07 P46/KR06 5 29 P20/SCK20/ASCK20 P45/KR05 6 28 P21/SO20/TxD20 P44/KR04 7 27 P22/SI20/RxD20 P43/KR03 8 26 P23/SS20 P42/KR02 9 25 P24/INTP0 P41/KR01 10 24 P25/INTP1 P40/KR00 11 23 P26/INTP2/CPT90 Caution P27/TI80/TO80 P30/TO90 RESET XT1 XT2 VDD0 VSS0 X1 X2 VPP P31/BZO90 12 13 14 15 16 17 18 19 20 21 22 Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode. ASCK20: Asynchronous Serial Input SCK20: Serial Clock BZO90: Buzzer Output SI20: Serial Input CPT90: Capture Trigger Input SO20: Serial Output INTP0 to INTP2: Interrupt from Peripherals SS20: Chip Select Input KR00 to KR07: Key Return TI80: Timer Input P00 to P07: Port 0 TO80, TO90: Timer Output P10 to P17: Port 1 TxD20: Transmit Data P20 to P27: Port 2 VDD0, VDD1: Power Supply P30, P31: Port 3 VPP: Programming Power Supply P40 to P47: Port 4 VSS0, VSS1: Ground RESET: Reset X1, X2: Crystal (Main System Clock) RxD20: Receive Data XT1, XT2: Crystal (Subsystem Clock) 6 Data Sheet U13546EJ1V0DS00 µPD78F9046 2. BLOCK DIAGRAM TI80/TO80/P27 CPT90/INTP2/P26 TO90/P30 BZO90/P31 8-bit TIMER/ EVENT COUNTER80 PORT0 P00 to P07 16-bit TIMER90 PORT1 P10 to P17 PORT2 P20 to P27 PORT3 P30,P31 PORT4 P40 to P47 WATCH TIMER 78K/0S CPU CORE FLASH MEMORY WATCHDOG TIMER SCK20/ASCK20/P20 SO20/TxD20/P21 Sl20/RxD20/P22 SS20/P23 INTP0/P24 INTP1/P25 INTP2/CPT90/P26 KR00/P40 to KR07/P47 SERIAL INTERFACE20 RAM SYSTEM CONTROL INTERRUPT CONTROL VDD0 VSS0 VDD1 VSS1 RESET X1 X2 XT1 XT2 VPP Data Sheet U13546EJ1V0DS00 7 µPD78F9046 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O P00 to P07 I/O Port 0 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input — P10 to P17 I/O Port 1 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input — P20 I/O Port 2 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input SCK20/ASCK20 P21 P22 After Reset Alternate Function SO20/TxD20 SI20/RxD20 P23 SS20 P24 INTP0 P25 INTP1 P26 INTP2/CPT90 P27 TI80/TO80 P30 I/O P31 P40 to P47 8 Function I/O Port 3 2-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input Port 4 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input Data Sheet U13546EJ1V0DS00 TO90 BZO90 KR00 to KR07 µPD78F9046 3.2 Non-Port Pins Pin Name INTP0 I/O Input INTP1 Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Alternate Function Input P24 P25 INTP2 P26/CPT90 KR00 to KR07 Input Key return signal detection Input P40 to P47 SI20 Input Serial interface serial data input Input P22/RxD20 SO20 Output Serial interface serial data output Input P21/TxD20 SCK20 I/O Serial interface serial clock input/output Input P20/ASCK20 SS20 Input Chip select input for serial interface Input P23 ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20 RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20 TI80 Input External count clock input to 8-bit timer 80 Input P27/TO80 TO80 Output 8-bit timer 80 output Input P27/TI80 TO90 Output 16-bit timer 90 output Input P30 BZO90 Output 16-bit timer 90 buzzer output Input P31 CPT90 Input Capture edge input Input P26/INTP2 X1 Input Connecting crystal resonator for main system clock oscillation X2 − − − − − − − − − XT1 Input XT2 − VDD0 − Positive power supply of ports − − VDD1 − Positive power supply (except ports) − − VSS0 − Ground potential of ports − − VSS1 − Ground potential (except ports) − − RESET VPP Input − Connecting crystal resonator for subsystem clock oscillation System reset input Input Flash memory programming mode setting. High-voltage application for program write/verify. Connect directly to VSS0 or VSS1 in normal operation mode. Data Sheet U13546EJ1V0DS00 − − − 9 µPD78F9046 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Input/Output Circuits and Recommended Connection of Unused Pins Pin Name P00 to P07 I/O Circuit Type 5-H I/O I/O Input: P10 to P17 P20/SCK20/ASCK20 Recommended Connection of Unused Pins Independently connect to VDD0 or VDD1, or VSS0 or VSS1 via a resistor. Output: Leave open. 8-C P21/SO20/TxD20 P22/SI20/RxD20 P23/SS20 P24/INTP0 P25/INTP1 P26/INTP2/CPT90 P27/TI80/TO80 P30/TO90 5-H P31/BZO90 P40/KR00 to P47/KR07 XT1 8-C − Input − XT2 RESET 2 VPP − 10 Connect to VSS0 or VSS1. Leave open. − Input − Connect directly to VSS0 or VSS1. Data Sheet U13546EJ1V0DS00 µPD78F9046 Figure 3-1. Pin Input/Output Circuits Type 2 Type 8-C VDD0 Pullup enable P-ch VDD0 IN Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch VSS0 Type 5-H VDD0 Pullup enable P-ch VDD0 Data P-ch IN/OUT Output disable N-ch VSS0 Input enable Data Sheet U13546EJ1V0DS00 11 µPD78F9046 4. MEMORY SPACE The µPD78F9046 can access up to 64 Kbytes of memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved Data memory space 3FFFH 4000H 3FFFH Program area Program memory space On-chip flash memory 16384 × 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 001AH 0019H 0000H 12 0000H Data Sheet U13546EJ1V0DS00 Vector table area µPD78F9046 5. PROGRAMMING FLASH MEMORY The program memory that is incorporated in the µPD78F9046 is flash memory. With flash memory, it is possible to write programs on-board. Writing is performed by connecting a dedicated flash programmer (Flashpro III, (Part No. FL-PR3, PG-FP3)) to the host machine and the target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 5.1 Selecting Communication Mode Writing to flash memory is performed using the Flashpro III in a serial communication mode. Select one of the communication modes in Table 5-1. The selection of the communication mode is made by using the format shown in Figure 5-1. Each communication mode is selected using the number of VPP pulses shown in Table 5-1. Table 5-1. List of Communication Mode Communication Mode Pins VPP Pulses 3-wire serial I/O SCK20/ASCK20/P20 SO20/TxD20/P21 SI20/RxD20/P22 0 UART TxD20/SO20/P21 RxD20/SI20/P22 8 P00 (Serial clock input) P01 (Serial data output) P02 (Serial data input) 12 Pseudo 3-wire Note Note Serial transfer is carried out by controlling ports with software. Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 5-1. Figure 5-1. Format of Communication Mode Selection 10 V VPP VDD 1 2 n VSS RESET VDD VSS Data Sheet U13546EJ1V0DS00 13 µPD78F9046 5.2 Function of Flash Memory Programming Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 5-2 shows the major functions of flash memory programming. Table 5-2. Major Function of Flash Memory Programming Function Description Batch erase Deletes the entire memory contents Batch blank check Checks the deletion status of the entire memory Data write Performs a write operation to the flash memory based on the write start address and the number of data to be written (number of bytes). Batch verify Compares the entire memory contents with the input data. 5.3 Connecting Flashpro III The connection of the Flashpro III and the µPD78F9046 differs according to the communication mode (3-wire serial I/O, UART, and pseudo 3-wire). The connections for each communication mode are shown in Figures 5-2, 5-3, and 5-4, respectively. Figure 5-2. Connection of Flashpro III When Using 3-Wire Serial I/O Mode µ PD78F9046 Flashpro III VPPnNote VPP VDD VDD0, VDD1 RESET RESET CLK X1 SCK SCK20 SO SI20 SI SO20 VSS0, VSS1 GND Note n = 0, 1 14 Data Sheet U13546EJ1V0DS00 µPD78F9046 Figure 5-3. Connection of Flashpro III When Using UART Mode µPD78F9046 Flashpro III VPPnNote VPP VDD VDD0, VDD1 RESET RESET CLK X1 SO RxD20 SI TxD20 VSS0, VSS1 GND Note n = 0, 1 Figure 5-4. Connection of Flashpro III When Using Pseudo 3-Wire (When P0 Is Used) µ PD78F9046 Flashpro III VPPnNote VPP VDD VDD0, VDD1 RESET RESET CLK X1 SCK P00 (Serial clock) SO P02 (Serial input) SI P01 (Serial output) GND VSS0, VSS1 Note n = 0, 1 Data Sheet U13546EJ1V0DS00 15 µPD78F9046 5.4 Example of Settings for Flashpro III (PG-FP3) When writing to flash memory using Flashpro III (PG-FP3), make the following settings. <1> Load a parameter file. <2> Select the mode of serial communication and serial clock with a type command. <3> Make the settings according to the example of settings for PG-FP3 shown below. Table 5-3. Example of Settings for PG-FP3 Communication Mode 3-wire serial I/O Note 1 VPP Pulse Number Example of Settings for PG-FP3 COMM PORT SIO-ch0 0 CPU CLK On Target Board In Flashpro UART Pseudo 3-wire On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT UART-ch0 CPU CLK On Target Board On Target Board 4.1943 MHz UART BPS 9600 bps COMM PORT Port A CPU CLK On Target Board 8 Note 2 12 In Flashpro On Target Board 4.1943 MHz SIO CLK 1 kHz In Flashpro 4.0 MHz SIO CLK 1 kHz Notes 1. This is the number of VPP pulses that are supplied by the Flashpro III at serial communication initialization. The pins that will be used for communication are determined according to this number. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT: Serial port selection 16 SIO CLK: Serial clock frequency selection CPU CLK: Input CPU clock source selection Data Sheet U13546EJ1V0DS00 µPD78F9046 6. INSTRUCTION SET OVERVIEW The instruction set for the µPD78F9046 is listed later in this section. 6.1 Conventions 6.1.1 Operand identifiers and descriptions The description made in the operand field of each instruction conforms to the operand identifier for the instructions listed below (the details conform to the assembly specifications). If more than one operand identifier is listed for an instruction, one is selected. Uppercase letters, #, !, $, and [ ] are used to specify keywords, which must be written exactly as they appear. The meanings of these special characters are as follows: • #: Immediate data specification • $: Relative address specification • !: Absolute address specification • [ ]: Indirect address specification Immediate data should be described using appropriate values or labels. The specification of values and labels must be accompanied by #, !, $, or [ ]. Operand registers, expressed by the identifiers r or rp, can be described using both functional names (X, A, C, etc.) and absolute names (R0, R1, R2, and other names listed inside the parentheses in Table 6-1). Table 6-1. Operand Formats and Descriptions Identifier Description r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH: Immediate data or label FE20H to FF1FH: Immediate data or label (even addresses only) addr16 addr5 0000H to FFFFH: Immediate data or label (only even address for 16-bit data transfer instructions) 0040H to 007FH: Immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Data Sheet U13546EJ1V0DS00 17 µPD78F9046 6.1.2 Descriptions of the operation field A: A register (8-bit accumulator) X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair (16-bit accumulator) BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag to indicate that a non-maskable interrupt is being handled (): Contents of a memory location indicated by a parenthesized address or register name XH, XL: Upper and lower 8 bits of a 16-bit register ∧: Logical product (AND) ∨: ∨: Logical sum (OR) : Exclusive OR Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 6.1.3 Description of the flag operation field (blank): No change 18 0: To be cleared to 0 1: To be set to 1 ×: To be set or cleared according to the result R: To be restored to the previous value Data Sheet U13546EJ1V0DS00 µPD78F9046 6.2 Operations Flag Mnemonic Operand Byte Clock Operation Z MOV r, #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte 3 6 sfr ← byte A, r Note 1 2 4 A←r r, A Note 1 2 4 r←A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A 1 4 A↔X 2 6 A↔r A, saddr 2 6 A ↔ (saddr) A, sfr 2 6 A ↔ (sfr) A, [DE] 1 8 A ↔ (DE) A, [HL] 1 8 A ↔ (HL) A, [HL + byte] 2 8 A ↔ (HL + byte) rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) sfr, #byte XCH A, X A, r MOVW Note 2 2 8 (saddrp) ← AX AX, rp Note 3 1 4 AX ← rp rp, AX Note 3 1 4 rp ← AX saddrp, AX AC CY × × × × × × Notes 1. Except when r = A. 2. Except when r = A or X. 3. Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU), specified by the processor clock control register (PCC). Data Sheet U13546EJ1V0DS00 19 µPD78F9046 Flag Mnemonic Operand Byte Clock Operation Z 8 AX ↔ rp A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × × × A, [HL] 1 6 A, CY ← A + (HL) × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × × AX, rp ADD ADDC SUB SUBC AND AC CY 1 XCHW Note A, #byte 2 4 A, CY ← A + byte + CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × × A, r 2 4 A, CY ← A + r + CY × × × A, saddr 2 4 A, CY ← A + (saddr) + CY × × × A, !addr16 3 8 A, CY ← A + (addr16) + CY × × × A, [HL] 1 6 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × × A, #byte 2 4 A, CY ← A − byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte × × × A, r 2 4 A, CY ← A − r × × × A, saddr 2 4 A, CY ← A − (saddr) × × × A, !addr16 3 8 A, CY ← A − (addr16) × × × A, [HL] 1 6 A, CY ← A − (HL) × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) × × × A, #byte 2 4 A, CY ← A − byte − CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × × A, r 2 4 A, CY ← A − r − CY × × × A, saddr 2 4 A, CY ← A − (saddr) − CY × × × A, !addr16 3 8 A, CY ← A − (addr16) − CY × × × A, [HL] 1 6 A, CY ← A − (HL) − CY × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY × × × A, #byte 2 4 A ← A ∧ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte × A, r 2 4 A←A∧r × A, saddr 2 4 A ← A ∧ (saddr) × A, !addr16 3 8 A ← A ∧ (addr16) × A, [HL] 1 6 A ← A ∧ (HL) × A, [HL + byte] 2 6 A ← A ∧ (HL + byte) × Note Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU), specified by the processor clock control register (PCC). 20 Data Sheet U13546EJ1V0DS00 µPD78F9046 Flag Mnemonic Operand Byte Clock Operation Z AC CY A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨ r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A − byte × × × saddr, #byte 3 6 (saddr) − byte × × × A, r 2 4 A−r × × × A, saddr 2 4 A − (saddr) × × × A, !addr16 3 8 A − (addr16) × × × A, [HL] 1 6 A − (HL) × × × A, [HL + byte] 2 6 A − (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX − word × × × CMPW AX, #word 3 6 AX − word × × × INC r 2 4 r←r+1 × × saddr 2 4 (saddr) ← (saddr) + 1 × × r 2 4 r←r−1 × × saddr 2 4 (saddr) ← (saddr) − 1 × × INCW rp 1 4 rp ← rp + 1 DECW rp 1 4 rp ← rp − 1 ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 × ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 × RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 × ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 × OR XOR CMP DEC Remark The instruction clock cycle is based on the CPU clock (fCPU), specified by the processor clock control register (PCC). Data Sheet U13546EJ1V0DS00 21 µPD78F9046 Flag Mnemonic Operand Byte Clock Operation Z AC CY saddr. bit 3 6 (saddr. bit) ← 1 sfr. bit 3 6 sfr. bit ← 1 A. bit 2 4 A. bit ← 1 PSW. bit 3 6 PSW. bit ← 1 [HL]. bit 2 10 (HL). bit ← 1 saddr. bit 3 6 (saddr. bit) ← 0 sfr. bit 3 6 sfr. bit ← 0 A. bit 2 4 A. bit ← 0 PSW. bit 3 6 PSW. bit ← 0 [HL]. bit 2 10 (HL). bit ← 0 SET1 CY 1 2 CY ← 1 1 CLR1 CY 1 2 CY ← 0 0 NOT1 CY 1 2 CY ← CY × CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, PC ← addr16, SP ← SP − 2 CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP − 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, AX 2 8 SP ← AX AX, SP 2 6 AX ← SP !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PCH ← A, PCL ← X SET1 CLR1 PUSH POP MOVW BR Remark × × × × × R R R R R R The instruction clock cycle is based on the CPU clock (fCPU), specified by the processor clock control register (PCC). 22 × Data Sheet U13546EJ1V0DS00 µPD78F9046 Flag Mnemonic Operand Byte Clock Operation Z BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0 NOP 1 2 No Operation EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ Remark AC CY The instruction clock cycle is based on the CPU clock (fCPU), specified by the processor clock control register (PCC). Data Sheet U13546EJ1V0DS00 23 µPD78F9046 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Conditions Ratings Unit VDD –0.3 to +6.5 V VPP –0.3 to +10.5 V Input voltage VI –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V Output current, high IOH Per pin –10 mA Total for all pins –30 mA Per pin 30 mA Total for all pins 160 mA –40 to +85 °C 10 to 40 °C –40 to +125 °C Output current, low Operating ambient temperature IOL TA In normal operation mode During flash memory programming Storage temperature Tstg Caution Product quality may suffer if the maximum absolute ratings exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 24 Data Sheet U13546EJ1V0DS00 µPD78F9046 Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit VPP X1 C1 Crystal resonator X2 C2 VPP X1 C1 External clock X1 X2 C2 X2 X1 Parameter Conditions MIN. Oscillation frequency Note 1 (fX) VDD = Oscillation voltage range 1.0 Oscillation stabilization Note 2 time After VDD reaches the oscillation voltage range MIN. Oscillation frequency Note 1 (fX) TYP. 1.0 Oscillation stabilization Note 2 time VDD = 4.5 to 5.5 V Note 1 MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 30 ms X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns Note 1 X2 X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz OPEN X1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation is stabilized within the oscillation stabilization wait time. Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS0. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U13546EJ1V0DS00 25 µPD78F9046 Subsystem Clock Oscillator Characteristics (TA = −40 to +85°°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Crystal resonator VPP XT1 C3 External clock XT1 XT2 R C4 XT2 Parameter Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s 10 s 32 35 kHz 14.3 15.6 µs Oscillation frequency Note 1 (fXT) Oscillation stabilization Note 2 time XT1 input frequency (fXT) VDD = 4.5 to 5.5 V Note 1 X1 input high-/low-level width (tXTH, tXTL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation is stabilized within the oscillation stabilization wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuation current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS0. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 26 Data Sheet U13546EJ1V0DS00 µPD78F9046 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Output current, high IOH Output current, low IOL Input voltage, high VIH1 Conditions MIN. TYP. MAX. Unit Per pin –1 mA Total for all pins –15 mA Per pin 10 mA Total for all pins VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 P00 to P07, P10 to P17, P30, P31 VDD = 2.7 to 5.5 V RESET, P20 to P27, P40 to P47, VDD = 2.7 to 5.5 V X1, X2 VDD = 4.5 to 5.5 V XT1, XT2 VDD = 4.5 to 5.5 V P00 to P07, P10 to P17, P30, P31 VDD = 2.7 to 5.5 V RESET, P20 to P27, P40 to P47 VDD = 2.7 to 5.5 V X1, X2 VDD = 4.5 to 5.5 V 80 mA 0.7VDD VDD V 0.9VDD VDD V 0.8VDD VDD V 0.9VDD VDD V VDD – 0.5 VDD V VDD – 0.1 VDD V VDD – 0.5 VDD V VDD – 0.1 VDD V 0 0.3VDD V 0 0.1VDD V 0 0.2VDD V 0 0.1VDD V 0 0.4 V 0 0.1 V 0 0.4 V 0 0.1 VIL4 XT1, XT2 Output voltage, high VOH VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V VDD = 1.8 to 5.5 V, IOH = −100 µA VDD – 0.5 V Output voltage, low VOL Input leakage current, high ILIH1 Input leakage current, low ILIL1 VDD = 4.5 to 5.5 V V VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 µA 0.5 V Pins other than X1, X2, XT1, XT2 3 µA X1, X2 20 µA Pins other than X1, X2, XT1, XT2 –3 µA X1, X2 –20 µA VIN = VDD ILIH2 VIN = 0 V ILIL2 Output leakage current, high ILOH VOUT = VDD 3 µA Output leakage current, low ILOL VOUT = 0 V –3 µA Software pull-up resistor R VIN = 0 V 200 kΩ Remark 50 100 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U13546EJ1V0DS00 27 µPD78F9046 DC Characteristics (TA = −40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Symbol Supply current Note 1 IDD1 IDD2 IDD3 IDD4 IDD5 Conditions MIN. TYP. MAX. Unit 5.0-MHz crystal oscillation operating mode (C1 = C2 = 22 pF) VDD = 5.0 V ± 10% Note 3 4.2 15 mA VDD = 3.0 V ± 10% Note 4 1.0 5.0 mA VDD = 2.0 V ± 10% Note 4 0.8 3.0 mA 5.0-MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) VDD = 5.0 V ± 10% Note 3 0.8 5.0 mA VDD = 3.0 V ± 10% Note 4 0.5 2.5 mA VDD = 2.0 V ± 10% Note 4 0.3 1.0 mA 32.768-kHz crystal oscillation operating Note 2 mode (C3 = C4 = 22 pF, R = 220 kΩ) VDD = 5.0 V ± 10% 200 750 µA VDD = 3.0 V ± 10% 150 600 µA VDD = 2.0 V ± 10% 130 450 µA 32.768-kHz crystal oscillation HALT Note 2 mode (C3 = C4 = 22 pF, R = 220 kΩ) VDD = 5.0 V ± 10% 25 150 µA VDD = 3.0 V ± 10% 10 90 µA VDD = 2.0 V ± 10% 3.5 60 µA VDD = 5.0 V ± 10% 0.1 30 µA VDD = 3.0 V ± 10% 0.05 10 µA VDD = 2.0 V ± 10% 0.05 10 µA STOP mode Notes 1. The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included. 2. Main system clock stopped. 3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 4. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 28 Data Sheet U13546EJ1V0DS00 µPD78F9046 Flash Memory Write/Erase Characteristics (TA = 10 to 40°°C, VDD = 1.8 to 5.5 V, in 5.0 MHz crystal oscillation operation mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write current (VDD pin) Note IDDW When VPP supply voltage = VPP1 18 mA Write current (VPP pin) Note IPPW When VPP supply voltage = VPP1 22.5 mA Erase current (VDD pin) Note IDDE When VPP supply voltage = VPP1 18 mA Erase current (VPP pin) Note IPPE When VPP supply voltage = VPP1 115 mA 1 s 20 s 20 Times 0.2VDD V 10.3 V Unit erase time ter Total erase time tera Write count VPP supply voltage 0.5 1 Erase/write are regarded as 1 cycle VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 Note The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included. Data Sheet U13546EJ1V0DS00 29 µPD78F9046 AC Characteristics (1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Symbol TCY Conditions Operating with main system clock MIN. VDD = 2.7 to 5.5 V Operating with subsystem clock TI80 input frequency fTI TI80 input high/low-level width tTIH, tTIL Interrupt input high-/low-level width tINTH, tINTL RESET input lowlevel width tRSL VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V INTP0 to INTP2 TCY vs. VDD (main system clock) 60 Cycle time TCY [ µ s] 10 8.0 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 Supply voltage VDD (V) 30 MAX. Unit 0.4 8 µs 1.6 8 µs 125 µs 0 4 MHz 0 275 kHz 114 Data Sheet U13546EJ1V0DS00 6 TYP. 122 0.1 µs 1.8 µs 10 µs 10 µs µPD78F9046 (2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK20...Internal clock) Parameter SCK20 cycle time Symbol tKCY1 SCK20 high-/lowlevel width tKH1, tKL1 SI20 setup time tSIK1 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V (to SCK20↑) SI20 hold time tKSI1 VDD = 2.7 to 5.5 V (from SCK20↑) SO20 output delay time from SCK20↓ tKSO1 R = 1 kΩ, C =100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY1/2 – 50 ns tKCY1/2 – 150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Note R and C are the load resistance and load capacitance of the SO20 output line, respectively. (b) 3-wire serial I/O mode (SCK20...External clock) Parameter SCK20 cycle time Symbol tKCY2 SCK20 high-/lowlevel width tKH2, tKL2 SI20 setup time (to SCK20↑) tSIK2 SI20 hold time (from tKSI2 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V SCK20↑) SO20 setup time (to SS20↓ when SS20 is used) tKAS2 SO20 disable time (to SS20↑ when SS20 is used) tKSD2 SO20 output delay time from SCK20↓ tKSO2 MIN. VDD = 2.7 to 5.5 V Unit ns 3500 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 120 ns 400 ns 240 ns 800 ns 0 300 ns 0 1000 ns VDD = 2.7 to 5.5 V Note MAX. 900 VDD = 2.7 to 5.5 V R = 1 kΩ, C =100 pF TYP. Note R and C are the load resistance and load capacitance of the SO20 output line, respectively. Data Sheet U13546EJ1V0DS00 31 µPD78F9046 (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. VDD = 2.7 to 5.5 V MAX. Unit 78125 bps 19531 bps MAX. Unit (d) UART mode (External clock input) Parameter Symbol ASCK20 cycle time tKCY3 ASCK20 high-/lowlevel width tKH3, tKL3 Transfer rate ASCK20 rise/fall time 32 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tR, tF Data Sheet U13546EJ1V0DS00 MIN. TYP. 900 ns 3500 ns 400 ns 1600 ns 39063 bps 9766 bps 1 µs µPD78F9046 AC Timing Test Points (Except the X1 and XT1 inputs) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXH tXL VIH3 (MIN.) X1 input VIL3 (MAX.) 1/fXT tXTL tXTH VIH4 XT1 input VIL4 (MIN.) (MAX.) TI Timing 1/fTI tTIL tTIH tINTL tINTH TI80 Interrupt Input Timing INTP0 to INTP2 RESET Input Timing tRSL RESET Data Sheet U13546EJ1V0DS00 33 µPD78F9046 Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm SI20 tKSIm Input data tKSOm SO20 Remark Output data m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 Output data SO20 UART mode (External clock input): tKCY3 tKL3 tKH3 tR ASCK20 34 Data Sheet U13546EJ1V0DS00 tF µPD78F9046 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 1.8 Release signal set time tSREL 0 Oscillation stabilization wait Note 1 time tWAIT TYP. MAX. Unit 5.5 V µs 15 Release by RESET Release by interrupt request 2 /fX ms Note 2 ms Notes 1. The oscillation stabilization wait time is the period when CPU operation is stopped in order to avoid unstable operation at the beginning of oscillation. 12 15 17 2. 2 /fX, 2 /fX, or 2 /fX can be selected according to the setting of bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS). Remark fX: Main system clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U13546EJ1V0DS00 35 µPD78F9046 8. CHARACTERISTICS CURVES IDD vs. VDD (fX = 5.0 MHz, fXT = 32.768 kHz) (TA = 25˚C) 10 PCC = 00H PCC = 02H PCC = 00H (HALT mode) 1.0 PCC = 02H (HALT mode) 0.5 Supply current IDD (mA) Subsystem clock operating mode (CSS0 = 1) 0.1 0.05 Subsystem clock operation HALT mode (CSS0 = 1) 0.01 0.005 X2 XT1 X1 22 pF XT2 Crystal resonator Crystal resonator 5.0 MHz 32.768 kHz 220 kΩ 33 pF 33 pF 22 pF VSS VSS 0.001 0 1 2 3 4 5 Supply voltage VDD (V) 36 Data Sheet U13546EJ1V0DS00 6 7 µPD78F9046 9. PACKAGE DRAWINGS 44 PIN PLASTIC LQFP (10x10) A B detail of lead end 23 22 33 34 S P C T D R 12 11 44 1 L U Q F J G H I M K M N S S NOTE ITEM Each lead centerline is located within 0.16 mm of its true position (T.P.) at maximum material condition. A 12.0±0.2 B 10.0±0.2 C 10.0±0.2 D 12.0±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I 0.2 J 0.8 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.06 N 0.10 P Q 1.4±0.05 0.1±0.05 R 3° +4° −3° S U Data Sheet U13546EJ1V0DS00 MILLIMETERS 1.6 MAX. 0.6±0.15 S44GB-80-8ES-1 37 µPD78F9046 10. RECOMMENDED SOLDERING CONDITIONS The µPD78F9046 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions µPD78F9046GB-8ES: Soldering Method 44-pin plastic LQFP (10 × 10 mm) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: twice or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: twice or less VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Caution Do not use different soldering methods together (except for partial heating). 38 Data Sheet U13546EJ1V0DS00 — µPD78F9046 APPENDIX A DIFFERENCES BETWEEN µPD78F9046 AND MASK ROM VERSIONS The µPD78F9046 has flash memory in place of the internal ROM of the mask ROM versions (µPD789046). Differences between the µPD78F9046 and mask ROM versions are shown in Table A-1. Table A-1. Differences Between µPD78F9046A and Mask ROM Versions Parameter Internal memory Flash Memory Version Mask ROM Versions µPD78F9046 µPD789046 ROM structure Flash memory ROM capacity 16 Kbytes High-speed RAM capacity 512 bytes Mask ROM VPP pin Available Not available IC pin Not available Available Electrical specifications See the relevant data sheet Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the consumer samples (not engineering samples) of the mask ROM version. Data Sheet U13546EJ1V0DS00 39 µPD78F9046 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for system development using the µPD78F9046. Language Processing Software RA78K0S Notes 1, 2, 3 Assembler package common to 78K/0S Series Notes 1, 2, 3 C compiler package common to 78K/0S Series CC78K0S DF789026 Notes 1, 2, 3 Notes 1, 2, 3 CC78K0S-L Device file for the µPD789046 Subseries C compiler library source file common to 78K/0S Series Flash Memory Writing Tools Flashpro lll Note 4 (FL-PR3 , PG-FP3) FA-44GB-8ES Note 4 Dedicated flash programmer for microcontrollers incorporating flash memory Flash memory writing adapter for 44-pin plastic LQFP (GB-8ES type) Debugging Tools IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging the hardware and software of the application system using the 78K/0S series. Supports the integrated debugger (ID78K0S-NS). Used with an AC adapter, emulation probe, and interface adapter that connects the host machine. IE-70000-MC-PS-B AC adapter Adapter that distributes power supply from an AC100- to 240-V outlet. IE-70000-98-IF-C Interface adapter Adapter when using a PC-9800 series PC (except notebook type) as the host machine of the IE-78K0S-NS (C bus supported). IE-70000-CD-IF-A PC card interface PC card and interface cable when using a notebook type PC as the host machine of the IE78K0S-NS (PCMCIA socket supported). IE-70000-PC-IF-C Interface adapter Adapter when using an IBM PC/AT or compatible as the host machine of the IE-78K0S-NS (ISA bus supported). IE-70000-PCI-IF Interface adapter Adapter when using a PC with PCI bus as the host machine of the IE-78K0S-NS. IE-789026-NS-EM1 Emulation board Board for emulating device-specific peripheral hardware. Used with an in-circuit emulator. Note 4 NP-44GB Note 4 NP-44GB-TQ SM78K0S Notes 1,2 ID78K0S-NS DF789046 40 Notes 1,2 Notes 1,2 TM Board connecting an in-circuit emulator and target system. For 44-pin plastic LQFP (GB-3BS type) and 44-pin plastic LQFP (GB-8ES type). System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for µPD789046 Subseries Data Sheet U13546EJ1V0DS00 µPD78F9046 Real-Time OS MX78K0S Notes 1, 2 OS for 78K/0S Series TM Notes 1. Based on the PC-9800 series (Japanese/English Windows ) 2. Based on IBM PC/AT and compatibles (Japanese/English Windows) TM TM TM TM TM TM 3. Based on the HP9000 series 700 (HP-UX ), SPARCstation (SunOS , Solaris ), and NEWS (NEWS-OSTM) 4. Products manufactured by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. Remark The RA78K0S, CC78K0S, and SM78K0S can be used in combination with the DF789046. Data Sheet U13546EJ1V0DS00 41 µPD78F9046 APPENDIX C RELATED DOCUMENTS Documents Related to Devices Document Name Document No. English Japanese µPD789046 Data Sheet U13380E U13380J µPD78F9046 Data Sheet This manual U13546J µPD789046 Subseries User’s Manual U13600E U13600J 78K/0S Series User’s Manual — Instruction U11047E U11047J 78K/0, 78K/0S Series Application Note — Flash Memory Write U14458E U14458J Documents Related to Development Tools (User's Manuals) Document Name Document No. English RA78K0S Assembler Package Japanese Operation U11622E U11622J Assembly Language U11599E U11599J Structured Assembly Language U11623E U11623J Operation U11816E U11816J Language U11817E U11817J SM78K0S System Simulator Windows Based Reference U11489E U11489J SM78K Series System Simulator External Parts User Open Interface Specifications U10092E U10092J ID78K0S-NS Integrated Debugger Windows Based Reference U12901E U12901J IE-78K0S-NS In-Circuit Emulator U13549E U13549J IE-789046-NS-EM1 Emulation Board To be prepared To be prepared CC78K0S C Compiler Documents Related to Embedded Software (User's Manuals) Document Name Document No. English 78K/0S Series OS MX78K0S Caution Fundamental U12938J The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 42 U12938E Japanese Data Sheet U13546EJ1V0DS00 µPD78F9046 Other Related Documents Document Name Document No. English Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Device C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J — U11416J Guide to Microcomputer-Related Products by Third Party Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U13546EJ1V0DS00 43 µPD78F9046 [MEMO] 44 Data Sheet U13546EJ1V0DS00 µPD78F9046 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet U13546EJ1V0DS00 45 µPD78F9046 EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 46 Data Sheet U13546EJ1V0DS00 µPD78F9046 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U13546EJ1V0DS00 47 µPD78F9046 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • The information in this document is current as of December, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4