ETC W218

W218
FTG for Integrated Core Logic with 133-MHz FSB
Features
CPU, 3V66 Output Skew:............................................175 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU clock at 66/100/133 MHz
• Nine copies of 100-MHz SDRAM clocks
• Seven copies of PCI clock
• Two copies of APIC clock at 33 MHz, synchronous to
CPU clock
• Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock
• Three copies of 3V 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power down control
• SMBus interface for turning off unused clocks
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
Tristate#
FSEL0
FSEL1
CPU
SDRAM
0
0
x
Three-state
Three-state
Key Specifications
0
1
x
Test
Test
1
0
0
66 MHz
100 MHz
1
1
0
100 MHz
100 MHz
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
1
0
1
133 MHz
133 MHz
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
1
1
1
133 MHz
100 MHz
APIC, SDRAM Output Skew: ...................................... 250 ps
Pin Configuration [1]
Block Diagram
VDDQ3
X1
X2
REF0/FSEL1
XTAL
OSC
PLL REF FREQ
VDDQ2
FSEL0:1
VDDA
I2C
Logic
2
CPU0:1
CPU2_ITP
2
APIC0:1
VDDQ3
PLL 1
2
3V66_0:1
3V66_AGP
PCI0_ICH
PCI1:6
Tristate#
7
DCLK
PWR_DWN#
SDRAM0:7
8
VDDA
VDDQ3
USB
PLL2
DOT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
W218
SDATA
SCLK
Divider,
Delay,
and
Phase
Control
Logic
*REF0/FSEL1
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
3V66_AGP
VDDQ3
VDDQ3
PCI0_ICH
PCI1
GND
PCI2
PCI3
GND
PCI4
PCI5
PCI6
VDDQ3
VDDA
GNDA
GND
USB
DOT
VDDQ3
FSEL0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
APIC0
APIC1
VDDQ2
CPU0
VDDQ2
CPU1
CPU2_ITP
GND
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
DCLK
VDDQ3
PWR_DWN#
SCLK
SDATA
Tristate#
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07221 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 21, 2002
W218
Pin Definitions
Pin Name
Pin No.
Pin
Type
REF0/FSEL1
1
I/O
X1
3
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
4
O
Crystal Output: A connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected.
PCI0_ICH,
PCI1:6
12, 13, 15, 16,
18, 19, 20
O
PCI Clock 0 through 6: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via SMBus interface.
3V66_0:1/
3V66_AGP
7, 8, 9
O
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
Pin Description
Reference Clock: 3.3V 14.318-MHz clock output. This pin also serves as a strap
option for CPU frequency selection. See Table 1 for detailed descriptions.
USB
25
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output.
DOT
26
O
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
28, 29
I
Clock Function Selection pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions.
32
I
Power-Down Control: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. This input can be used as the
VTT_PWRGD input to support Intel VRM 8.5 implementation.
CPU2_ITP,
CPU0:1
49,52,50
O
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the
configuration of SEL0:1 and SEL133. Voltage swing set by VDDQ2.
SDRAM0:7,
DCLK
46, 45, 43, 42,
40, 39, 37, 36,
34
O
SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via SMBus interface.
APIC0:1
55, 54
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by VDDQ2.
SDATA
30
I/O
Data pin for SMBus circuitry.
FSEL0,
Tristate#
PWR_DWN#
SCLK
VDDQ3
VDDA
VDDQ2
GND
GNDA
31
I
Clock pin for SMBus circuitry.
2, 10, 11, 21, 27,
33, 38, 44
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
22
P
3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V.
51, 53
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V.
5, 6, 14, 17, 24,
35, 41, 47, 48,
56
G
Ground Connections: Connect all ground pins to the common system ground
plane.
23
G
Ground Connections: Ground for core logic, PLL circuitry.
Document #: 38-07221 Rev. *A
Page 2 of 17
W218
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W218
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W218 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF0/FSEL1is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. If the pin is strapped to a HIGH state
externally, CPU clock outputs will run at 133 MHz. If it is
strapped LOW, CPU clock outputs will be determined by the
status of FSEL input pin. An external 10-kΩ strapping resistor
should be used. Figure 1 shows a suggested method for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
Threestate#, FSEL0 and FSEL1. Specific outputs available at
each pin are detailed in Table 2 below. The SEL0 pin requires
a 220Ω pull-up resistor to 3.3V for the W218 to sense the maximum host bus frequency of the processor and configure itself
accordingly. Also note that FSEL0, Threestate# input levels
should be stable within 500 µs of the later of VDDQ3, VDDQ2,
PWR_DWN# rising edge.
Table 2. CK Whitney Truth Table
CPU
SDRAM
3V66
PCI
48 MHz
REF
Notes
Tristate#
FSEL0
FSEL1
APIC
0
0
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
0
1
X
TCLK/4
TCLK/4
TCLK/6
TCLK/12
TCLK/2
TCLK
TCLK/12
4, 5
1
0
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
1
0
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
0
1
133 MHz
133 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
1
1
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
Notes:
2. Provided for board-level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07221 Rev. *A
Page 3 of 17
W218
How to use PD# input to support VTT_PWRGD
The PD# input can be used to support the VTT_PWRGD signal specified in the Intel VRM 8.5 specification. The
VTT_PWRGD is used to indicated that the frequency select
output pins (BSEL[0:1]) from the CPU are valid and the clock
generator can use them to determine the CPU FSB frequency.
The assertion of PD# input pin during initial power up will delay
the start of the PLL, keep all the multiplexed I/O pins as input
and keep all the output inactive. The functionality of PD# will
allow system designer to use this input to support the
VTT_PWRGD output from the VRM 8.5 module. Please refer
to the Figure 2 for power up sequence details.
3.3V & 2.5V
PD# (connected to
VTT_PWRGD)
PLL & Output
Synchronization
Outputs
Input Latch
(pin 4 & pin21)
1 ms
Figure 2. Power up sequence with PD# (VTT_PWRGD) hold LOW
Document #: 38-07221 Rev. *A
Page 4 of 17
W218
Offsets Among Clock Signal Groups
Figure 3 and Figure 4 represent the phase relationship among
the different groups of clock outputs from W218 when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, re10 ns
0 ns
20 ns
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
30 ns
40 ns
Cycle Repeat
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 3. Group Offset Waveforms (66-MHz CPU/100-MHZ SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (100-MHz CPU/100-MHZ SDRAM Clock)
Document #: 38-07221 Rev. *A
Page 5 of 17
W218
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 6. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
Document #: 38-07221 Rev. *A
Page 6 of 17
W218
Power Down Control
W218 provides one PWRDWN# signal to place the device in
low-power mode. In low-power mode, the PLLs are turned off
and all clock outputs are driven LOW.
0 ns
25 ns
50 ns
75 ns
Center
1
2
VCO Internal
CPU 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
PwrDwn
SDRAM 100-MHz
REF 14.318-MHz
USB 48-MHz
Figure 7. W218 PWRDWN# Timing Diagram[8, 9, 10, 11]
Table 3. W218 Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
All static inputs = VDDQ3 or VSS
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWRDWN# = 0)
10 µA
10 µA
Full Active 66 MHz
FSEL1:0 = 00 (PWRDWN# =1)
70 mA
280 mA
Full Active 100 MHz
FSEL1:0 = 01 (PWRDWN# =1)
100 mA
280 mA
Full Active 133 MHz
FSEL1:0 = 11 (PWRDWN# =1)
TBD
TBD
W218
Condition
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
9. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W218.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07221 Rev. *A
Page 7 of 17
W218
Spread Spectrum Frequency Timing
Generation
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 9. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% of the selected frequency. Figure 9 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 8.
As shown in Figure 8, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the I2C
data stream. Refer to page 10 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Spectrum
Enabled
NonSpread
Spectrum
Figure 8. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
MIN.
Figure 9. Typical Modulation Profile
Document #: 38-07221 Rev. *A
Page 8 of 17
W218
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte N
Ack
Stop
8 bits
1
1
Figure 10. An Example of a Block Write[12]
Serial Data Interface
The W218 features a two-pin, serial data interface that can be
used to configure internal register settings that control particular device functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver address for W218 is 11010010. Figure 10 shows an example of
a block write.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W218 expects a command
code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 4 shows an
example of a possible byte count value.
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W218.
However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 4. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
LSB
0000
0000
Not allowed. Must have at least one byte
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data (byte 0 then byte 1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13]
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13]
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max. byte count supported = 32
Table 5. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused
PCI slots.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0.
duction device testing.
Notes:
12. The acknowledgment bit is returned by the slave/receiver (W218).
13. Data Bytes 3 to 7 are reserved.
Document #: 38-07221 Rev. *A
Page 9 of 17
W218
W218 Serial Configuration Map
2. All unused register bits (reserved and N/A) should be written to a “0” level.
1. The serial bits will be read by the clock driver in the following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in higher than normal operating current.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
4. Only Byte 0, 1 and 2 are defined in W218. Byte 3 to Byte 7
are reserved and must be written to “zero.”
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
Name
Pin Description
Bit 7
-
Reserved
(Active/Inactive)
Bit 6
-
Reserved
(Active/Inactive)
Bit 5
-
Reserved
(Active/Inactive)
Bit 4
-
Reserved
(Active/Inactive)
Bit 3
-
Spread Spectrum (1 = On/0 = Off)
(Disabled/Enabled)
Bit 2
26
DOT
(Active/Inactive)
Bit 1
25
USB
(Active/Inactive)
Bit 0
49
CPU2_ITP
(Active/Inactive)
Byte 1: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
Name
Pin Description
Bit 7
36
SDRAM7
(Active/Inactive)
Bit 6
37
SDRAM6
(Active/Inactive)
Bit 5
39
SDRAM5
(Active/Inactive)
Bit 4
40
SDRAM4
(Active/Inactive)
Bit 3
42
SDRAM3
(Active/Inactive)
Bit 2
43
SDRAM2
(Active/Inactive)
Bit 1
45
SDRAM1
(Active/Inactive)
Bit 0
46
SDRAM0
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable) [14]
Bit
Pin#
Name
Pin Description
Bit 7
9
3V66_AGP
(Active/Inactive)
Bit 6
20
PCI6
(Active/Inactive)
Bit 5
19
PCI5
(Active/Inactive)
Bit 4
18
PCI4
(Active/Inactive)
Bit 3
16
PCI3
(Active/Inactive)
Bit 2
15
PCI2
(Active/Inactive)
Bit 1
13
PCI1
(Active/Inactive)
Bit 0
--
Reserved
Reserved
Note:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07221 Rev. *A
Page 10 of 17
W218
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Pin Description
Bit 7
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 6
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 5
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 4
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 3
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 2
-
Reserved Drive to ’0’
(Active/Inactive)
Reserved Drive to ’0’
(Active/Inactive)
SDRAM 133-MHz Mode Enable
Default is Disabled = ’0’, Enabled = ’1’
(Disabled/Enabled)
Bit 1
Bit 0
-
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Pin Description
Bit 7
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 6
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 5
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 4
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 3
-
Reserved Drive to ’0’
(Active/Inactive)
Bit 2
-
Reserved Drive to ’0’
(Active/Inactive)
Reserved Drive to ’0’
(Active/Inactive)
Reserved Drive to ’0’
(Active/Inactive)
Bit 1
Bit 0
-
Document #: 38-07221 Rev. *A
Page 11 of 17
W218
DC Electrical Characteristics[15]
Absolute Maximum DC Power Supply
Parameter
Description
Min.
Max.
Unit
VDD3
3.3V Core Supply Voltage
–0.5
4.6
V
VDDQ2
2.5V I/O Supply Voltage
–0.5
3.6
V
VDDQ3
3.3V Supply Voltage
–0.5
4.6
V
TS
Storage Temperature
–65
150
°C
Absolute Maximum DC I/O
Min.
Max.
Unit
Vih3
Parameter
3.3V Input High Voltage
Description
–0.5
4.6
V
Vil3
3.3V Input Low Voltage
–0.5
V
ESD prot.
Input ESD Protection
2000
V
DC Operating Requirements
Parameter
Description
Condition
Min.
Max.
Unit
VDD3
3.3V Core Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ3
3.3V I/O Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ2
2.5V I/O Supply Voltage
2.5V±5%
2.375
2.625
V
Vih3
3.3V Input High Voltage
VDD3
2.0
VDD + 0.3
V
Vil3
3.3V Input Low Voltage
VSS – 0.3
0.8
V
Iil
Input Leakage Current[16]
0<Vin<VDD3
–5
+5
µA
Voh2
2.5V Output High Voltage
Ioh=(–1 mA)
2.0
Vol2
2.5V Output Low Voltage
Iol=(1 mA)
Voh3
3.3V Output High Voltage
Ioh=(–1 mA)
Vol3
3.3V Output Low Voltage
Iol=(1 mA)
VDD3 = 3.3V±5%
VDDQ2 = 2.5V±5%
V
0.4
V
VDDQ3 = 3.3V±5%
2.4
V
0.4
V
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
Ioh=(–1 mA)
Vpol3
PCI Bus Output Low Voltage
Iol=(1 mA)
Cin
Input Pin Capacitance
Cxtal
Xtal Pin Capacitance
Cout
Output Pin Capacitance
Lpin
Pin Inductance
2.4
V
0.55
13.5
0
V
5
pF
22.5
pF
6
pF
7
nH
Ambient Temperature
No Airflow
0
70
Ta
Note:
15. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
16. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Document #: 38-07221 Rev. *A
°C
Page 12 of 17
W218
AC Electrical Characteristics[15]
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
AC Electrical Characteristics
66.6-MHz Host
Parameter
Description
100-MHz Host
133-MHz Host
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15.0
15.5
10.0
10.5
7.5
8.0
ns
17
Notes
N/A
ns
20
N/A
ns
TPeriod
Host/CPUCLK Period
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TPeriod
SDRAM CLK Period (100-MHz)
10.0
10.5
10.0
10.5
10.0
10.5
ns
17
THIGH
SDRAM CLK High Time (100-MHz)
3.0
N/A
3.0
N/A
3.0
N/A
ns
20
TLOW
SDRAM CLK Low Time (100-MHz)
2.8
N/A
2.8
N/A
2.8
N/A
ns
TRISE
SDRAM CLK Rise Time (100-MHz)
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TFALL
SDRAM CLK Fall Time (100-MHz)
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TPeriod
SDRAM CLK Period (133-MHz)
7.5
8.0
7.5
8.0
7.5
8.0
ns
17
THIGH
SDRAM CLK High Time (133-MHz)
1.87
N/A
1.87
N/A
1.87
N/A
ns
20
TLOW
SDRAM CLK Low Time (133-MHz)
1.67
N/A
1.67
N/A
1.67
N/A
ns
TRISE
SDRAM CLK Rise Time (133-MHz)
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TFALL
SDRAM CLK Fall Time (133-MHz)
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TPeriod
APIC 33-MHz CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
17
THIGH
APIC 33-MHz CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
20
TLOW
APIC 33-MHz CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
21
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
.04
1.6
ns
21
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
17, 19
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
20
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
21
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
21
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
17, 18
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
20
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
21
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
21
Notes:
17. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
18. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
19. TLOW is measured at 0.4V for all outputs.
20. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable
and operating within specification.
21. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs, and Vol =
0.4V and Voh = 2.4V for 3.3V.
Document #: 38-07221 Rev. *A
Page 13 of 17
W218
AC Electrical Characteristics (continued)
66.6-MHz Host
Parameter
Description
100-MHz Host
133-MHz Host
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from Power-Up
3
ms
3
3
Notes
20
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max.
Cycle-Cycle Jitter
Duty Cycle
Nom VDD
Skew, Jitter
Measure Point
CPU
175 ps
250 ps
45/55
2.5V
1.25V
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
APIC
250 ps
500 ps
45/55
2.5V
1.25V
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
3V66
175 ps
500 ps
45/55
3.3V
1.5V
PCI
500 ps
500 ps
45/55
3.3V
1.5V
REF
N/A
1000 ps
45/55
3.3V
1.5V
Output
Buffer
Test Point
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
2.5V Clocking
Interface
1.25
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
3.3V Clocking
Interface
1.5
0.4
TLOW
TRISE
TFALL
Figure 11. Output Buffer
Ordering Information
Ordering Code
W218
Document #: 38-07221 Rev. *A
Package Name
H
Package Type
56-pin SSOP (300 mils)
Page 14 of 17
W218
Layout Diagram
+2.5V Supply
+3.3V Supply
FB
FB
VDDQ2
VDDQ3
C4
0.005 µF
G
G
G C6
1
2
3
4
5
6
7
8
9
G
56
55
G
54
V 53
52
V
51
G
50
49
G 48
47
46
G 45
V 44
G
43
42
G
41
40
G 39
V 38
G 37
36
35
34
V 33
G 32
31
30
G
29
10 µF
0.005 µF
G
G
C2
µ
G
V
G
G
G
V
G
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
G
W218
C5 G
G
10
G
10 Ω
C1
C3
G
G
VDDQ3
10 µF
G
G
G
V
V
Core
G
PLL2
G
G
G
G
G
G
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
Ceramic Caps C1 & C3 = 10–22 µF C2 & C4 = 0.005 µF C5 = 47 µF C6 = 0.1 µF
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07221 Rev. *A
Page 15 of 17
W218
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07221 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W218
Document Title: W218 FTG for Integrated Core Logic with 133-MHz FSB
Document Number: 38-07221
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110486
10/21/01
SZV
Change from Spec number: 38-00885 to 38-07221
*A
122838
12/21/02
RBI
Add Power up Requirements to Electrical Characteristics Information
Document #: 38-07221 Rev. *A
Page 17 of 17