WED3DG648V-D1 64MB- 8Mx64 SDRAM, UNBUFFERED FEATURES DESCRIPTION Burst Mode Operation Serial Presence Detect with EEPROM The WED3DG648V is a 8Mx64 synchronous DRAM module which consists of eight 4Mx16 SDRAM components in TSOP- 11 package, and one 2K EEPROM in an 8- pin TSSOP package for Serial Presence Detect which are mounted on a 144 Pin SO-DIMM multilayer FR4 Substrate. Fully synchronous: All signals are registered on the positive edge of the system clock * This product is subject to change without notice. Auto and Self Refresh capability LVTTL compatible inputs and outputs Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3 volt + 0.3v Power Supply 144 Pin SO-DIMM JEDEC PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 Sept. 2002 Rev. 0 ECO #15457 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin 51 53 55 57 59 Front DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC VOLTAGE KEY 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 CLK0 VDD RAS WE CS0 CS1 DNU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 CKE0 VDD CAS CKE1 *A12 *A13 CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 PIN NAMES Pin 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Back DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD 1 Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD A0 – A11 BA0-1 DQ0-63 CLK0,CLK1 CKE0,CKE1 CS0,CS1 RAS CAS WE DQM0-7 VDD VSS SDA SCL DNU NC Address input (Multiplexed) Select Bank Data Input/Output Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial data I/O Serial clock Do not use No Connect * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED3DG648V-D1 FUNCTIONAL BLOCK DIAGRAM S1 WE S0 WE DQMB0 I/O 4 I/O 5 I/O 6 I/O 7 WE WE I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 I/O 5 I/O 6 I/O 7 D0 WE DQMB4 I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D4 DQMB1 I/O 4 I/O 5 I/O 6 I/O 7 D2 D6 DQMB5 I/O 8 I/O 8 I/O 8 I/O 8 I/O 9 I/O 9 I/O 9 I/O 9 I/O 10 I/O 11 I/O 10 I/O 11 I/O 10 I/O 11 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 DQMB2 WE I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQMB6 WE I/O 5 I/O 6 I/O 7 WE I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 4 D1 WE I/O 0 I/O 1 I/O 2 I/O 3 I/O 0 I/O 1 I/O 2 I/O 3 D5 DQMB3 I/O 4 I/O 5 I/O 6 I/O 7 D3 D7 DQMB7 I/O 8 I/O 8 I/O 8 I/O 8 I/O 9 I/O 9 I/O 9 I/O 9 I/O 10 I/O 11 I/O 10 I/O 11 I/O 10 I/O 11 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 I/O 12 I/O 13 I/O 14 I/O 15 *CLOCK WIRING RAS CAS CKE0 CKE1 RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 CKE: SDRAM D0-D3 CKE: SDRAM D4-D7 CLOCK INPUT SDRAMS *CLK0 4 SDRAMS *CLK1 4 SDRAMS * Wire per clock Loading Table/Wiring Diagrams BA0-BA1 A0-A11 BA0-BA1: SDRAM D0-D8 A0-A11: SDRAM D0-D8 SERIAL PD SDA SCL VDD D0-D7 VSS D0-D7 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com A0 2 A1 A2 Sept. 2002 Rev. 0 ECO #15457 WED3DG648V-D1 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, Vout VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50 Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C) Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 — -10 Typ 3.3 3.0 — — — — Max 3.6 VDDQ+0.3 0.8 — 0.4 10 Unit V V V V V µA Note 1 2 IOH= -2mA IOL= -2mA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV) Parameter Input Capacitance (A0-A12) Input Capacitance (RAS,CAS,WE) Input Capacitance (CKE0,CKE1) Input Capacitance (CLK0,CLK1) Input Capacitance (CS0,CS1) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Sept. 2002 Rev. 0 ECO #15457 3 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 Cout Min - Max 25 25 25 21 25 12 25 12 Unit pF pF pF pF pF pF pF pF White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED3DG648V-D1 OPERATING CURRENT CHARACTERISTICS (VCC = 3.3V, TA = 0°C to +70°C) Parameter Operating Current (One bank active) Symbol ICC1 Precharge Standby Current in Power Down Mode ICC2P ICC2PS Icc2N Precharge Standby Current in Non-Power Down Mode Active standby current in power-down mode Active standby current in non power-down mode Icc2NS ICC3P ICC3PS ICC3N ICC3NS Operating current (Burst mode) ICC4 Refresh current Self refresh current ICC5 ICC6 Conditions Burst Length = 1 tRC ≥ tRC(min) IOL = 0mA CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns Input signals are charged one time during 20 CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞ Input signals are stable CKE ≥ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tcc = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞ input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC ≥ tRC(min) CKE ≤ 0.2V 1 Bank Version 133 100Units 460 400 mA 5 5 Note 1 mA 60 mA 30 15 15 mA 110 mA 80 560 mA 440 mA 560 500 10 1 mA mA 2 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ) White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 Sept. 2002 Rev. 0 ECO #15457 WED3DG648V-D1 Ordering Information WED3DG648V10D1 WED3DG648V7D1 WED3DG648V75D1 Speed 100MHz 133MHz 133MHz Cas Latency CL=2 CL=2 CL=3 PACKAGE DIMENSIONS .170 MAX. ALL DIMENSIONS ARE IN INCHES Sept. 2002 Rev. 0 ECO #15457 5 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED3DG648V-D1 REV. DATE REQUESTED BY DETAILS A 11-15-01 PAUL MARIEN CREATED B 6-25-02 PAUL MARIEN -CORRECT PART NUMBER ON THE ORDERING INFORMATION TABLE 0 9-6-02 PAUL MARIEN -CHANGE FROM ADVANCED TO FINAL White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 6 Sept. 2002 Rev. 0 ECO #15457