ETC CLC432AJP

CLC431/432
Dual Wideband Monolithic Op Amp with Disable
General Description
Features
The CLC431 and CLC432 current-feedback amplifiers
provide wide bandwidths and high slew rates for applications
where board density and power are key considerations.
These amplifiers provide DC-coupled small signal
bandwidths exceeding 92MHz while consuming only 7mA
per channel. Operating from ± 15V supplies, the
CLC431/432’s enhanced slew rate circuitry delivers
large-signal bandwidths without out voltage swings up to
28Vpp. A wide range of bandwidth insensitive gains are
made possible by virtue of the CLC431 and CLC432’s
current-feedback topology.
The large common-mode input range and fast settling time
(70ns to 0.05%) make these amplifiers well suited for CCD &
data telecommunication applications. The disable of the
CLC431 can accommodate ECL or TTL logic levels or a wide
range of user definable inputs. With its fast enable/disable
time (0.2µs/1µs) and high channel isolation of 70dB at
10MHz, the CLC431 can easily be configured as a 2:1 MUX.
Many high performance video applications requiring signal
gain and/or switching will be satisfied with the CLC431/432
due to their very low differential gain and phase errors (less
than 0.1% and 0.1˚; AV = +2V/V at 4.43MHz into 150Ω load).
Quick 8ns rise and fall times on 10V pulses allow the
CLC431/432 to drive either twisted pair or coaxial
transmission lines over long distances.
The CLC431/432’s combination of low input voltage noise,
wide common-mode input voltage range and large output
voltage swings make them especially well suited for wide
dynamic range signal processing applications
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-94725
n
n
n
n
n
Wide bandwidth: 92MHz(AV =+1), 62MHz(AV =+2)
Fast slew rate: 2000V/µs
Fast disable: 1µs to high-Z output
High channel isolation: 70dB at 10MHz
Single or dual supplies: ± 5V to ± 16.5V
Applications
n
n
n
n
n
Video signal multiplexing
Twisted-pair differential driver
CCD buffer & level shifting
Discrete gain-select amplifier
Transimpedance amplifier
CLC431/CLC432 Channel Matching
DS012712-1
*Space level versions also available.
*For more information, visit http://www.national.com/mil
Connection Diagrams
DS012712-5
Pinout
CLC432 DIP & SOIC
© 2001 National Semiconductor Corporation
DS012712
www.national.com
CLC431/432 Dual Wideband Monolithic Op Amp with Disable
February 2001
CLC431/432
Connection Diagrams
(Continued)
DS012712-4
Pinout
CLC431 DIP & SOIC
Typical Application
DS012712-3
CLC431 Gain-Select Amplifier
DS012712-2
Discrete Gain-Select Amplifier
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2
Package
Temperature Range
Industrial
Part Number
Package
Marking
NSC
Drawing
14-Pin Plastic DIP
−40˚C to +85˚C
CLC431AJP
CLC431AJP
N14A
14-Pin Plastic SOIC
−40˚C to +85˚C
CLC431AJE
CLC431AJE
M14A,B
8-Pin Plastic DIP
−40˚C to +85˚C
CLC432AJP
CLC432AJP
N08E
8-Pin Plastic SOIC
−40˚C to +85˚C
CLC432AJE
CLC432AJE
M08A
3
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CLC431/432
Ordering Information
CLC431/432
Absolute Maximum Ratings (Note 1)
Lead Temperature (Soldering 10 sec)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings
Supply Voltage
Short Circuit Current
Common-Mode Input Voltage
Differential Input voltage
Maximum Junction Temperature
Storage Temperature Range
Thermal Resistance
Package
14-Pin MDIP
14-Pin SOIC
8-Pin MDIP
8-Pin SOIC
± 16.5V
100mA
± VCC
± 10V
150˚C
−65˚C to +150˚C
+300˚C
(θJC)
55˚C/W
35˚C/W
55˚C/W
40˚C/W
(θJA)
100˚C/W
105˚C/W
110˚C/W
115˚C/W
Electrical Characteristics
VCC = ± 15V; AV = +2; Rf = Rg = 750Ω; RL = 100Ω; unless noted
(Note 3)
Parameters
Ambient Temperature
Conditions
Typ
Max/Min Ratings (Note 2)
Units
CLC431 & CLC432
+25
+25
0 to +70
−40 to
+85
˚C
VOUT < 4.0VPP
62
42
37
36
MHz
Frequency Domain Response
-3dB Bandwidth
< 4.0VPP, VCC
(Note 4)
Gain Flatness
VOUT
= ± 5V
62
VOUT < 10VPP
28
21
20
20
MHz
dB
MHz
VOUT < 4.0VPP
Peaking
DC to 100MHz
0.05
0.5
0.7
0.7
Rolloff
DC to 20MHz
0.0
0.8
0.8
0.8
dB
Linear Phase Deviation
DC to 30MHz
0.3
1.8
2.0
2.1
deg
Differential Gain
RL = 150Ω,4.43MHz
0.12
0.18
0.2
0.2
%
Differential Phase
RL = 150Ω, 4.43MHz
0.12
0.18
0.23
0.25
deg
Time Domain Response
(Note 4)
(Note 4)
Rise and Fall Time
10V Step
8
12
13
13
ns
Overshoot
2V Step
5
10
12
12
%
Settling Time
2V Step to 0.05%
70
100
110
110
ns
Slew Rate
VOUT = ± 10V
2000
1500
1450
1400
V/ms
2nd Harmonic Distortion
2VPP, 1MHz
−65
dBc
3rd Harmonic Distortion
2VPP, 1MHz
−75
dBc
Voltage
> 1MHz
3.3
4.2
4.4
4.5
nV/
Current, Inverting
> 1MHz
13
16
17
18
pA/
Current, Non-Inverting
> 1MHz
2.0
2.5
2.6
2.8
pA/
Distortion And Noise Response
(Note 8)
(Note 8)
Equivalent Input Noise
Static, DC Performance
(Note 9)
Input Offset Voltage
3
6
7
7
mV
Average Drift
20
-
50
50
µV/˚C
(Note 9)
Input Bias Current,
Non-Inverting
2
8
10
16
µA
Average Drift
25
-
100
150
nA/˚C
(Note 9)
Input Bias Current, Inverting
2
6
6
8
µA
8
-
25
40
nA/˚C
59
59
59
dB
Average Drift
(Note 9)
Power Supply Rejection Ratio
DC
64
Common-Mode Rejection Ratio
DC
RL = ∞, Per Channel
63
58
57
56
dB
7.1
7.9
8.5
9.6
mA
Supply Current
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4
(Continued)
VCC = ± 15V; AV = +2; Rf = Rg = 750Ω; RL = 100Ω; unless noted
(Note 3)
Parameters
Ambient Temperature
Typ
Max/Min Ratings (Note 2)
CLC431 & CLC432
Conditions
+25
+25
0 to +70
−40 to
+85
Units
˚C
RL = ∞, Per Channel
0.8
1.2
1.3
1.45
mA
± 12.2
± 12.0
± 11.8
± 11.6
V
MΩ
Static, DC Performance
(Note 9)
CLC431
Disabled
Miscellaneous Performance
Input Voltage Range
Common Mode
Input Resistance
Non-Inverting
24
16
10
6
Input Capacitance
Non-Inverting
0.5
1
1
1
pF
± 60
± 14.0
± 6.0
± 38
± 13.6
± 3.7
± 35
± 13.4
± 3.7
± 30
± 13.2
± 2.9
mA
Turn On
0.1
0.15
0.155
0.165
µs
Turn Off
0.7
1.0
1.2
1.2
µs
> 2.0
< 0.8
> 2.0
< 0.8
> 2.0
< 0.8
> 2.0
< 0.8
V
150
180
190
205
µA
0.3
0.4
0.4
0.4
V
Output Current
Output Voltage Range
RL ≥ 5kΩ
RL = 100Ω
V
V
Switching Performance (CLC431)
Switching Time
(Note 5)
DIS Logic Levels
Single-Ended Mode
High Input Voltage (VIH)
Low Input Voltage (VIL)
Maximum Current Input
(Note 6)
DIS-DIS
VIH > DIS > VIL
V
Differential Mode
Minimum Differential Voltage
Isolation
(Note 7)
Crosstalk, Input Referred
10MHz
70
64
64
64
dB
Off Isolation
10MHz
64
60
60
60
dB
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Tested and guaranteed with Rf = 866Ω. CLC432 tested and guaranteed with Rf = 750Ω
Note 4: Spec is guaranteed for RL ≥ 500Ω
Note 5: VRTTL = 0, See text for single-ended mode of operation.
Note 6: VRTTL = NC, See text for differential mode operation.
Note 7: Spec is guaranteed for AJE & AJP yield 7dB lower
Note 8: Spec is tested with 2VPP, 10MHz and RL = 100Ω
Note 9: J-level: spec is 100% tested at +25˚C
Typical Performance Characteristics
(TA = +25˚C, AV = +2, VCC = ± 15V, unless specified)
Non-Inverting Frequency Response
Inverting Frequency Response
DS012712-6
DS012712-7
5
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CLC431/432
Electrical Characteristics
CLC431/432
Typical Performance Characteristics
(TA = +25˚C, AV = +2, VCC = ± 15V, unless
specified) (Continued)
Frequency Response vs. Load Resistance
Output Current
DS012712-8
Gain Flatness & Linear Phase Deviation
DS012712-9
Differential Gain and Phase at 3.58MHz
DS012712-10
DS012712-11
Pulse Response
Short-Term Settling Time
DS012712-12
DS012712-13
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CLC431/432
Typical Performance Characteristics
(TA = +25˚C, AV = +2, VCC = ± 15V, unless
specified) (Continued)
Long-Term Settling Time
Settling Time vs. Capacitive Load
DS012712-15
DS012712-14
Turn-Off/ On Time (CLC431)
Open-Loop Transimpedance
DS012712-16
DS012712-17
CMRR, PSRR and Closed-Loop RO
Off-Isolation during Disable (CLC431)
DS012712-19
DS012712-18
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CLC431/432
Typical Performance Characteristics
(TA = +25˚C, AV = +2, VCC = ± 15V, unless
specified) (Continued)
Typical DC Errors vs. Temperature
Equivalent Input Noise
DS012712-21
DS012712-20
2nd and 3rd Harmonic distortion
2-Tone, 3rd-Order Intermod. Intercept
DS012712-22
Recommended Rfvs. Gain (CLC432)
DS012712-23
Recommended Rfvs. Gain (CLC431)
DS012712-24
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DS012712-25
8
CLC431/432
Typical Performance Characteristics
(TA = +25˚C, AV = +2, VCC = ± 15V, unless
specified) (Continued)
Recommended Rfvs. VCC (AV = +2)
DS012712-26
Application Division
Introduction
The CLC431 and the CLC432 are dual wideband
current-feedback op amps that operate from single (+10V to
+33V) or dual ( ± 5V to ± 16.5) power supplies. The CLC431
is equipped with a disable feature and is offered in 14-dip
DIP and SOIC packages. The CLC432 is packaged in a
standard 8-pin dual pinout and is offered in an 8-pin DIP and
SOIC. Evaluation boards are available for each version of
both devices. The evaluation boards can assist in the device
and/or application evaluation and were used to generate the
typical device performance plots on the preceding pages.
Each of the CLC431/CLC432’s dual channels provide
closely matched DC & AC electrical performance
characteristics making them ideal choices for wideband
signal processing. The CLC431, with its disable features,
can easily be configured as a 2:1 mux or several can be
used to form a 10:1 mux without performance degradation.
The two closely-matched channels of the CLC432 can be
combined to form composite circuits for such applications as
filter blocks, integrators, transimpedance amplifiers and
differential line drives and receivers.
Feedback Resistor Selection
The loop gain and frequency response for a
current-feedback operational amplifier is determined largely
by the feedback resistor (Rf). Package parasitic also
influence ac response. Since the package parasitics of the
CLC431 and the CLC4332 are different, the optimum
frequency and phase response are obtained with different
values of feedback resistor (for AV = +2; CLC431: Rf = 866Ω,
CLC432: Rf = 750Ω). The Electrical Characteristics and
Typical Performance plot are valid for both devices under the
specified conditions. Generally, lowering Rf from its
recommended value will peak the frequency response and
extended the bandwidth while increasing its value will roll off
the response. Reducing the value of Rf too far below its
recommended value will cause overshoot, ringing and
eventually oscillation. For more information see Application
Note OA-20 and OA-13.
In order to minimize the devices’ frequency and phase
response for gains other than +2V/V it is recommended to
adjust the value of the feedback resistor. The two plots found
in the Typical Performance section entitled “Recommended
Rf vs. Gain” provide the means of selecting the
feedback-resistor value that optimizes frequency and phase
response over the CLC431/CLC432’s gain range. Both pots
show the value of Rf approaching a nonzero minimum at
high non-inverting gains, which is characteristic of
current-feedback op amps and yields best results. The linear
portion of the two Rf vs. Inverting-gain curves results from
the limitation placed on Rg (i.e. Rg ≥ 50Ω) in order to
maintain an adequate input impedance for the inverting
configuration. It should be noted that for stable operation a
non-inverting gain of +1 requires an Rf equal to 1kΩ for both
the CLC431 and the CLC4332.
CLC431 Disable Feature
The CLC431 disable feature can be operated either
single-endedly or differentially thereby accommodating a
wide range of logic families. There are three pins associated
with the disable feature of each of the CLC431’s two
amplifiers: DIS,DIS and VRTTL (please see pinout on front
page). Also note that both amplifiers are guaranteed to be
enabled if all three of these pins are unconnected.
Figure 1 illustrates the single-ended mode of the CLC431’s
disable feature for logic families such as TTL and CMOS. In
order to operate properly, VRTTL must be grounded, thereby
biasing DIS to approximately +1.4V through the two internal
series diodes. For single-ended operation, DIS should be left
floating. Applying a TTL or CMOS logic “high” (i.e. > 2.0Volts)
to DIS will switch the tail current of the differential pair to Q1
and “shut down” Q2 which results in the disabling of that
channel of the CLC431. Alternatively, applying a logic “low”
(i.e. < 0.8Volts) to DIS will switch the tail current from Q1 to
Q2 effectively enabling that channel. If DIS is left floating
under single-ended operation, then the associated amplifier
is guaranteed to be disabled.
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CLC431/432
Application Division
(Continued)
Vnon-inv
+
Vinv
+VCC
Vout
+VCC
+VCC
100kΩ
TTL
CMOS
100kΩ
DIS
DIS
Q2
Q1
VRTTL
½CLC431
DS012712-27
FIGURE 1.
The disable feature of the CLC431 is such that DIS and DIS
have common-mode input voltage ranges of (+VCC) to
(−VCC+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect the
DIS input from excessive input voltages that could otherwise
cause damage to the device. This condition occurs when
enough source current flows into the node so as to allow DIS
to rise to VCC. This clamp is activated once DIS exceeds DIS
by 1.5Volts and guarantees that VDIS(ground referenced)
does not exceed 4.7Volts.
Vnon-inv
+
Vinv
+VCC
Vout
+VCC
+VCC
100kΩ
TTL
CMOS
100kΩ
DIS
DIS
Q1
Q2
VRTTL
½CLC431
DS012712-27
FIGURE 2.
Figure 2 illustrates the differential mode of the CLC431’s
disable feature for ECL-type logic. In order for this mode to
operate properly, VRTTL must be left floating while DIS and
DIS are to be connected directly to the ECL gate as
illustrated. Applying a differential logic “high” (DIS - DIS ≥
0.4Volts) switches the tail current of the differential pair from
Q2 to Q1 and results in the disabling of that CLC431
channel. Alternatively, applying a differential logic “low” (DIS
- DIS ≤ −0.4Volts) switches the tail current of the differential
pair from Q1 to Q2 and results in the enabling of that same
channel. The internal clamp, mentioned above, also protects
against excessive differential voltages up to 30 Volts while
limiting input currents to < 3mA.
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DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot be
cancelled and each contributes to the total DC offset voltage
at the output by the following equation:

Voffset = ±  Ibn ∗R s



R 
 1 + f  + Vio
 R 

g


R 
 1 + f  + Ibi ∗R f 
 R 


g

(1)
The input resistor Rs is that resistance seen when looking
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance seen
10
Figure 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75Ω. Each of the two
CLC431’s amplifiers is configured with a non-inverting gain
of +2V/V using 634Ω feedback (Rf) and gain-setting (Rg)
resistors . The feedback resistor value is lower than that
recommended in order to compensate for the reduction of
loop-gain that results from the inclusion of the 50Ω resistor
(Rj) in the feedback loop. The 50Ω resistor serves to insolate
the output of the active channel from the impedance of
inactive channel yet does not affect the low output
impedance channel. Notice that for proper operation VRTTL
1(pin 13) is grounded and VRTTL2 (pin 9) is unconnected.
The pins associated with the disable feature are to be
connected as follows: DIS1 and DIS2 (pins 3 & 10) are
connected together as well as DIS2 and DIS1 (pins 5 & 12).
Channel 1 is selected with the application of a logic “low” to
SELECT while a logic “high” selects Channel 2.
(Continued)
by the input resistor Rg must be included in the output offset
calculation as a part of the non-inverting gain equation.
Application note OA-7 gives several circuits for DC offset
correction.
Layout Considerations
It is recommended that the decoupling capacitors (0.1µF
ceramic and 6.8µF electrolytic) should be placed as close as
possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention to
circuit board layout is also necessary for best performance.
Of particular importance is the control of parasitic
capacitances (to ground) at the output and inverting input
pins. See CLC431/CLC432 Evaluation Board literature for
more information.
Applications Circuit
2:1 Video Mux (CLC431)
Rg
634Ω
Rf
634Ω
75Ω
½CLC431
Channel 1
3
12
Ri
13
50Ω
Rs
SELECT
NC
10
Channel 2
75Ω
5
½CLC431
Vout
75Ω
Ri
RL
75Ω
9
50Ω
634Ω
Optional
Rf
Rg
1kΩ
634Ω
-15V
DS012712-30
FIGURE 3.
The optional 1kΩ pull-down resistor connected from the
output of the 2:1 mux to the negative power supply (−VCC)
results in improved differential gain and phase performance
(0.02% and 0.01˚) at PAL video levels.
Switched Gain Amplifier (CLC431)
As seen from the front page, the CLC431 can also be
configured as a switched-gain amplifier that is similar to the
2:1 mux. Configuring each of the two CLC431’s amplifiers
with different non-inverting gains and tying the two inputs
together (eliminating one of the input-terminating resistors)
allows the CLC431 to switch an input signal between two
different gains.
Inactive Channel Impedances (CLC431)
The impedance that is seen when looking into the output of
a disabled CLC431 is typically represented as 1MΩ\16pF.
The inverting input impedance becomes very high,
essentially open. Therefore, the impedance presented by a
disabled channel is (Rf+ Rg)\ (Rj + (1MΩ\16pF)) as
illustrated in Figure 4. Its should also be noted that any trace
capacitance that is associated with the common output
connection will add in parallel to that presented by the
CLC431’s inactive channel.
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CLC431/432
Application Division
CLC431/432
Application Division
(Continued)
DS012712-31
FIGURE 4.
Twisted-Pair Driver
Twisted-pair cables are used in many applications such as
telephony, video and data communications. The CLC432’s
two matched channels make it well suited for such
applications and is illustrated in Figure 5
DS012712-32
FIGURE 5.
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12
Notice that one of the CLC432’s channels buffers the CCD
output while the other channel is configured with both an
inverting DC gain and an AC gain in order to achieve the
overall transfer function shown in Figure 6
(Continued)
CCD Amplifier
The CLC432 can easily be configured as 10MSPS CCD
amplifier with DC level shifting as illustrated in Figure 6.
DS012712-33
FIGURE 6.
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CLC431/432
Application Division
CLC431/432
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
8-Pin MDIP
NS Package Number N08E
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14
CLC431/432
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Pin SOIC
NS Package Number M14A
14-Pin SOIC
NS Package Number M14B
15
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CLC431/432 Dual Wideband Monolithic Op Amp with Disable
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Pin MDIP
NS Package Number N14A
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