CLC430 General Purpose 100MHz Op Amp with Disable General Description The CLC430 is a low cost, wideband monolithic amplifier for general purpose applications. The CLC430 utilizes National’s patented current feedback circuit topology to provide an op amp with a slew rate of 2000V/µs, 100MHz unity-gain bandwidth and fast output disable function. Like all current feedback op amps, the CLC430 allows the frequency response to be optimized (or adjusted) by the selection of the feedback resistor. For demanding video applications, the 0.1dB bandwidth to 20MHz and differential gain/phase of 0.03%/0.05˚ make the CLC430 the preferred component for broadcast quality NTSC and PAL video systems. The large voltage swing (28VPP) , continuous output current (85mA) and slew rate (2000V/µs) provide high-fidelity signal conditioning for applications such as CCDs, transmission lines and low impedance circuits. Even driving loads of 100Ω, the CLC430 provides very low 2nd and 3rd harmonic distortion at 1MHz (−76/−82dBc). Video distribution, multimedia and general purpose applications will benefit from the CLC430’s wide bandwidth and disable feature. Power is reduced and the output becomes a high impedance when disabled. The wide gain range of the CLC430 makes this general purpose op amp an improved solution for circuits such as active filters, differential-to-single-ended drivers, DAC transimpedance amplifiers and MOSFET drivers. n n n n n 0.03%/0.05˚ differential gain/phase ± 5V, ± 15V or single supplies 100ns disable to high impedance output Wide gain range Low cost Applications n n n n n Video distribution CCD clock driver Multimedia systems DAC output buffers Imaging systems Unity-Gain Frequency Response Features n 0.1dB gain flatness to 20MHz (AV = +2) n 100MHz bandwidth (AV = +1) n 2000V/µs slew rate DS012711-1 Connection Diagram DS012711-4 Pinout DIP & SOIC © 2001 National Semiconductor Corporation DS012711 www.national.com CLC430 General Purpose 100MHz Op Amp with Disable January 2001 CLC430 Typical Application DS012711-3 DS012711-2 CCD Clock Driver Ordering Information Package Temperature Range Industrial Part Number Packaging Marking 8-pin plastic DIP −40˚C to +85˚C CLC430AJP CLC430AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC430AJE CLC430AJE M08A www.national.com 2 NSC Drawing Lead Temperature (soldering 10 sec) ESD (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Ratings ± 16.5V (see note 4) ± VCC +150˚C −65˚C to +150˚C Supply Voltage Short Circuit Current Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range +300˚C 4000V Thermal Resistance Package MDIP SOIC θJA 115˚C/W 135˚C/W θJC 60˚C/W 55˚C/W Electrical Characteristics VCC = ± 15 V, AV = +2V/V, Rf = 604Ω, RL = 100Ω; unless specified Symbol Parameter Ambient Temperature Conditions VCC CLC430AJ Typ +25˚C Min/Max Ratings (Note 2) Units +25˚C 0 to 70˚c −40 to 85˚C 75 50 45 42 55 35 MHz 20 7 MHz Frequency Domain Response Unity-Gain Bandwidth VOUT < 1.0VPP Small-Signal Bandwidth VOUT < 1.0VPP ± 15 ± 15 ±5 ± 15 ±5 VOUT < 1.0VPP 0.1dB Bandwidth VOUT < 1.0VPP VOUT < 1.0VPP Large-Signal Bandwidth VOUT Gain Flatness VOUT < 10VPP < 1.0VPP 100 MHz 16 MHz MHz 30 22 20 19 MHz Peaking DC to 10MHz 0.0 0.1 0.2 0.2 dB Rolloff DC to 20MHz 0.1 0.7 1.0 1.2 dB Linear Phase Deviation DC to 20MHz Differential Gain 4.43 MHz, RL = 150Ω ± 15 ±5 ± 15 ±5 4.43 MHz, RL = 150Ω Differential Phase 4.43 MHz, RL = 150Ω 4.43 MHz, RL = 150Ω 0.5 1.8 2.0 2.1 deg 0.03 0.05 0.06 0.06 % 0.03 0.05 0.05 0.09 0.09 0.19 % 0.12 0.13 deg deg Time Domain Response Rise and Fall Time 2V Step 5 7 7 7 ns 10V Step 10 14 14 14 ns Settling Time to 0.05% 2V Step 35 50 55 55 ns Overshoot 2V Step 5 15 15 15 % Slew Rate 20V Step 2000 1500 1450 1450 V/µs 2nd Harmonic Distortion 1VPP, 1MHz, RL = 500Ω −89 3rd Harmonic Distortion 1VPP, 1MHz, RL = 500Ω −92 Input Voltage Noise > 1MHz 3.0 3.5 3.7 3.8 nV/ Non-Inverting Input Current Noise > 1MHz 3.2 6.0 6.3 6.8 pA/ Inverting Input Current Noise > 1MHz 15 18 20 21 pA/ 1.0 7.5 9.0 10.0 mV 25 - 50 50 µV/˚C ± 15, ±5 3 14 16 20 µA - 10 - 100 100 nA/˚C Distortion And Noise Response dBc dBc DC Performance ± 15 Input Offset Voltage (Note 3) Average Drift Input Bias Current (Note 3) Non-Inverting Average Drift 3 www.national.com CLC430 Absolute Maximum Ratings (Note 1) CLC430 Electrical Characteristics (Continued) VCC = ± 15 V, AV = +2V/V, Rf = 604Ω, RL = 100Ω; unless specified Symbol Parameter Conditions VCC Typ ± 15, ±5 3 Min/Max Ratings (Note 2) Units DC Performance Input Bias Current (Note 3) Inverting average drift - 14 15 17 µA 10 - 60 90 nA/˚C Power-Supply Rejection Ratio DC 62 56 54 53 dB Common-Mode Rejection Ratio DC 62 54 53 52 dB Supply Current (Note 3) RL = ∞ 11, 8.5 12 13 14.5 mA Disabled (Note 3) RL = ∞ 1.5 2.0 2.2 2.4 mA 200 300 320 340 ns ± 15, ±5 ± 15, ±5 Switching Performance Turn On Time Turn Off Time (Note 5) 100 200 200 200 ns Off Isolation 10MHz 59 56 56 56 dB High Input Voltage VIH 11.8 12.5 12.7 V V Low Input Voltage VlL ± 15 ±5 ± 15 ±5 1.8 2.5 2.7 10.8 10.5 10.0 V 0.8 0.6 0.1 V Non-Inverting Input Resistance 8.0 3.0 2.5 1.7 MΩ Non-Inverting Input Capacitance 0.5 1.0 1.0 1.0 pF ± 12.5 ± 2.5 ± 14 ± 4.0 ± 85 ± 12.3 ± 2.3 ± 13.7 ± 3.9 ± 60 ± 12.1 ± 2.2 ± 13.7 ± 3.8 ± 50 ± 11.8 ± 1.9 ± 13.6 ± 3.7 ± 45 V Miscellaneous Performance Input Voltage Range ±5 ±5 ± 15 ±5 Common Mode Common Mode Output Voltage Range RL = ∞ RL = ∞ Output Current V V V mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 125mA. Note 5: To < 50dB attenuation @10MHz. www.national.com 4 (VCC = ± 15V, AV = +2V/V, Rf = 640Ω, RL = 100Ω; Unless Specified) Non-Inverting Frequency Response Inverting Frequency Response DS012711-6 Frequency Response vs. Load DS012711-7 Open-Loop Transimpedance Gain, Z(s) DS012711-8 −3dB Bandwidth vs. VCC DS012711-9 Gain Flatness and Linear Phase DS012711-11 DS012711-10 5 www.national.com CLC430 Typical Performance Characteristics CLC430 Typical Performance Characteristics (VCC = ± 15V, AV = +2V/V, Rf = 640Ω, RL = 100Ω; Unless Specified)) (Continued) Maximum Output Voltage vs. VCC Output Impedance, Disable Mode DS012711-12 Recommended Rf vs. Gain DS012711-13 Equivalent Input Noise DS012711-14 Large Signal Pulse Response DS012711-15 Histogram of Input Offset Voltage DS012711-16 www.national.com DS012711-17 6 (VCC = ± 15V, AV = +2V/V, Rf = 640Ω, RL = 100Ω; Unless Specified)) (Continued) PSRR, CMRR and Closed Loop RO Small Signal Pulse Response DS012711-19 DS012711-18 Differential Gain and Phase (3.58MHz) Short Term Settling Time DS012711-21 DS012711-20 Long Term Settling Time Settling Time vs. Capacitive Load DS012711-23 DS012711-22 7 www.national.com CLC430 Typical Performance Characteristics CLC430 Typical Performance Characteristics (VCC = ± 15V, AV = +2V/V, Rf = 640Ω, RL = 100Ω; Unless Specified)) (Continued) Output Voltage Swing vs. Load Resistance Typical IBI, IBN, VOS vs. Temperature DS012711-24 DS012711-25 Power Derating Curves 2-Tone, 3rd Order Intermodulation Intercept DS012711-26 Harmonic Distortion vs. Frequency DS012711-27 3rd Harmonic Distortion vs. POUT DS012711-29 DS012711-28 www.national.com 8 (VCC = ± 15V, AV = +2V/V, Rf = 640Ω, RL = 100Ω; Unless Specified)) (Continued) −1dB Compression to Load Harmonic Distortion vs. Frequency DS012711-30 DS012711-31 2nd Harmonic Distortion vs. POUT DS012711-32 9 www.national.com CLC430 Typical Performance Characteristics CLC430 Application Division General Design Considerations The CLC430 is a general purpose current-feedback amplifier for use in a variety of small and large signal applications. Use the feedback resistor to fine tune the gain flatness and −3dB bandwidth for any gain setting. National provides information for the performance at a gain of +2 for small and large signal bandwidths. The plots show feedback resistor values for selected gains. Gain Use the following equations to set the CLC430’s non-inverting or inverting gain: Non -Inverting Gain = 1+ Inverting Gain = - VCC ± 15V ± 5V Enable > 12.7V < 10.0V > 2.7V < 0.08 Disable The amplifier is enabled with pin 8 left open due to the 2kΩ pull-up resistor, shown in Figure 2. +Vcc 2kΩ Rf Rg To CLC430 Bias network Rf Rg 8kΩ Choose the resistor values for non-inverting or inverting gain by the following steps. -Vcc Pin 8 DISABLE DS012711-35 FIGURE 2. Pin 8 Equivalent Disable Circuit Vin Open-collector or CMOS interfaces are recommended to drive pin 8. The turn on and off time depends on the speed of the digital interface. The equivalent output impedance when disabled is shown in Figure 3. With Rg connected to ground, the sum of Rf and Rg dominates and reduces the disabled output impedance. To raise the output impedance in the disabled state, connect the CLC430 as a unity-gain voltage follower by removing Rg. Current-feedback op-amps need the recommended Rf in a unity-gain follower circuit. For high density circuit layouts consider using the dual CLC431 (with disable) or the dual CLC432 (without disable). + Vout Rin CLC430 Rs - Rg Rf DS012711-34 FIGURE 1. Component Identification 1) Select the recommended feedback resistor Rf (refer to plot in the plot section entitled Rf vs. Gain). Equivalent Impedance in Disable Vin + 2) Choose the value of Rg to set gain. 3) Select Rs to set the circuit output impedance. 4) Select Rin for input impedance and input bias. 300kΩ Vout High Gains Current feedback closed-loop bandwidth is independent of gain-bandwidth-product for small gain changes. For larger gain changes the optimum feedback resister Rf is derived by the following: Rf = 724Ω - 60Ω x (AV). 8pF - Rg As gain is increased, the feedback resistor allows bandwidth to be held constant over a wide gain range. For a more complete explanation refer to application note OA-25 Stability Analysis of Current-Feedback Amplifiers. Resistors have varying parasitics that affect circuit performance in high speed design. For best results, use leaded metal-film resistors or surface mount resistors. A SPICE model for the CLC430 is available to simulate overall circuit performance. Enable/Disable Function The CLC430 amplifier features an enable/disable function that changes the output and inverting input from low to high impedance. The pin 8 enable/disable logic levels are as follows: www.national.com Rf DS012711-36 FIGURE 3. Equivalent Disabled Output Impedance 2nd and 3rd Harmonic Distortion To meet low distortion requirements, recognize the effect of the feedback resistor. Increasing the feedback resistor will decrease the loop gain and increase distortion. Decreasing the load impedance increases 3rd harmonic distortion more than 2nd. 10 (Continued) R Rf − Vin f Vout = Vin 1 + ac DC R || R 2 R2 g Differential Gain and Differential Phase The CLC430 has low DG and DP errors for video applications. Add an external pulldown resistor to the CLC430’s output to improve DG and DP as seen in Figure 4. A 604Ω RP will improve DG and DP to 0.01% and 0.02˚. + Vin AC C Rin Add Rp to improve DG and DP Vout CLC430 Vin DC Vin CLC430 Application Division Rf R2 Rg + Vout Rin CLC430 DS012711-38 Rs - FIGURE 5. Level Shifting Circuit Multiplexing Multiple signal switching is easily handled with the disable function of the CLC430. Board trace capacitance at the output pin will affect the frequency response and switching transients. To lessen the effects of output capacitance place a resistor (Ro) within the feedback loop to isolate the outputs as shown in Figure 6. To match the mux output impedance to a transmission line, add a resistor (Rs) in series with the output. Rp Rg Rf -Vcc DS012711-37 FIGURE 4. Improved DG and DP Video Amplifier Printed Circuit Layout To get the best amplifier performance careful placement of the amplifier, components and printed circuit traces must be observed. Place the 0.1µF ceramic decoupling capacitors less than 0.1″ (3mm) from the power supply pins. Place the 6.8µF tantalum capacitors less than 0.75″ (20mm) from the power supply pins. Shorten traces between the inverting pin and components to less than 0.25″ (6mm). Clear ground plane 0.1″ (3mm) away from pads and traces that connect to the inverting, non-inverting and output pins. Do not place ground or power plane beneath the op-amp package. National provides literature and evaluation boards 730013 DIP or 730027 SOIC illustrating the recommended op-amp layout. Applications Circuits Level Shifting The circuit shown in Figure 5 implements level shifting by AC coupling the input signal and summing a DC voltage. The resistor Rin and the capacitor C set the high-pass break frequency. The amplifier closed-loop bandwidth is fixed by the selection of Rf. The DC and AC gains for circuit of Figure 5 are different. The AC gain is set by the ratio of Rf and Rg. And the DC gain is set by the parallel combination of Rg and R2. Rf Rg Ro CLC430 Vin1 Rs DIS1 Rin Vout DIS2 Vin2 Ro CLC430 RL Rin Rf Rg DS012711-39 FIGURE 6. Output Connection 11 www.national.com CLC430 Application Division (Continued) Automatic Gain Control Current-feedback amplifiers can implement very fast automatic-gain control circuits. The circuit shown in Figure 7 shows an AGC circuit using the CLC430, a half-wave rectifier, an integrator and a FET. The CLC430 current-feedback amplifier maintains constant bandwidth and linear phase over AGC’s gain range. This circuit effectively controls the output level for continuous signals. DS012711-40 FIGURE 7. AGC Circuit The bandwidth of CLC430 AGC is limited by Rf, the feedback resistor. The FET gate voltage is limited to a range of: −2.5 < Vg < −1 R of 750Ω and C1 of 1.0µF gives a useful Rds range of approximately 150 to 2kΩ. Scaling the integrator gain or adding attenuation before the diode D accommodates large signal swings. Determine the overall gain by: 1+ Rf R g + R ds The integrator sets the loop time constant. www.national.com 12 CLC430 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Product Number N08E 13 www.national.com CLC430 General Purpose 100MHz Op Amp with Disable Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.