WED3DL644V White Electronic Designs 4Mx64 SDRAM FEATURES DESCRIPTION n n n n n n The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA. 53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 133, 125 and 100MHz The WED3DL644V is available in clock speeds of 133MHz, 125MHz and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Burst Operation Sequential or Interleaved Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write The package and design provides performance enhancements via a 50% reduction in capacitance vs. four monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise. Multiple Burst Read and Single Write n n n n n Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 17mm x 23mm, 153 BGA FIG. 1 PIN DESCRIPTION PINOUT (TOP A B C D E F G H J K L M N P R T U 1 DQ 41 DQ 40 DQ 33 DQ 32 NC NC CE 2 NC NC NC CE 1 NC NC DQ 30 DQ 31 DQ 22 DQ 23 August 2002 Rev.1 ECO #15464 2 3 DQ 43 DQ 45 DQ 42 DQ 44 DQ 35 DQ 37 DQ 34 DQ 36 DQML2 DQMH2 V DDQ V DDQ CE 3 V SS NC V SS CKE CAS NC V SS CE 0 V SS V DDQ V DDQ DQMH 1 DQML1 DQ 28 DQ 26 DQ 29 DQ 27 DQ 20 DQ 18 DQ 21 DQ 19 4 DQ 47 DQ 46 DQ 39 DQ 38 VDD VDD V SS CLK 1 RAS CLK 0 V SS VDD VDD DQ 24 DQ 25 DQ 16 DQ 17 5 NC NC NC NC VDD VDD V SS V SS WE V SS V SS VDD VDD NC NC NC NC VIEW) 6 DQ 48 DQ 49 DQ 56 DQ 57 VDD VDD V SS V SS A9 V SS V SS VDD VDD DQ 06 DQ 07 DQ 14 DQ 15 7 8 DQ 50 DQ 52 DQ 51 DQ 53 DQ 58 DQ 60 DQ 59 DQ 61 DQML3 DQMH 3 V DDQ V DDQ V SS A4 V SS A5 A11 A6 V SS A7 V SS A8 V DDQ V DDQ DQMH 0 DQML0 DQ 04 DQ 02 DQ 05 DQ 03 DQ 12 DQ 10 DQ 13 DQ 11 1 9 DQ 54 DQ 55 DQ 62 DQ 63 NC A3 A2 A1 A0 A10 BA 1 BA 0 NC DQ 00 DQ 01 DQ 08 DQ 09 A0 A11 Address Bus BA0-1 Bank Select Addresses DQ0-63 Data Bus CLK0-1 Clock CKE Clock Enable DQML0-3 Data Input/Output Masks DQMH0-3 RAS Row Address Strobe CAS Column Address Strobe WE Write Enable CE0-3 Chip Enables VDD Power Supply pins, 3.3V VDDQ Data Bus Power Supply, 3.3V V SS Ground pins White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs FIG. 2 4MX64 SDRAM BLOCK DIAGRAM White Electronic Designs Corporation Westborough, MA (508) 366-5151 2 WED3DL644V White Electronic Designs WED3DL644V INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CLK Type Input CKE Input Level Active High CE Input Pulse Active Low RAS, CAS WE BA0,BA1 Input Pulse Active Low Input Level A0-11, A10/AP Input Level Input/Output Level DQ DQML0 - (DQ0-7) DQMH0 - (DQ8-15) DQML1 - (DQ16-23) DQMH1 - (DQ24-31) DQML2 - (DQ31-39) DQMH2 - (DQ40-47) DQML3 - (DQ48-55) DQMH3 - (DQ56-63) VDD, VSS Input Signal Polarity Pulse Positive Edge Pulse Mask Active High Supply Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A 0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A 0-7 defines the column address (CA0-7 ) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A 10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Each DQM pin controls the byte in parentheses associated with it. Power and ground. RECOMMENDED DC OPERATING CONDITIONS A BSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD/VDDQ Input Voltage VIN Output Voltage VOUT Operating Temperature TOPR Storage Temperature TSTG Power Dissipation PD Short Circuit Output Current IOS Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 3.0 50 (VOLTAGE REFERENCED TO: VSS = 0V) Units V V V °C °C W mA Parameter Symbol Supply Voltage VDD/VDDQ Input High Voltage VIH Input Low Voltage VIL Output High Voltage (IOH =-2mA) VOH Output Low Voltage (IOL = 2mA) VOL Input Leakage Voltage IIL Output Leakage Voltage IOL Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Min Typ Max Unit 3.0 3.3 3.6 V 2.0 3.0 VDD +0.3 V -0.3 0.8 V 2.4 V 0.4 V -5 5 µA -5 5 µA CAPACITANCE (TA = 25°C, f= 1MHZ, VDD = 3.3V) Parameter Input Capacitance Input/Output Capacitance (DQ) 3 Symbol C IN C OUT Max 8 5 Unit pF pF White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V OPERATING CURRENT CHARACTERISTICS (VCC = 3.6V, TA = -40°C TO +85°C) Parameter Symbol Conditions Operating Current (One Bank Active)1 ICC1 Burst Length = 1, tRC ³ tRC (min), IOL = 0mA Operating Current (Burst Mode)1 ICC4 Page Burst, 4 banks active, t CCD = 2 clocks Precharge Standby Current in Power Down Mode ICC2P CKE £ VIL (max), tCC = 15ns ICC2PS CKE, CLK £ VIL (max), t CC = ¥, Inputs Stable ICC1N CKE = VIH, tCC = 15ns Precharge Standby Current in Input Change one time every 30ns Non-Power Down Mode ICC1NS CKE ³ VIH (min), tCC = ¥ No Input Change Precharge Standby Current in Power Down Mode ICC3P CKE £ VIL(max), tCC = 15ns ICC3PS CKE £ VIL(max), tCC = ¥ ICC3N CKE = VIH, tCC = 15ns Active Standby Current in Non-Power Down Mode Input Change one time every 30ns (One Bank Active) ICC3NS CKE ³ VIH(min), tCC = ¥, No Input Change Refresh Current2 ICC5 tRC ³ tRC(min) Self Refresh Current ICC6 CKE £ 0.2V NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. White Electronic Designs Corporation Westborough, MA (508) 366-5151 4 -7 560 500 2 2 160 -8 540 480 2 2 160 -10 500 440 2 2 160 Units mA mA mA mA mA 120 120 120 mA 12 12 500 12 12 480 12 12 440 mA mA mA 385 160 4 375 160 4 350 140 4 mA mA mA WED3DL644V White Electronic Designs Mode Register Definition A11 11 A10 10 A9 9 A8 8 A6 A7 6 7 Reserved* WB Op Mode A5 5 A4 A3 4 CAS Latency 1 2 BT A1 A2 3 Burst Definition 0 Burst Length Address Bus A0 2 Mode Register (Mx) Burst Length *Should program M11, M10 = ì 0, 0î to ensure compatibility with future devices. 4 Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 M9 Starting Column Address 8 Full Page (y) A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 n = A0-A9/8/7 (location0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... Ö Cn - 1, CnÖ 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - All other states reserved Write Burst Mode 0 Programmed Burst Length 1 Single Location Access 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL644V White Electronic Designs SDRAM AC CHARACTERISTICS Symbol Parameter Clock Cycle Time 1 CL = 3 CL = 2 Clock to valid Output delay 1,2 Output Data Hold Time 2 Clock HIGH Pulse Width3 Clock LOW Pulse Width 3 Input Setup Time 3 Input Hold Time 3 CLK to Output Low-Z 2 CLK to Output High-Z Row Active to Row Active Delay 4 RAS to CAS Delay4 Row Precharge Time 4 Row Active Time 4 Row Cycle Time - Operation4 Row Cycle Time - Auto Refresh 4,8 Last Data in to New Column Address Delay 5 Last Data in to Row Precharge 5 Last Data in to Burst Stop5 Column Address to Column Address Delay6 Data Out to High Impedance from Precharge tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD CL3 t ROH CL2 t ROH 133MHz Min Max 7 1000 7.5 1000 5.4 2 2.5 2.5 2 1 1.0 5.4 14 15 15 37 120,000 60 66 1 2 1 1.0 3 2 125MHz Min 8 10 Max 1000 1000 6 2 2.75 2.75 2 1 1 6 20 20 20 50 70 70 1 2 1 1.0 3 2 120,000 100MHz Min Max 10 1000 12 1000 7 2 3 3 2 1 1.5 7 20 20 20 50 120,000 80 80 1 2 1 1.5 3 2 NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit. White Electronic Designs Corporation Westborough, MA (508) 366-5151 6 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK CLK WED3DL644V White Electronic Designs COMMAND TRUTH TABLE Function Register Refresh Mode Register Set Auto Refresh (CBR) Entry Self Refresh Precharge Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Clock Suspend/Standby Mode Data Write/Output Disable Data Mask/Output Disable Power Down Mode Entry Exit CKE Previous Current Cycle Cycle H X H H H L H X H X H X H X H X H X H X H X H X H X L X H X H X X L X H CE RAS CAS WE L L L L L L L L L L L L H X X X H H L L L L L L H H H H H H X X X X X X L L L H H H L L L L H H X X X X X X L H H L L H L L L H L H X X X X X X DQM BA0-1 X X X X X X X X X X X X X X L H X X X X BA X BA BA BA BA BA X X X X X X X X A10/AP A9-0 A11 OP CODE X X X X L X H X Row Address L Column H Column L Column H Column X X X X X X X X X X X X X X X X Notes 2 3 4 4 5 5 NOTES: 1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock. 2. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 3. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 4. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 5. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device cant remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL644V White Electronic Designs CLOCK ENABLE (CKE) TRUTH TABLE Current State Self Refresh Power Down All Banks Idle Any State other than listed above CKE Previous Current Cycle Cycle H X L H L H L H L H L H L L H X L H L H H X H H H H H H H H H H H L H L H L H L H H L X H H H L L L H L Command CAS WE BA0-1 CE RAS X H L L L L X X H L L H L L L L H L L L L X X X X H H H L X X X X H X H L L L X H L L L X X X X H H L X X X X X L X X H L L X X H L L X X X X H L X X X X X X L X X X H L X X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Action Notes INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode 1 2 2 2 2 2 Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set 3 Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 3 A10-11 X X X X X X X X X X X OP Code X OP Code X X X X X 1 2 2 2 4 4 4 5 NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (t CKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. White Electronic Designs Corporation Westborough, MA (508) 366-5151 8 WED3DL644V White Electronic Designs CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write Read with Auto Precharge Command CE RAS CAS WE BA0-1 L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Action Notes Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 2 2,3 Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect 9 4 2 2 5 6 2 7,8 7,8 4 8,9 8,9 4 8,9 8,9 4 4 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com WED3DL644V White Electronic Designs CURRENT STATE TRUTH TABLE (CONT.) Current State Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge Command CE RAS CAS WE BA0-1 L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X Action A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Notes Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect White Electronic Designs Corporation Westborough, MA (508) 366-5151 10 ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after t RP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after t RP No Operation; Bank(s) idle after t RP No Operation; Bank(s) idle after t RP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after t RCD No Operation; Row active after t RCD No Operation; Row active after t RCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after t DPL No Operation; Row active after t DPL No Operation; Row active after t DPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after t DPL No Operation; Precharge after t DPL No Operation; Precharge after t DPL 4 4 4 4 4 4 4,10 4 4 4 4 9 9 4 4 4,9 4,9 WED3DL644V White Electronic Designs CURRENT STATE TRUTH TABLE (CONT.) Current State Refreshing Mode Register Accessing Command CE RAS CAS WE L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X Action BA0-1 A11, A10/AP-A0 OP Code X X X X BA Row Address BA Column BA Column X X X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X X X Notes Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after t RC No Operation; Idle after t RC No Operation; Idle after t RC Load mode register ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 11 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1 NOTES: 1. All input except CKE & DQM can be don't care when CE is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. BA0 0 0 1 1 BA1 Active & Read/Write 0 Bank A 1 Bank B 0 Bank C 1 Bank D 4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP BA0 BA1 Precharge 0 0 0 Bank A 0 0 1 Bank B 0 1 0 Bank C 0 1 1 Bank D 1 x x All Banks White Electronic Designs Corporation Westborough, MA (508) 366-5151 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP 0 1 12 BA0 BA1 Operation 0 0 Distribute auto precharge, leave bank A active at end of burst. 0 1 Disable auto precharge, leave bank B active at end of burst. 1 0 Disable auto precharge, leave bank C active at end of burst. 1 1 Disable auto precharge, leave bank D active at end of burst. 0 0 Enable auto precharge, precharge bank A at end of burst. 0 1 Enable auto precharge, precharge bank B at end of burst. 1 0 Enable auto precharge, precharge bank C at end of burst. 1 1 Enable auto precharge, precharge bank D at end of burst. White Electronic Designs WED3DL644V FIG. 4 POWER UP SEQUENCE 13 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4 NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst). White Electronic Designs Corporation Westborough, MA (508) 366-5151 14 White Electronic Designs WED3DL644V FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4 NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 15 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4 NOTES: 1. CE can be don't care when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corporation Westborough, MA (508) 366-5151 16 White Electronic Designs WED3DL644V FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4 NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. 17 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4 NOTE: 1. tCDL should be met to complete write. White Electronic Designs Corporation Westborough, MA (508) 366-5151 18 White Electronic Designs WED3DL644V FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH=4 NOTE: 1. tCDL should be controlled to meet minimum t RAS before internal precharge start. (in the case of Burst Length=1 & 2 and BRSW mode) 19 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS LATENCY=2, BURST LENGTH=4 NOTE: 1. DQM is needed to prevent bus contention. White Electronic Designs Corporation Westborough, MA (508) 366-5151 20 White Electronic Designs WED3DL644V FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @BURST LENGTH=FULL PAGE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length. 21 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @BURST LENGTH=FULL PAGE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. White Electronic Designs Corporation Westborough, MA (508) 366-5151 22 White Electronic Designs WED3DL644V FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2 @BURST LENGTH=FULL PAGE NOTES: 1. BRSW mode is enabled by setting A9 High at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to 1 regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. 23 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs WED3DL644V FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS LATENCY=2, BURST LENGTH=4 NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1 CLK + tSS prior to Row active command. 3. Cannot violate minimum refresh specification (64ms). White Electronic Designs Corporation Westborough, MA (508) 366-5151 24 White Electronic Designs WED3DL644V FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE NOTES: TO ENTER SELF REFRESH MODE 1. CE, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum t RAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE starts from high. 6. Minimum t RFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. 25 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com White Electronic Designs FIG. 17 MODE REGISTER SET CYCLE FIG. 18 AUTO REFRESH CYCLE NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. White Electronic Designs Corporation Westborough, MA (508) 366-5151 WED3DL644V 26 White Electronic Designs WED3DL644V PACKAGE DESCRIPTION NOTE: 1. All dimensions and tolerances conform to ASME Y14.5m 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum. 3. Primary datum seating place is defined by the spherical crowns of the solder balls. 4. The surface finish of the package shall be EDM Charmille #24 - #27 ORDERING INFORMATION Part Number WED3DL644V7BC WED3DL644V8BC WED3DL644V10BC WED3DL644V7BI WED3DL644V8BI WED3DL644V10BI Clock Frequency 133MHz 125MHz 100MHz 133MHz 125MHz 100MHz Package 153 BGA 153 BGA 153 BGA 153 BGA 153 BGA 153 BGA 27 Operating Range Commercial Commercial Commercial Industrial Industrial Industrial White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com