AD AD1887JST

a
AC’97 SoundMAX® Codec
AD1887
ENHANCED FEATURES
Full Duplex Variable Sample Rates from 7040 Hz to
48 kHz with 1 Hz Resolution
Software-Enabled VREFOUT Output for Microphones and
External Power Amp
Split Power Supplies (3.3 V Digital/5 V Analog)
Mobile Low-Power Mixer Mode
Extended 6-Bit Headphone Volume Control
Digital Audio Mixer Mode
AC’97 2.1 FEATURES
Variable Sample Rate Audio
AC’97 FEATURES
AC’97 2.2 Compliant
Greater than 90 dB Dynamic Range
Integrated Stereo Headphone Amplifier
Multibit ⌺-⌬ Converter Architecture for Improved S/N
Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Two Analog Line-Level Stereo Inputs for:
LINE-IN and CD
Mono MIC Input with Built-In Programmable Preamp
High-Quality CD Input with Ground Sense
Power Management Support
48-Terminal TQFP Package
FUNCTIONAL BLOCK DIAGRAM
ID0
AD1887
MIC
ID1
VREF
CHIP SELECT
VREFOUT
MIC
PREAMP
SELECTOR
LINE_IN
CD
PGA
16-BIT
⌺-⌬ A/D
CONVERTER
PGA
16-BIT
⌺-⌬ A/D
CONVERTER
RESET
SYNC
HP_OUT_R
HP
HP
M
M
GA
GA
GA
GA
GA
GA
M
M
M
M
M
SELECTOR
HP_OUT_L
GA
SAMPLE
RATE
GENERATORS
AC
LINK
BIT_CLK
SDATA_OUT
M
GA
16-BIT
⌺-⌬ A/D
CONVERTER
M
GA
16-BIT
⌺-⌬ A/D
CONVERTER
SDATA_IN
M
M
G = GAIN
A = ATTENUATE
M = MUTE
OSCILLATOR
XTL_OUT
XTL_IN
SoundMAX is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD1887–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
25°C
DAC Test Conditions
Digital Supply (VDD)
3.3 V
Calibrated
Analog Supply (VCC)
5.0 V
–3 dB Attenuation Relative to Full Scale
48 kHz
Sample Rate (fS)
Input 0 dB
Input Signal
1008 Hz
32 Ω Output Load (HP_OUT)
Analog Output Pass Band
20 Hz to 20 kHz
2.0 V
VIH
ADC Test Conditions
VIL
0.8 V
Calibrated
VIH (CS0, CS1)
4.0 V
0 dB Gain
1.0 V
VIL
Input –3.0 dB Relative to Full Scale
ANALOG INPUT
Parameter
Min
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, CD
MIC with 20 dB Gain
MIC with 0 dB Gain
Input Impedance*
Input Capacitance*
Typ
Max
Unit
1
2.83
0.1
0.283
1
2.83
20
5
7.5
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
pF
Typ
Max
Unit
80
dB
dB
dB
Max
Unit
HEADPHONE OUT VOLUME
Parameter
Min
Step Size (+6 dB to –88.5 dB); HP_OUT_R, HP_OUT_L
Output Attenuation Range Span*
Mute Attenuation of 0 dB Fundamental*
1.5
–94.5
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Step Size (0 dB to 22.5 dB)
PGA Gain Range Span
Typ
1.5
22.5
dB
dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Min
Signal-to-Noise Ratio (SNR)
CD to HP_OUT
Other to HP_OUT
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, CD, DAC
Input Gain/Attenuation Range:
MIC, LINE_IN, CD, DAC
Typ
Max
Unit
90
90
dB
dB
1.5
dB
–46.5
dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter
Min
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Rejection
Group Delay
Group Delay Variation over Pass Band
0
0.4 × fS
0.6 × fS
–74
Typ
Max
Unit
0.4 × fS
± 0.09
0.6 × fS
∞
Hz
dB
Hz
Hz
dB
sec
µs
12/fS
0.0
*Guaranteed but not tested.
–2–
REV. 0
AD1887
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Min
Resolution
Total Harmonic Distortion (THD)
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
84
Typ
Max
16
–84
87
85
Unit
Bits
dB
dB
dB
–100
–90
–90
–85
± 10
± 0.5
±5
dB
dB
%
dB
mV
Min
Typ
Max
Unit
85
16
–75
90
–100
± 10
± 0.7
–80
Bits
dB
dB
dB
%
dB
dB
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Resolution
Total Harmonic Distortion (THD) HP_OUT
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion* (CCIF Method)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L,
Measure L_OUT)
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)*
–40
dB
ANALOG OUTPUT
Parameter
Min
Full-Scale Output Voltage; HP_OUT
Typ
Max
1
2.83
Output Impedance*
External Load Impedance*
Output Capacitance*
External Load Capacitance
VREF
VREF_OUT
VREF_OUT Current Drive
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
800
32
2.05
2.25
2.25
15
100
2.45
5
±5
Unit
V rms
V p-p
Ω
Ω
pF
pF
V
V
mA
mV
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
High-Level Input Voltage (VIH): Digital Inputs
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH), IOH = 2 mA
Low-Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
Output Leakage Current
0.65 × DVDD
Typ
Max
Unit
V
0.35 × DVDD V
V
0.1 × DVDD V
+10
µA
+10
µA
0.9 × DVDD
–10
–10
POWER SUPPLY
Parameter
Min
Power Supply Range—Analog (AVDD)
Power Supply Range—Digital (DVDD)
Power Dissipation—5 V/3.3 V
Analog Supply Current—5 V (AVDD)
Digital Supply Current—3.3 V (DVDD)
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
4.75
3.15
*Guaranteed but not tested.
REV. 0
–3–
Typ
253
36
22
40
Max
Unit
5.25
3.45
V
V
mW
mA
mA
dB
AD1887–SPECIFICATIONS
CLOCK SPECIFICATIONS*
Parameter
Min
Typ
Max
Unit
Input Clock Frequency
Recommended Clock Duty Cycle
40
24.576
50
60
MHz
%
POWER-DOWN STATES
Parameter
Set Bits
DVDD Typ
AVDD Typ
Unit
ADC
DAC
ADC + DAC
ADC + DAC + Mixer (Analog CD On)
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Analog CD Only (AC-Link On)
Analog CD Only (AC-Link Off)
Standby
Headphone Standby
PR0
PR1
PR1, PR0
LPMIX, PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
LPMIX, PR5, PR1, PR0
LPMIX, PR1, PR0, PR4, PR5
PR5, PR4, PR3, PR2, PR1, PR0
PR6
15.82
15.08
3.79
3.85
17.65
15.70
15.07
3.80
3.85
0.06
0.06
17.66
30.0
26.3
19.9
18.1
17.4
11.1
8.3
2.1
18.1
18.1
0
26.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*Guaranteed but not tested.
Specifications subject to change without notice.
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
Min
Typ
Max
1.0
162.8
1.3
19.5
162.8
12.288
81.4
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
32.56
32.56
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
5
5
2
2
2
2
2
2
2
2
0
15
42
38
48.0
20.8
2.5
4
4
4
4
4
4
4
4
750
48.84
48.84
6
6
6
6
6
6
6
6
1.0
25
15
50
15
Unit
µs
ns
µs
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
–4–
REV. 0
AD1887
BIT_CLK
tRST_LOW
tRST2CLK
tFALLCLK
tRISECLK
RESET
SYNC
BIT_CLK
tRISESYNC
Figure 1. Cold Reset
tFALLSYNC
SDATA_IN
tRISEDIN
tRST2CLK
tSYNC_HIGH
SYNC
tFALLDIN
SDATA_OUT
BIT_CLK
tRISEDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
SYNC
BIT_CLK
tFALLDOUT
SLOT 1
SLOT 2
WRITE
TO 0x26
DATA
PR4
tCLK_HIGH
BIT_CLK
tCLK_PERIOD
tSYNC_LOW
SDATA_OUT
DON’T
CARE
SYNC
tS2_PDOWN
tSYNC_HIGH
SDATA_IN
tSYNC_PERIOD
NOTE: BIT_CLK NOT TO SCALE
Figure 6. AC Link Low Power Mode Timing
Figure 3. Clock Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC
tSETUP2RST
SDATA_IN, BIT_CLK
SDATA_OUT
tOFF
tHOLD
Figure 7. ATE Test Mode
Figure 4. Data Setup and Hold
REV. 0
HI-Z
–5–
AD1887
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supplies
Digital (DVDD)
Analog (AVCC)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
Max
Temperature
Range
Unit
Model
–0.3
–0.3
–0.3
–0.3
0
–65
+3.6
+6.0
± 10.0
AVDD + 0.3
DVDD + 0.3
70
+150
AD1887JST 0°C to 70°C
V
V
mA
V
V
°C
°C
Package
Description
Package
Option
Thin-Quad Flatpack ST-48
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package
␪JA
␪JC
␪CA
TQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
NC
AVDD2
HP_OUT_L
AVSS2
HP_OUT_R
NC
AVDD3
ID0
AVSS3
ID1
NC
NC
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1
XTL_IN 2
PIN 1
IDENTIFIER
XTL_OUT 3
DVSS1 4
SDATA_OUT 5
AD1887
BIT_CLK 6
DVSS2 7
TOP VIEW
(Not to Scale)
SDATA_IN 8
DVDD2 9
36
NC
35
NC
34
NC
33
NC
32
FILT_L
31
FILT_R
30
AFILT2
29
AFILT1
VREFOUT
28
SYNC 10
RESET 11
NC 12
27
VREF
26
AVSS1
25
AVDD1
–6–
LINE_IN_R
LINE_IN_L
NC
CD_R
MIC_IN
CD_L
NC
NC
CD_GND_REF
NC = NO CONNECT
NC
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
REV. 0
AD1887
PIN FUNCTION DESCRIPTIONS
Digital I/O
Pin Name
TQFP
I/O
Description
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
2
3
5
6
8
10
11
I
O
I
O/I
O
I
I
Crystal (or Clock) Input, 24.576 MHz
Crystal Output
AC-Link Serial Data Output, AD1887 Input Stream
AC-Link Bit Clock 12288 MHz Serial Data Clock Daisy Chain Output Clock
AC-Link Serial Data Input AD1887 Output Stream
AC-Link Frame Sync
AC-Link Reset AD1887 Master H/W Reset
Pin Name
TQFP
Type
Description
ID0
ID1
45
46
I
I
Chip Select Input 0 (Active Low)
Chip Select Input 1 (Active Low)
Chip Selects
Analog I/O
These signals connect the AD1887 component to analog sources and sinks, including microphones and speakers
Pin Name
TQFP
I/O
Description
CD_L
CD_GND_REF
CD_ R
MIC
LINE_IN_L
LINE_IN_R
HP_OUT_L
HP_OUT_R
18
19
20
21
23
24
39
41
I
I
I
I
I
I
O
O
CD Audio Left Channel
CD Audio Analog Ground Reference for Differential CD Input
CD Audio Right Channel
Microphone Input
Line in Left Channel
Line in Right Channel
Headphones Out Left Channel
Headphones Out Right Channel
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages
Pin Name
TQFP
I/O
Description
VREF
VREFOUT
AFILT1
AFLIT2
FILT_R
FILT_L
27
28
29
30
31
32
O
O
O
O
O
O
Voltage Reference Filter
Voltage Reference Output 5 mA Drive (Intended for Mic Bias)
Antialiasing Filter Capacitor—ADC Right Channel
Antialiasing Filter Capacitor—ADC Left Channel
AC-Coupling Filter Capacitor—ADC Right Channel
AC-Coupling Filter Capacitor—ADC Left Channel
Power and Ground Signals
Pin Name
TQFP
Type
Description
DVDD1
DVSS1
DVSS2
DVDD2
AVDD1
AVSS1
AVDD2
AVSS2
AVDD3
AVSS3
1
4
7
9
25
26
38
40
43
44
I
I
I
I
I
I
I
I
I
I
Digital VDD 33 V
Digital GND
Digital GND
Digital VDD 33 V
Analog VDD 50 V
Analog GND
Analog VDD 50 V
Analog GND
Analog VDD 50 V
Analog GND
REV. 0
–7–
AD1887
No Connects
Pin Name
TQFP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
13
14
15
16
17
22
33
34
35
36
37
42
47
48
Type
Description
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
Indexed Control Registers
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0010h
04h
Headphones Volume
HPM
X
LHV5
LHV4
LHV3
LHV2
LHV1
LHV0
X
X
RHV5
RHV4
RHV3
RHV2
RHV1 RHV0
8000h
08h
Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
00Eh
Mic Volume
MCM
X
X
X
X
X
X
X
X
M30
X
MCV4
MCV3
MCV2 MCV1 MCV0 8008h
10h
Line-In Volume
LM
X
X
LLV4
LLV3
LLV2
LLV1
LLV0
X
X
X
RLV4
RLV3
RLV2
12h
CD Volume
CVM
X
X
LCV4
LCV3
LCV2
LCV1
LCV0
X
X
X
RCV4
RCV3
RCV2
RCV1 RCV0
8808h
18h
PCM Out Vol
OM
X
X
LOV4
LOV3
LOV2
LOV1
LOV0
X
X
X
ROV4
ROV3
ROV2
ROV1 ROV0
8808h
1Ah
Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
0000h
1Ch
Record Gain
IM
X
X
X
LIM3
LIM2
LIM1
LIM0
X
X
X
X
RIM3
RIM2
RIM1
RIM0
8000h
20h
General-Purpose
X
X
X
X
X
X
X
X
LPBK X
X
X
X
X
X
X
0000h
RLV1
RLV0
RS0
8808h
26h
Power-Down Ctrl/Stat
X
X
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Xh
28h
Ext’d Audio ID
ID1
ID0
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0005h
2Ah
Ext’d Audio Stat/Ctrl
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0000h
2Ch/
PCM DAC Rate (SR1) SR15
(7Ah)*
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
32h/
PCM ADC Rate (SR0) SR15
(78h)*
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
X
X
X
X
X
X
X
7000h
0404h
74h
Serial Configuration
SLOT16 REGM2 REGM1 REGM0 X
X
X
X
X
76h
Misc Control Bits
DACZ
7Ch
Vendor ID1
7Eh
Vendor ID2
LPMIX X
DAM
DMS
DLSR
X
ALSR
MOD SRX10 SRX8
EN
D7
D7
X
X
DRSR
X
ARSR
F7
F6
F5
F4
F3
F2
F1
F0
S7
S5
S4
S3
S2
S1
S0
4144h
T7
T6
T5
T4
T3
T2
T1
T0
REV7 REV6
REV5
REV4
REV3
REV2
REV1
REV0
5362h
S6
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819, AD1819A backward compatibility.
–8–
REV. 0
AD1887
Reset (Index 00h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0010h
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0]
Identify Capability. The ID decodes the capabilities of AD1887 based on the following:
Bit = 1
Function
AD1887*
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated Mic PCM in Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
0
0
0
*The AD1887 contains none of the optional features identified by these bits.
SE[4:0]
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Headphones Volume Registers (Index 04h)
Reg
Num
Name
04h
Headphones
HPM
Volume
D15
D14 D13
D12
D11
D10
D9
D9
X
LHV4
LHV3
LHV2
LHV1 LHV0
LHV5
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
X
X
RHV5 RHV4
D3
D3
D2
D2
D1
D1
D0
D0
Default
RHV3
RHV2 RHV1 RHV0 8000h
RHV[5:0]
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
LHV[5:0]
Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
HPM
Headphones Volume Mute. When this bit is set to “1,” the channel is muted.
REV. 0
HPM
xHV5 . . . xHV0
Function
0
0
0
1
00 0000
01 1111
11 1111
xx xxxx
6 dB Gain
–40.5 dB Attenuation
–88.5 dB Attenuation
–∞ dB Attenuation
–9–
AD1887
Mic Volume (Index 0Eh)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
0Eh
MIC
Volume
MCM
X
X
X
X
X
X
X
X
M30
X
MCV4
MCV3
MCV2
MCV1
MCV0
8008h
MCV[4:0]
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M30
Mic Boost Gain: Amplifies the Mic input. 0 = 0 dB, 1 = 30 dB
MCM
Mic Mute. When this bit is set to “1,” the channel is muted.
Line In Volume (Index 10h)
Reg
Num
N ame
D 15
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
10h
L in e In
Volu me
LM
LM
X
X
LLV4
LLV3
LLV2
LLV1
LLV0
X
X
X
RLV4
RLV3
RLV2
RLV1
RLV0
8808h
RLV[4:0]
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LLV[4:0]
Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LM
Line In Mute. When this bit is set to “1,” the channel is muted.
CD Volume (Index 12h)
Reg
Num
N ame
D 15
12h
CD
CD
Volu me
CVM X
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
X
LCV4
LCV3
LCV2
LCV1
LCV0
X
X
X
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0]
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LCV[4:0]
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CVM
CD Volume Mute. When this bit is set to “1,” the channel is muted.
–10–
REV. 0
AD1887
PCM Out Volume (Index 18h)
Reg
Num
N ame
D 15
D 14
D 13
D 12
18h
PCM O u t
Volu me
OM
OM
X
X
LO V4 LO V3 LO V2 LO V1 LO V0 X
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
X
X
RO V4 RO V3 RO V2 RO V1 RO V0 8808h
ROV[4:0]
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
LOV[4:0]
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
OM
PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute
x4 . . . x0
Function
0
0
0
1
00000
01000
11111
xxxxx
+12 dB Gain
0 dB Gain
–34.5 dB Gain
–∞ dB Gain
Record Select Control Register (Index 1Ah)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
1Ah
Record Select
X
X
X
X
X
LS2
LS1
LS0
X
X
X
X
X
RS2
RS1
RS0
0000h
RS[2:0]
Right Record Select
LS[2:0]
Left Record Select
Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to Mic in.
LS2 . . . LS0
Left Record Source
RS2 . . . RS0
Right Record Source
0
1
4
5
6
MIC
CD_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
0
1
4
5
6
MIC
CD_L
LINE_IN_R
Stereo Mix (R)
Mono Mix
Record Gain (Index 1Ch)
Reg
Num
N ame
D 15
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
1Ch
R e c or d G a in
IM
IM
X
X
X
LIM 3
LIM 2
LIM 1
LIM 0
X
X
X
X
RIM 3
RIM 2
RIM 1
RIM 0
8000h
RIM[3:0]
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
LIM[3:0]
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
IM
Input Mute
0 = Unmuted
1 = Muted or –∞ dB Gain
REV. 0
IM
xIM3 . . . xIM0
Function
0
0
1
1111
0000
xxxxx
22.5 dB Gain
0 dB Gain
–∞ dB Gain
–11–
AD1887
General Purpose Register (Index 20h)
Reg
Num
N ame
D 15
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
20h
G e n e r a l P u r pose
X
X
X
X
X
X
X
X
LPB K
X
X
X
X
X
X
X
0000h
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default
value is 0000h, which is all off.
LPBK
Loopback Control. ADC/DAC digital loopback mode.
Subsection Ready Register (Index 26h)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
26h
Power-Down Cntrl/Stat
X
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
NA
NA
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1887 subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its nominal state.
ADC
ADC section ready to transmit data.
DAC
DAC section ready to accept data.
ANL
Analog gainuators, attenuators, and mixers ready.
REF
Voltage References, VREF and VREFOUT up to nominal level.
PR[5:0]
AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
PR0 – Powered-Down ADC
PR1 – Powered-Down DAC
PR2 – Powered-Down Analog Mixer
PR3 – Powered-Down VREF and VREFOUT
PR4 – Powered-Down AC-Link
PR5 – Powered-Down Internal Clock
PR6 – Powered-Down Headphone
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are
both set.
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect or disable PR5.
Power-Down State
PR6
PR5
PR4
PR3
PR2
PR1
PR0
ADC Power-Down
DACs Power-Down
ADC and DAC Power-Down
Mixer Power-Down
ADC + Mixer Power-Down
DAC + Mixer Power-Down
ADC + DAC + Mixer Power-Down
Standby
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
–12–
REV. 0
AD1887
Extended Audio ID Register (Index 28h)
Reg
Num
N ame
D 15
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
28h
E x te n de d A u dio ID
ID 1
ID 0
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0001h
Note: The Extended Audio ID is a read only register.
VRA
Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.
ID[1:0]
ID1, ID0 is a 2-bit field which indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
Extended Audio Status and Control Register (Index 2Ah)
Reg
Num
N ame
D 15
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
2A h
E x t' d A u dio Sta t/ C tr l
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA
0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio mode (sample rate control registers and
SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
Reg
Num
N ame
D 15
2 C h / (7 A h ) P C M D A C R a te SR 1 5
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 B B 80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg
Num
N ame
D 15
3 2 h / (7 8 h )
P C M A D C R a te
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 B B 80h
D 14
D 13
D 12
D 11
D 10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0]
REV. 0
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.
–13–
AD1887
Serial Configuration (Index 74h)
Reg
Num
Name
D15
74h
Serial
Configuration
SLOT 16 REGM2
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6 D5
D5
D4
D4 D3
D3 D2
D2 D1
D1
D0
D0
Default
REGM1
REGM0
X
X
X
X
X
X
X
X
7000h
X
X
X
X
Note: This register is not reset when the reset register (Register 00h) is written.
DHWR
Disable Hardware Reset.
REGM0
Master Codec Register Mask.
REGM1
Slave 1 Codec Register Mask.
REGM2
Slave 2 Codec Register Mask.
SLOT16
Enable 16-bit slots.
If your system uses only a single AD1887, you can ignore the register mask bits.
SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg
Num
Name
D15
76h
Misc
DACZ
Control
Bits
D14
D13 D12
LPMIX
X
D11
DAM DMS
D10
D9
D9 D8
D8
DLSR X
ALSR
D7
D7
D6
D6
D5
D5
D4
D4 D3
D3 D2
D2
MOD
EN
EN
SRX10 SRX8 X
D7
D7
D7
D7
X
D1
D1 D0
D0
DRSR X
Default
ARSR 0404h
ARSR
ADC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DRSR
DAC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
SRX8D7
Multiply SR1 rate by 8/7.
SRX10D7
Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
MODEN
Modem filter enable (left channel only). Change only when DACs are powered down.
ALSR
ADC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DLSR
DAC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DMS
Digital Mono Select
0 = Mixer
1 = Left DAC + Right DAC
DAM
Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.
LPMIX
Low-Power Mixer
DACZ
Zero-fill (vs. repeat) if DAC is starved for data.
–14–
REV. 0
AD1887
Sample Rate 0 (Index 78h)
Reg
Num
Name
(32h)/78h
Sample
SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Rate 0
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D2
D2
D1
D1
D0
D0
Default
Note: 32h is an alias for 78h. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR0[15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg
Num
Name
(2Ch)/7Ah
Sample
SR115
Rate 1
D15
D14
D13
D12
D11
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D2
D2
D1
D1
D0
D0
Default
SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR1[15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch–7Eh)
Reg
Num
N ame
7Ch
V e n d o r I D 1 F7
F7
D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D9
D9
F6
F6
F5
F5
F4
F4
F3
F3
F2
F2
S[7:0]
This register is ASCII encoded to ‘A.’
F[7:0]
This register is ASCII encoded to ‘D.’
F1
F1
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
D efau lt
F0
F0
S7
S7
S6
S6
S5
S5
S4
S4
S3
S3
S2
S2
S1
S1
S0
S0
4144h
Reg
Name
Num
D15 D14 D13 D12 D11 D10 D9
D9
D8
D8
D7
D7
7Eh
T7
T7
T0
T0
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5362h
Vendor ID2
T[7:0]
REV. 0
T6
T6
T5
T5
T4
T4
T3
T3
T2
T2
T1
T1
This register is ASCII encoded to ‘S.’
–15–
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default
AD1887
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.354 (9.00) BSC SQ
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
24
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
0.006 (0.15) SEATING
0.002 (0.05) PLANE
PRINTED IN U.S.A.
COPLANARITY
0.003 (0.08)
C02497–.8–7/01(0)
48-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-48)
–16–
REV. 0