Voice Signal Interface Codec GENERAL DESCRIPTION cod0413x_pci FEATURES • Analog 2.5Volt Operation • Linear 14bit Codec • 3 Mic Inputs (2 Differential and 1 Single) • 3 Analog Outputs 32ohm Driver (2 Differential and 1 Single) • Mic Volume 0dB ~ 22.5dB & 20dB Gain On/Off accessed through a serial control channel that easily • Speaker Volume 0dB ~ -30dB interfaces to any classical micro controller. • Side-tone -12.5dB ~ -27.5dB • Serial Data Input, Output Format • Control Register Interface for u-Controller This IP core has been developing for AFE (Analog-front-end) function of voice signal processing with 14bit 8KHz voice codec. The core consists of 14bit linear monolithic PCM CODEC/transmit and receive band-pass filters utilizing the sigma-delta A/D and D/A conversion architecture. It offers a number of programmable functions This IP core is suitable for digital mobile phones, as cellular and cordless phones, or any battery powered equipment. APPLICATIONS • digital mobile phones • cellular and cordless phones FUNCTIONAL BLOCK DIAGRAM MIC1P MIC1N MIC2P MIC2N MIC3 20dB On/Off MIC VOLUME 0dB~22.5dB 1.5dB Step M U X ADC PGA 4 TGN[3:0] X10 2 PGA 4 SGN[3:0] ISS[1:0] AOUT1P AOUT1N SIDETONE AMP -12.5dB~-27.5dB -1dB Step SPEAKER VOLUME 0dB~-30dB -2.dB Step SOUT SIN S I G N A L I / F DAC MCLK FS STEN AOUT2P AOUT2N PGA 2 OSS[1:0] AOUT3 PORSB REN 4 RGN[3:0] CSB WRB RDB A[8:0] CONTROL REGISTER VREF REFERENCE IREF DIN[7:0] DOUT[7:0] (Test Pin) AVDD25A1 VABB AVDD25A2 AVSS25A1 AVDD25A3 AVSS25A2 AVDD25A4 AVSS25A3 AVDD25A5 AVSS25A4 AVDD25A6 AVSS25A5 AVDD25A7 AVSS25A6 AVDD25A8 AVSS25A7 AVDD25D AVSS25A8 AVSS25D Ver 1.4 (Apr 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SEC ASIC 1 / 13 ANALOG Voice Band Signal Interface cod0413x_pci CORE PIN DIAGRAM PIN NAME Type I/O Type FUNCTION AVDD25A1 AP vdd2t_abb Analog Power Supply 1 (2.5V) AVSS25A1 AG vss2t_abb Analog Ground 1 • • I/O TYPE ABBR. Power Pins AVDD25A2 AP vdd2t_abb Analog Power Supply 2 (2.5V) AVSS25A2 AG vss2t_abb Analog Ground 2 AVDD25A3 AP vdd2t_abb Analog Power Supply 3 (2.5V) AVSS25A3 AG vss2t_abb Analog Ground 3 • AVDD25A4 AP vdd2t_abb Analog Power Supply 4 (2.5V) • AVSS25A4 AG vss2t_abb Analog Ground 4 • AVDD25A5 AP vdd2t_abb Analog Power Supply 5 (2.5V) AVSS25A5 • • • • • AG vss2t_abb Analog Ground 5 AVDD25A6 DP vdd2t_abb Digital Power Supply 6 (2.5V) AVSS25A6 DG vss2t_abb Digital Ground 6 AVDD25A7 AP vdd2t_abb Analog Power Supply 7 (2.5V) AVSS25A7 AG vss2t_abb Analog Ground 7 AVDD25A8 AP vdd2t_abb Analog Power Supply 8 (2.5V) AVSS25A8 AG vss2t_abb Analog Ground 8 AVDD25D DP vdd2t_abb Digital Power Supply (2.5V) AVSS25D DG vss2t_abb Digital Ground VABB AG vbb_abb Analog Ground AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground Analog Pins MIC1P AI pia_abb Mic Input 1 Positive MIC1N AI pia_abb Mic Input 1 Negative MIC2P AI pia_abb Mic Input 2 Positive MIC2N AI pia_abb Mic Input 2 Negative MIC3 AI pia_abb Mic Input 3 (Single Input) AOUT1P AO poa_abb Differential Output 1 Positive AOUT1N AO poa_abb Differential Output 1 Negative AOUT2P AO poa_abb Differential Output 2 Positive AOUT2N AO poa_abb Differential Output 2 Negative AOUT3 AO poa_abb Single Output VREF AO poa_abb Reference Output VCOMDR AO poa_abb tied to VREF pin VCOMDT AO poa_abb tied to VREF pin VCOMR AO poa_abb tied to VREF pin VCOMT AO poa_abb tied to VREF pin VREFMR AO poa_abb tied to Analog Ground pin VREFMT AO poa_abb tied to Analog Ground pin VREFPR AO poa_abb tied to VREF pin VREFPT AO poa_abb tied to VREF pin IREF AO poa_abb Analog Current Control (Test Pin). If this pin is not used, it may be left floating state. SEC ASIC 2 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Digital Pins SOUT DO pot2_abb ADC Serial Data Ouput SIN DI picc_abb DAC Serial Data Input MCLK DI picc_abb Master Clock Input FS DI picc_abb Frame Sync Pulse Input PORSB DI picc_abb Power-On-Reset and Reset Control Input (Low Active) CSB DI picc_abb Chip Select (Low Active) WRB DI picc_abb Write Enable (Low Active) RDB DI picc_abb Read Enable (Low Active) A[8:0] DI picc_abb Control Register Address DIN[7:0] DI picc_abb Control Register Data Input (WR is Enabled) DOUT[7:0] DO pot2_abb Control Register Data Output (RD is Enabled) CORE CONFIGURATION AVDD25D AVDD25A8 AVDD25A7 AVDD25A6 AVDD25A5 AVDD25A4 AVDD25A3 AVDD25A2 AVDD25A1 MIC1P MIC1N MIC2P MIC2N MIC3 SIN cod0413x_pci MCLK FS PORSB CSB WRB RDB A[8:0] DIN[7:0] AOUT1P AOUT1N AOUT2P AOUT2N AOUT3 SOUT VREF VCOMDR VCOMDT VCOMR VCOMT VREFMR VREFMT VREFPR VREFPT DOUT[7:0] IREF VABB AVSS25D AVSS25A8 AVSS25A7 AVSS25A6 AVSS25A5 AVSS25A4 AVSS25A3 AVSS25A2 AVSS25A1 Power Group : AVDD25A1 (AVDD25A1,AVDD25A2,AVDD25A3,AVDD25A4,AVDD25A5,AVDD25A6,AVDD25A8) AVDD25A2 (AVDD25A7) AVDD25D (AVDD25D) SEC ASIC 3 / 13 ANALOG Voice Band Signal Interface cod0413x_pci ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit AVDD25A1 AVDD25A2 AVDD25D 3.3 V Analog Input Voltage - AVSS25A1 to AVDD25A1 AVSS25A2 to AVDD25A2 V Digital Input Voltage - AVSS25D to AVDD25D V VOH, VOL AVSS25D to AVDD25D V Tstg -45 to 125 ºC Supply Voltage Digital Output Voltage Storage Temperature Range NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5KΩ resistor (Human body model) 4. This core has initial calibration time for about 3m second from rising edge of PORSB. RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage AVDD25A1,AVDD25A2, AVDD25D 2.375 2.5 2.625 V Supply Voltage Difference AVDD25A1, AVDD25A2, AVDD25D -0.1 0.0 0.1 V Digital Input Voltage 2.25 2.5 2.75 V Analog Input Voltage - 1.6 - Vpp -40 - 85 ºC Characteristics Operating Temperature Topr NOTES 1. It is strongly recommended that all the supply pins (AVDD25A1, AVDD25A2, AVDD25D) be powered from the same source to avoid power latch-up. AC ELECTRICAL CHARACTERISTICS (Measurement Bandwidth is 20Hz~4KHz. Full scale input sine wave 1KHz, FS=8KHz, @AVDD25A1=2.5V, AVDD25A2=2.5V, AVDD25D=2.5V Ta=55ºC,Unless otherwise specified.) Characteristics Min Typ Max Unit Conditions Resolution Symbol - 14 - Bits - Sampling rate - 8 - KHz - ADC Characteristics * Signal to Distortion Ratio - 65 - dB 0dB Input : Linear Offset Error - - ±20 mV - Input Voltage Range - 1.6 - Vpp - DAC Characteristics * Signal to Distortion Ratio - 65 - dB 0dB Input : Linear Offset Error - - ±20 mV - Output Voltage Range - 1.6 3.2 - Vpp Vpp Differential SEC ASIC 4 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Power Supply Power consumption (Operating Mode) Analog Digital 6.5 0.5 Power consumption (Power down mode) 50 - mA mA No load - uA TRANS-MISSION CHARACTERISTICS (Measurement Bandwidth is 60Hz~4KHz. Full scale, FS=8KHz, @AVDD25A1=2.5V, AVDD25A2=2.5V, AVDD25D=2.5V Ta=55ºC,,Unless otherwise specified.) Characteristics Test Condition Min Typ Max Unit Transmit Gain Variation with Frequency Relative to 1000Hz f = 60Hz f = 200Hz f = 300Hz f = 400Hz ~ 3000Hz f = 3400Hz] f = 4000Hz f = 8000Hz - - -7.9 -1.5 -0.6 -0.2 -1.1 -17.8 -62.8 dB dB dB dB dB dB dB Receive Gain Variation with Frequency Relative to 1000Hz f = 60Hz f = 200Hz f = 300Hz f = 400Hz ~ 3000Hz f = 3400Hz] f = 4000Hz 0.6 - - -8.2 -1.4 -0.6 -0.2 -0.7 -17.8 dB dB dB dB dB dB Transmit Delay f = 60hz ~ 3000Hz - - 750 us Receive Delay f = 60Hz ~ 3000Hz - - 750 us CONTROL CLOCKS CHARACTERISTICS Symbol Min Typ Max Unit Fmclk - 2.048 - MHz McDuty - 50:50 - % FS Frequency Fsync - 8 - KHz MCLK Falling and FS SetUp TsuI 10 - - ns MCLK Falling and FS Hold ThdI 10 - - ns Tdsdout - - 10 ns MCLK Falling and SIN SetUp Tsusin 10 - - ns MCLK Falling and SIN Hold Thdsin 10 - - ns WR Rising and A[8:0] SetUp Tsuwra 20 - - ns WR Rising and A[8:0] Hold Thdwra 20 - - ns WR Rising and DIN[7:0] SetUp Tsuwrd 10 - - ns WR Rising and DIN[7:0] Hold Thdwrd 10 - - ns RD Falling and A[8:0] SetUp Tsurda 10 - - ns RD Rising and A[8:0] Hold Thdrda 20 - - ns RD Falling and DOUT[8:0] Delay Tdrdf - - 10 ns RD Rising and DOUT[8:0] Delay Tdrdr - - 10 ns Characteristics MCLK Frequency MCLK Duty Cycle (H/L) MCLK Rising and SOUT Delay SEC ASIC 5 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Timing Diagram Serial Data Interface Fmclk MCLK Tsui Thdi "H" McDuty "L" FS Tdsdout SOUT LSBit MSBit Serial Output Format Fmclk MCLK Tsui Thdi "H" McDuty "L" FS Tsusin SIN Thdsin LSBit MSBit Serial Input Format Control Register Interface PORSB(High) CSB (Low) WRB A[8:0] Tsuwra Thdwra DIN[7:0] Tsuwrd Thdwrd Write Mode Note : Of the data written on the registers, the control signals(OSS, STEN, RGN) for Tx path are assigned at the rising edge of the internal signal RXZC. PORSB (High) (Low) CSB RDB A[8:0] Tsurda Thdrda DOUT[7:0] Tdrdf Tdrdr Read Mode SEC ASIC 6 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Programmable Functions Control Register Mapping Table ADDRESS DATA[7:0] FUNCTION A[8:0] 7 6 5 4 3 2 1 0 0D0h Status X X X X X X X INIT 0D1h Power Management X X X X X PW[2] PW[1] PW[0] 0D2h Path Select ISS[1] ISS[0] STEN OSS[1] OSS[0] REN X X 0D3h Mic Volume T20DB X X X TGN[3] TGN[2] TGN[1] TGN[0] 0D4h Speaker Volume X X X X RGN[3] RGN[2] RGN[1] RGN[0] 0D5h Sidetone Volume X X X X SGN[3] SGN[2] SGN[1] SGN[0] 0D6h Miscellaneous X X X X X X CALDIS DLB 0D7h Test Path X TLBM DIBYP MOBYP AMOPI ABYP ALBM DLBM Status Register (0D0H); Read Only 7 6 5 4 3 2 1 0 X X X X X X X INIT FUNCTION 0 Under Initializing 1 Initialize Done Power Management (0D1H) 7 6 5 4 3 2 1 0 X X X X X PW[2] PW[1] PW[0] 0 0 0 0 0 1 Standby Mode 0 1 0 Rx Power Up, Tx Power Down 0 1 1 Tx Power Up, Rx Power Down 1 x x All Power Up FUNCTION All Power Down (*) Path Selection (0D2H) 7 6 5 4 3 2 1 0 ISS[1] ISS[0] STEN OSS[1] OSS[0] REN X X 0 0 1 1 0 1 0 1 All Muted (*) MIC1P, MIC1N Selected MIC2P, MICT2N Selected MIC3 Selected 0 1 Sidetone Disabled (*) Side Tone Enabled 0 1 0 0 1 1 SEC ASIC FUNCTION Receive path Disaable (*) Receive path Enable 0 1 0 1 All Muted (*) AOUT1P, AOUT1N Selected AOUT2P, AOUT2N Selected AOUT3 Selected 7 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Mic volume control register (0D3H) 7 6 5 4 T20DB X X X 3 2 1 0 TGN[3] TGN[2] TGN[1] TGN[0] 0 FUNCTION 0dB Selected (*) 1 20dB Selected 0 0 0 0 0dB Selected (*) 0 0 0 1 1.5dB Selected - - - - - 1 1 1 1 22.5dB Selected 1 0 Speaker Volume Control Register (0D4H) 7 6 5 4 X X X X 3 2 RGN[3] RGN[2] RGN[1] RGN[0] FUNCTION 0 0 0 0 0dB Selected (*) 0 0 0 1 -2dB Selected - - - - - 1 1 1 1 -30dB Selected Sidetone Volume Control Register (0D5H) 7 6 5 4 3 2 1 0 X X X X SGN[3] SGN[2] SGN[1] SGN[0] 0 0 0 0 -12.5dB Selected (*) 0 0 0 1 -13.5dB Selected - - - - - 1 1 1 1 -27.5dB Selected FUNCTION Miscellaneous Control Register (0D6H) 7 6 5 4 3 2 1 0 X X X X X X CALDIS DBYP FUNCTION 0 Calibration Function Enabled (*) 1 Calibration Function Disabled 0 Serial Data Loop Back Disabled (*) 1 Serial Data Loop Back Enabled Test Mode Control Register (0D7H) 7 X 6 TLBM 5 DIBYP 4 MOBY P 3 2 AMOPI ABYP 1 0 ALBM DLBM FUNCTION 0 ADC/DAC Loop Mode disabled (*) 1 ADC/DAC Loop Mode enabled 0 Digital Decimator Filter Input Bypass Disabled (*) 1 Digital Decimator Filter Input Bypass Enabled SEC ASIC 8 / 13 ANALOG Voice Band Signal Interface cod0413x_pci 0 Digital Modulator Output Bypass Disabled (*) 1 Digital Modulator Ourput Bypass Enabled 0 Analog Moulator Output / Postfilter Input Bypass Disabled (*) 1 Analog Moulator Output / Postfilter Input Bypass Enabled (*) Analog Bypass Disabled (*) 0 1 Analog Bypass Enabled 0 Analog Loop Back Disabled (*) 1 Analog Loop Back Enabled 0 Digital Loop Back Disabled (*) 1 Digital Loop Back Enabled Power Down/Up Management Guide cod0413x_pci is capable of operating at required power when no activity is required. The State of power down/up is controlled by the Power Management Register(0D1H). Rx Power Up Tx Power Down All Power Down Normal Operation (All Power Up) Standby Mode Tx Power Up Rx power Down The above figure illustrates one example procedure a complete power down/up of cod0413x_pci. From normal operation sequential writes to the Power Management Register are preformed to power down/up cod0413x_pci a piece at a time Layout Guide REFERENCE VOLTAGE & POWER LINE CONNECTION CHIP VCOMR VREFPR VCOMDR VREF VCOMDT VREFPT VCOMT Lead Frame VREF SEC ASIC 9 / 13 ANALOG Voice Band Signal Interface cod0413x_pci AVDD25A1(W=20um) AVDD25A2(W=20um) AVDD25A3(W=10um) AVDD25A4(W=10um) AVDD25A1 Lead Frame AVSS25A1 Lead Frame AVDD25A5(W=20um) AVDD25A8(W=9um AVSS25A1(W=20um) AVSS25A2(W=20um) AVSS25A3(W=10um) AVSS25A4(W=10um) AVSS25A5(W=20um) AVSS25A8(W=9um) VABB(W=10um) VREFMT(W=2.4um) VREFMR(W=2.2um) AVDD25A7(W=45um) AVDD25A2 Lead Frame AVSS25A7(W=45um) AVSS25A2 Lead Frame AVDD25D(W=10um) Lead Frame AVDD25A6(W=10um) AVDD25D AVSS25D(W=10um) Lead Frame AVSS25A6(W=10um) AVSS25D SEC ASIC 10 / 13 ANALOG Voice Band Signal Interface cod0413x_pci Phantom cell AVSS25A2 VABB AVDD25A2 AVDD25A7 AVSS25A7 VABB AVSS25D AVDD25D Pin Name Pin Usage AVDD25A6 External AVSS25A6 External AVDD25A7 External AVSS25A7 External AVDD25A8 External AOUT2N AVSS25A8 External WRB AOUT2P AVDD25D External RDB AOUT3 AVSS25D External VCOMR VABB External CSB AOUT1N A[8:0] AOUT1P DIN[7:0] MIC1P External MIC1N External VREFMR MIC2P External VREFPR MIC2N External IREF DOUT[7:0] PORSB VCOMDR cod0413x_pci 14b 8k voice codec SIN SOUT AOUT1P External - Do not overlap with digtal lines. External - Maintain the shotest path to pads. VREF AOUT1N External AVDD25A4 AOUT2P External AOUT2N External AOUT3 External VREF External VCOMDR External VCOMDT External VCOMR External VCOMT VCOMDT VREFPT VREFMT VCOMT VREFPR External - Maintain the larger width and the shorter length as far as the pads. External - Separate from all other digital lines. MIC2P VREFPT External MIC1P VREFMR External MIC1N VREFMT External MIC2N IREF External SOUT External/ Internal SIN External/ Internal MCLK External/ Internal FS External/ Internal PORSB External/ Internal CSB External/ Internal WRB External/ Internal RDB External/ Internal A[8:0] External/ Internal DIN[7:0] External/ Internal DOUT[7:0] External/ Internal MIC3 FS External AVSS25A2 External AVDD25A3 External AVSS25A3 External AVDD25A4 External AVSS25A4 External AVDD25A5 External AVSS25A5 External VABB AVDD25A2 AVSS25A1 External AVSS25A5 AVSS25A1 AVDD25A1 External AVDD25A5 Pin Layout Guide Usage AVDD25A1 AVSS25A6 Pin Name VABB AVDD25A6 AVSS25A8 AVDD25A8 AVDD25D AVSS25D VABB MCLK Pin - Maintain the large width of lines as far as the pads. - Place the port positions to minimize the length of power lines. - Do not merge the analog powers with anoter power from other blocks. - Use good power and ground source on board. SEC ASIC - Maintain the large width of lines as far as the pads. - Place the port positions to minimize the length of power lines. - Do not merge the analog powers with anoter power from other blocks. - Use good power and ground source on board. AVSS25A4 AVDD25A3 AVSS25A3 MIC3 Pin Layout Guide 11 / 13 - Separate from all other analog signals ANALOG Voice Band Signal Interface cod0413x_pci CORE EVALUATION GUIDE 2.5V 2.5V Cc + Ct Cc + Ct AVSS25A1 AVDD25A1AVSS25A2 AVDD25A2 DOUT[7:0] MIC1P MIC1N SOUT SIN MIC2P MIC2N MCLK FS MIC3 PORSB MAIN PATH CSB AOUT1P WRB AOUT1N RDB AOUT2P A[8:0] AOUT2N C1 MIC C1 MIC C1 MIC SPEAKER SPEAKER AOUT3 DIN[7:0] SPEAKER IREF cod0413x_pci VREF AVSS25D AVDD25D Cc Cc Ct Ct + SELECT 2.5V TEST PATH LOCATION DESCRIPTION Ct 0.1uF TANTALUM CAPACITOR Cc 10uF CERAMIC CAPACITOR C1 0.47uF CERAMIC CAPACITOR R1 32Ω RESISTOR <The Connection User Guide Line for Embedded Core Test> NOTES 1. If SOUT is externally shorted with SIN, The CODEC is achieved to loop-back test mode(ADC->DAC). 2. If end users want to test CODEC in integrated chip, The above pin must be extracted to the PAD. 3. The analog power/ground must be separated from digital power/ground. 4. Power typical value : AVDD25A1 = AVDD25A2 =AVDD25D= 2.5V, AVSS25A1 = AVSS25A2 =AVSS25D= 0.0V SEC ASIC 12 / 13 ANALOG Voice Band Signal Interface cod0413x_pci FEEDBACK REQUEST It should be quite helpful to our CODEC core development if you specify your system requirements on CODEC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Could you explain external/internal pin configurations as required? Specially requested function list : 1. What is your signal band to use, 3.6KHz? 4KHz? or 4.8KHz? 2. What is your analog in/output signal voltage swing? and what kind of format do your want as analog signal in/ouput: single or differential format? If you can, Please let us know, what is your exact in/output signal spec. 3. What is your minimum S/N+D spec? 4. Do you want linear phase characteristic or you don't care on digital filter spec? 5. Could you give us exact design spec of speech codec? (For example, A-law, u-law and so on.) SEC ASIC 13 / 13 ANALOG Voice Band Signal Interface cod0413x_pci HISTORY CARD Version Ver 1.0 Ver 1.1 Modified Items Date Comments '99.Nov. 1.Original version published '00.Feb 1.REN signal (Path Selection) added 2.Power Grouping information AVDD25A1 : AVDD25A1,AVDD25A2,AVDD25A3,AVDD25A4, AVDD25A5,AVDD25A6,AVDD25A8 AVDD25A2 : AVDD25A7 AVDD25D : AVDD25D AVSS25A1 : AVSS25A1,AVSS25A2,AVSS25A3,AVSS25A4, AVSS25A5,AVSS25A6,AVSS25A8,VABB AVSS25A2 : AVSS25A7 AVSS25D : AVSS25D 1. Add Codec Bulk VABB to Pin List 2. Connect AVDD25A6, AVDD25D to Glue Logic Power. Ver 1.2 '00.Mar Connect AVSS25A6, AVSS25D to Glue Logic Ground. 3. Add ADC1255X_PCI Digital/IO Power/GND Connection Information to Layout Guide Ver 1.3 '00.Jul Ver 1.4 '02 Apr 1. Layout Guide Changed - Analog Power(AVDD25A1) is not shared with ADC analog Power - Digital Power(AVDD25D) Pin, Digital Ground(AVSS25D) Pin added 1. Phantom cell added SEC ASIC ANALOG