ETC CS5132/D

CS5132
CS5132
Dual Output CPU Buck Controller
Description
Features
CS5132 dual output provides the
industry’s most highly integrated
solution, minimizing external component count, total solution size,
and cost.
The CS5132 is specifically designed
to power Intel’s Pentium® II processor and includes the following
features: 5 bit DAC and fixed
1.23V reference, Power-Good output, hiccup mode overcurrent protection, adaptive voltage positioning, and overvoltage protection.
The CS5132 will operate over an
8.4V to 14V range and is available
in 24 lead surface mount package.
The CS5132 is a dual output CPU
power supply controller. It contains a synchronous dual NFET
buck controller utilizing the V2TM
control method to achieve the
fastest possible transient response
and best overall regulation. The
CS5132 also contains a second nonsynchronous NFET buck controller. These synchronous and
non-synchronous buck regulators
are designed to power the core and
I/O logic of the latest high performance CPUs. The CS5132 incorporates many additional features
required to ensure the proper
operation and protection of the
CPU and power system. The
Application Diagram
C6-C11
1200µF x 6
10V
C3-C5
20
1200µF x 3
10V
23
FS70VSJ-03
16
VID2
GATE(H)
Q3
PCB TRACE
(FreeCurrent
Sensing Element)
FS70VSJ-03
L2
VID3
3
17
Q2
COMP2
6.6mΩ
C12
0.1µF
C22
100pF
GATE
51Ω
R1
510Ω
10K
VFFB2
12
MBRD835L
C18-C21
11
D1
1200µF
10V
x4
14
PWRGD
0.1µF
LGnd
9
COFF1
5
4
PGnd
C15
680pF
C14
0.1µF
5 bit DAC with 1% Tolerance
■
Hiccup Mode Overcurrent
Protection
■
65ns adaptive FET Non-Overlap
Time
■
Non-Synchronous Switching
Regulator Controller (VI/O)
■
Single N-Channel MOSFET
buck design
■
Adjustable Output with 2%
Tolerance
■
System Power Management
Power-Good Output
Monitors VCORE Switching
Regulator Output
0.01µF
100Ω
R10
2K
1%
VID2
1
24
VID1
VID3
2
23
VID0
VID4
3
22
PWRGD
COFF1
4
21
OVP
COMP1
5
20
VCC1
VOUT1
6
19
GATEL
VFB1
7
18
PGND
VFFB1
8
17
GATEH
LGND
9
16
VCC2
VFFB2
10
15
GATE
VFB2
11
14
COFF2
VOUT2
12
13
COMP2
R9
18
R3
R4
1.18K
1%
200ns Transient Loop Response
■
Control Topology
24L SO Wide
21
OVP
■
TM
C13
0.1µF
22
COMP1
7 VFB1
R6
510Ω
COFF2
V2
8
VOUT1
VFB2
■
Package Options
R8
6
VOUT2
C17
R2
510Ω
VFFB1
Dual N-Channel MOSFET
Synchronous Buck Design
R5
510Ω
R7
10
3.5µH
■
OVP Signal Monitors VCORE
Switching Regulator Output
FS70VSJ-03
GATE(L)
VID4
15
VCC(CORE)
1200µF x 8
10V
13
2
C23-C30
1.2µH
19
1
3.3mΩ
L1
VID0 VCC1 VCC2
24 VID1
+3.3V (VI/O)
PCB TRACE (Free
Current Sensing
Element)
Q1
C1
1µF
C2
1µF
+5V
Synchronous Switching
Regulator Controller (VCORE)
Pentium® II System VCORE
and VI/O Controlled by
a Single IC
+5V
+12V
+12V
■
10K
C25
C16
390pF
5V/12V to 2V/16A for Pentium®II VCC(CORE) , 5V/12V to 3.3V/8A for VI/O
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885–3600 Fax: (401)885–5786
N. American Technical Support: 800-282-9855
Web Site: www.cherry–semi.com
June, 1999 - Rev. 2
1
CS5132
Absolute Maximum Ratings
Pin Symbol
VMAX
Pin Name
VMIN
ISOURCE
ISINK
VCC1
IC Logic and Low Side Driver Power Input
16V
-0.3V
N/A
VCC2
IC High Side Drivers Power Input
16V
-0.3V
N/A
COMP1, COMP2
Compensation Pins for the VCORE
and VI/O error amplifiers.
6V
-0.3V
1mA
1.5A Peak
200mA DC
3A Peak
400mA DC
5mA
6V
-0.3V
1mA
1mA
VFB1, VOUT1, VID0-4, VCORE Voltage Feedback Input Pin,
VOUT2, VFB2, VFFB1, VCORE Output Voltage Sense Pin,
VFFB2
Voltage ID DAC Input Pins, VI/O Output Voltage
Sense Pin, VI/O Voltage Feedback Input Pin,
VCORE PWM comparator Fast Feedback Pin, VI/O
PWM comparator Fast Feedback Pin.
COFF1, COFF2
Off-Time Pins for the VCORE and VI/O regulators
6V
-0.3V
1mA
50mA
GATE(H), GATE
High-Side FET Drivers for the VCORE
and VI/O regulators.
16V
-0.3V
1.5A Peak
200mA DC
1.5A Peak
200mA DC
GATE(L)
Low-Side FET Driver
16V
-0.3V
PWRGD
Power-Good Output
6V
-0.3V
1.5A Peak
200mA DC
1mA
1.5A Peak
200mA DC
30mA
OVP
Overvoltage Protection
15V
-0.3V
30mA
1mA
PGnd
Power Ground
0V
0V
3A Peak
400mA DC
N/A
LGnd
Logic Ground
0V
0V
40mA
N/A
Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 125°C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 183°C, 230°C Peak
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
23,24,1,2,3
VIDO – VID4
20
VCC1
17
18
19
16
GATE(H)
PGnd
GATE(L)
VCC2
15
21
GATE
OVP
22
PWRGD
FUNCTION
Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if
left open. VID4 selects the DAC range. When VID4 is high (logic one),
the Error Amp reference range is 2.125V to 3.525V with 100mV increments. When VID4 is low (logic zero), the Error amp reference voltage
is 1.325V to 2.075V with 50mV increments.
Input power supply pin for the internal circuitry, and low side gate
driver. Decouple with filter capacitor to PGnd.
High side switch FET driver pin for VCORE section.
Power ground for VCORE and VI/O section.
Low side synchronous FET driver pin.
Input power supply pin for on-board high side gate drivers. Decouple
with filter capacitor to PGnd.
High side switch FET driver pin for VI/O section.
Overvoltage protection pin. Goes high when overvoltage condition is
detected on VFB1.
Power-Good Output. Open collector output drives low when VFB1 is
out of regulation.
2
CS5132
Package Pin Description: continued
PACKAGE PIN #
PIN SYMBOL
14
COFF2
13
COMP2
12
11
10
VOUT2
VFB2
VFFB2
9
7
LGnd
VFB1
6
5
VOUT1
COMP1
4
COFF1
8
VFFB1
FUNCTION
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the non-synchronous regulator (VI/O).
VI/O section error amp output. PWM comparator inverting input. A
capacitor to LGnd provides error amp compensation.
VI/O section current limit comparator inverting input.
VI/O section error amp inverting feedback input.
VI/O PWM comparator fast feedback non-inverting input. VI/O section current limit comparator non-inverting input.
Logic ground.
VCORE section error amp inverting input, PWRGD and OVP comparator input.
VCORE section current limit comparator inverting input.
VCORE section error amp output. VCORE section PWM comparator
inverting input. A capacitor to LGnd provides error amp compensation.
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets the off
time for the synchronous regulator (VCORE).
VCORE section PWM comparator fast feedback non-inverting input.
VCORE section current limit comparator non-inverting input.
Block Diagram
VFFB1
COMP1
COFF1
- +
1.06V
VFB1
PWM
COMP1
+
+
+
EA1
Current
Limit1
-
PGnd
Non-overlap
Logic
Q
Fault
Latch1
+
- 0.25V
GATE(H)
Off Time1
One Shot
Discharge
Comparator
+
-
VID0
VID1
VID2
VID3
VID4
UVLO
R
- +
VCC2
-
86mV
VOUT1
VCC1
GATE(L)
S
DAC
PGnd
COFF2
-
PWM
COMP2
GATE
+
+
Off Time2
One Shot
1.10V
-
PGnd
+ -
VFFB2
VFB2
+
+
EA2
+
- 0.25V
+
Discharge
Comparator
86mV
Q
+
- 1.23V
PWRGD
-
R
Fault
Latch2
VCC1
Current
Limit2
S
OVP
COMP2
LGnd
3
PGnd
+
+ -
VOUT2
CS5132
Electrical Characteristics: 0°C < TA < 70°C; 0°C < TJ < 125°C; VOUT2 ≤ 3.5V, 9V ≤ VCC1 ≤ 14V, 9V ≤ VCC2 ≤ 14V; 2.0V DAC Code
(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
■ VCORE Switching Regulator Error Amplifier
VFB1 Bias Current
VFB1 = 0V
COMP1 Source Current
COMP1 = 1.2V to 3.6V; VFB1 = 1.9 V
COMP1 Sink Current
COMP1=1.2V; VFB1 =2.1V;
Open Loop Gain
CCOMP1 = 0.1µF
Unity Gain Bandwidth
CCOMP1 = 0.1µF
PSRR @ 1kHz
CCOMP1 = 0.1µF
■ Voltage Identification DAC
Accuracy (all codes)
VID4 VID3 VID2 VID1 VID0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
Line Regulation
Input Threshold
Measure VFB1 = COMP1,
25°C ≤ TJ≤ 125°C, VCC1 = VCC2 = 12V
MIN
TYP
MAX
UNIT
-1.0
15
30
0.1
30
60
80
20
70
1.0
60
120
µA
µA
µA
dB
kHz
dB
-1.0
3.489
3.390
3.291
3.192
3.093
2.994
2.895
2.796
2.697
2.598
2.499
2.400
2.301
2.202
2.103
2.054
2.004
1.955
1.905
1.856
1.806
1.757
1.707
1.658
1.608
1.559
1.509
1.460
1.410
1.361
1.311
1.225
9V ≤ VCC1 ≤ 14V
VID4, VID3, VID2, VID1, VID0
4
1.00
1.0
3.525
3.425
3.325
3.225
3.125
3.025
2.925
2.825
2.725
2.625
2.525
2.425
2.325
2.225
2.125
2.075
2.025
1.975
1.925
1.875
1.825
1.775
1.725
1.675
1.625
1.575
1.525
1.475
1.425
1.375
1.325
1.250
0.01
1.25
3.560
3.459
3.358
3.257
3.156
3.055
2.954
2.853
2.752
2.651
2.550
2.449
2.348
2.247
2.146
2.096
2.045
1.995
1.944
1.894
1.843
1.793
1.742
1.692
1.641
1.591
1.540
1.490
1.439
1.389
1.338
1.275
2.40
%
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
%/V
V
PARAMETER
Input Pull-up Resistance
Pull-up Voltage
■ GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pull-down
TEST CONDITIONS
VID4, VID3, VID2, VID1, VID0
MIN
25
5.48
■ PWM Comparator 1
PWM Comparator Offset Voltage 0V ≤ VFFB1 ≤ 3.5V
Transient Response
VFFB1 = 0 to 3.5V
VFFB1 Bias Current
0.2V ≤ VFFB1 ≤ 3.5V
VCOFF1 = 1.5V
VCOFF1 = 1.5V
■ Power-Good Output
PWRGD Sink Current
PWRGD Upper Threshold
PWRGD Lower Threshold
PWRGD Output Low Voltage
VFB1 = 1.7V, VPWRGD = 5V
% of nominal DAC code
% of nominal DAC code
VFB1 = 1.7V, IPWRGD = 500µA
UNIT
100
5.82
kΩ
V
1.2
1.0
40
40
65
65
50
2.1
1.5
80
80
100
100
115
V
V
ns
ns
ns
ns
kΩ
77
0.2
-7.0
100
86
0.25
0.1
800
101
0.3
7.0
2500
mV
V
µA
µA
0.95
1.06
200
0.1
1.18
300
7.0
V
ns
µA
1.0
1.6
550
25
2.3
µs
µA
mA
0.5
5
-12
4
8.5
-8.5
0.2
15
12
-5
0.3
mA
%
%
V
-7.0
■ COFF1
Off-Time
Charge Current
Discharge Current
MAX
50
5.65
Measure VCC1/2 –GATE(L)/(H)
Measure GATE(L)/(H)
1.6V < GATE(H)/(L) < (VCC1/2 – 2.5V)
(VCC1/2 – 2.5V) > GATE(L)/(H) > 1.6V
GATE(H)<2V, GATE(L)>2V
30
GATE(L)<2V, GATE(H)>2V
30
Resistance to PGnd (Note 1)
20
■ VCORE Overcurrent Protection
OVC Comparator Offset Voltage 0V < VOUT1 ≤ 3.5V
Discharge Threshold Voltage
VOUT1 Bias Current
0.2V ≤ VOUT1 ≤ 3.5V
OVC Latch Discharge Current
VCOMP = 1V
TYP
■ Overvoltage Protection (OVP) Output
OVP Source Current
OVP = 1V
OVP Threshold
% of nominal DAC code
OVP Pull-up Voltage
IOVP = 1mA, VCC1 - VOVP
1
5
10
8.5
1.1
25
12
1.5
mA
%
V
■ VI/O Switching Regulator Error Amplifier
VFB2 Bias Current
VFB2 = 0V
COMP2 Source Current
COMP2 = 1.2V to 3.6V; VFB2 = 1V
COMP2 Sink Current
COMP2=1.2V; VFB2=1.4V;
Open Loop Gain
CCOMP2 = 0.1µF
-1.0
15
30
0.1
30
60
80
1.0
60
120
µA
µA
µA
dB
5
CS5132
Electrical Characteristics: 0°C < TA < 70°C; 0°C < TJ < 125°C; VOUT2 ≤ 3.5V, 9V ≤ VCC1 ≤ 14V, 9V ≤ VCC2 ≤ 14V; 2.0V DAC Code
(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.
CS5132
Electrical Characteristics: 0°C < TA < 70°C; 0°C < TJ < 125°C; VOUT2 3.5V, 9V VCC1 14V, 9V VCC2 14V; 2.0V DAC Code
(VID4= VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = CGATE = 3.3nF, COFF = 390pF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
■ VI/O Switching Regulator Error Amplifier continued
Unity Gain Bandwidth
CCOMP2 = 0.1µF
PSRR @ 1kHZ
CCOMP2 = 0.1µF
Reference Voltage
VFB2=COMP2
■ GATE
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Fall Time
GATE pull-down
Measure VCC2 –GATE
Measure GATE
1.6V < GATE < (VCC2 – 2.5V)
(VCC2 – 2.5V) > GATE > 1.6V
Resistance to PGnd
■ VI/O Overcurrent Protection
OVC2 Comparator Offset Voltage 0V < VOUT2 ≤ 3.5V
Discharge Threshold Voltage
VOUT2 Bias Current
0.2V ≤ VOUT2 ≤ 3.5V
OVC2 Latch Discharge Current
■ PWM Comparator 2
PWM Comparator Offset Voltage 0V ≤ VFFB2 ≤ 3.5V
Transient Response
VFFB2 = 0 to 3.5V
VFFB2 Bias Current
0.2V ≤ VFFB2 ≤ 3.5V
■ COFF2
Off-Time
Charge Current
Discharge Current
MIN
6
UNIT
1.205
1.255
KHz
dB
V
20
1.2
1.0
40
40
50
2.1
1.5
80
80
115
V
V
ns
ns
kΩ
77
0.2
-7.0
100
86
0.25
0.1
800
101
0.3
7.0
2500
mV
V
µA
µA
0.99
1.10
200
0.1
1.22
300
7.0
V
ns
µA
1.0
1.6
550
25
2.3
µs
µA
mA
7.9
7.6
0.15
8.4
8.1
0.30
13
6
8.9
8.6
0.60
20
9
V
V
V
mA
mA
VCOFF2 = 1.5V
VCOFF2 = 1.5V
Note 1: Guaranteed by design, not 100% tested in production.
MAX
20
70
1.230
-7.0
■ General Electrical Specifications
VCC Monitor Start Threshold
All Outputs On
All Outputs Off
VCC Monitor Stop Threshold
Hysteresis
Start - Stop
VCC1 Supply Current
No Load on GATE(L)
VCC2 Supply Current
No Loads on GATE(H) and GATE
TYP
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the
error signal for a deviation in load. The V2TM method of
control maintains a fixed error signal for both line and load
variation, since the ramp signal is affected by both line and
load.
Theory Of Operation
V2TM Control Method
The V2TM method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
PWM
Comparator
Constant Off-Time
To minimize transient response, the CS5132 uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
COFF capacitor. Every time the VFFB pin exceeds the COMP
pin voltage an Off-Time is initiated. To maintain regulation, the V2TM Control Loop varies switch On-Time. The
PWM comparator monitors the output voltage ramp, and
terminates the switch On-Time.
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient conditions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients.
+
GATE(H)
C
GATE(L)
–
VFFB
Ramp Signal
Output
Voltage
Feedback
VFB
Error
Amplifier
COMP
Error
Signal
–
E
+
Reference
Voltage
Figure 1: V2TM Control Diagram.
The V2TM control method is illustrated in Figure 1. The output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2TM
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2TM control scheme has the
same advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effectively filtered.
Programmable Output
The CS5132 is designed to provide two methods for programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.125V to 3.525V in 100mV steps, the second is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS5132
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The
CS5132 is specifically designed to meet or exceed Intel’s
Pentium® II specifications.
Error Amplifier
An inherent benefit of the V2TM control topology is that
there is no large bandwidth requirement on the error
amplifier design. The reaction time to an output load step
has no relation to the crossover frequency, since transient
response is handled by the ramp signal loop. The main
purpose of this”slow”feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the
error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered. The COMP
pin is the output of the error amplifier and a capacitor to
LGnd compensates the error amplifier loop. Additionally,
through the built-in offset on the PWM Comparator noninverting input, the COMP pin provides the hiccup timing
for the Over-Current Protection, the soft start function that
7
CS5132
Application Information
CS5132
Application Information: continued
the 1.06V PWM comparator offset, the regulator output will
softstart normally (see Figure 5).
Because the start-up circuitry depends on the current sense
function, a current sense resistor should always be used.
minimizes inrush currents during regulator power-up, and
switcher output enable.
Start-up
The CS5132 provides a controlled start-up of regulator output voltage and features Programmable Soft Start implemented through the Error Amp and external Compensation
Capacitor. This feature, combined with overcurrent protection, prevents stress to the regulator power components
and overshoot of the output voltage during start-up.
As Power is applied to the regulator, the CS5132
Undervoltage Lockout circuit (UVL) monitors the ICs supply voltage (VCC) which is typically connected to the +12V
output of the AC-DC power supply. The UVL circuit prevents the NFET gates from being activated until VCC
exceeds the 8.4V (typ) threshold. Hysteresis of 300mV (typ)
is provided for noise immunity. The Error Amp Capacitor
connected to the COMP pin is charged by a 30µA current
source. This capacitor must be charged to 1.06V (typ) so
that it exceeds the PWM comparator’s offset before the V2
PWM control loop will permit switching to occur.
When VCC has exceeded 8.4V and COMP has charged to
1.06V, the upper Gate driver (GATE(H)) is activated, turning on the upper FET. This causes current to flow through
the output inductor and into the output capacitors and load
according to the following equation:
Start-up @
VCC > 8.4V
Figure 2: Normal Start-up (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
T
L
GATE(H) and the upper NFET remain on and inductor current ramps up until the initial pulse is terminated by either
the PWM control loop or the overcurrent protection. This
initial pulse of in-rush current minimizes start-up time, but
does not overstress the regulator’s power components.
The PWM comparator will terminate the initial pulse if the
regulator output exceeds the voltage on the COMP pin
minus the 1.06V PWM comparator offset prior to the drop
across the current sense resistor exceeding the current limit
threshold. In this case, the PWM control loop has achieved
regulation and the initial pulse is then followed by a constant off time as programmed by the COFF capacitor. The
COMP capacitor will continue to slowly charge and regulator output voltage will follow it, less the 1.06V PWM offset,
until it achieves the voltage programmed by the DAC’s VID
input. The Error Amp will then source or sink current to the
COMP cap as required to maintain the correct regulator DC
output voltage. Since the rate of increase of the COMP pin
voltage is typically set much slower than the regulator’s
slew capability, inrush current, output voltage, and duty
cycle all gradually increase from zero. (See Figures 2, 3,
and 4.)
If the voltage across the Current Sense resistor generates a
voltage difference between the VFFB and VOUT pins that
exceeds the OVC Comparator Offset Voltage (86mV typical), the Fault latch is set. This causes the COMP pin to be
quickly discharged, turning off GATE(H) and the upper
NFET since the voltage on the COMP pin is now less than
the 1.06V PWM comparator offset. The Fault latch is reset
when the voltage on the COMP decreases below the
Discharge threshold voltage (0.25V typical). The COMP
capacitor will again begin to charge, and when it exceeds
I = (VIN – VOUT) x
Start-up @
VCC > 8.4V
Initial Pulse until VOUT
> COMP - PWM Offset
Figure 3: Normal Start-up showing initial pulse followed by Soft Start
(20µs/div).
Channel 1 - Regulator Output Voltage (0.2V/div)
Channel 2 – Inductor Switching Node (5V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
8
ILIM = Current Limit Threshold;
ILOAD = Load Current during start-up;
COUT = Total Output Capacitance.
CS5132
Application Information: continued
Normal Operation
During Normal operation, Switch Off-Time is constant and
set by the COFF capacitor. Switch On-Time is adjusted by
the V2TM Control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line.
Output voltage ripple will be determined by inductor ripple current and the ESR of the output capacitors
Duty Cycle = VOUT / VIN
0.27V / 3.54V = 7% ≈ 5.2%
Transient Response
The CS5132 V2TM Control Loop’s 200ns reaction time provides unprecedented transient response to changes in input
voltage or output current. Pulse-by-pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.
Overall load transient response is further improved through
a feature called “Adaptive Voltage Positioning”. This technique pre-positions the output voltage to reduce total output voltage excursions during changes in load.
Holding tolerance to 1% allows the error amplifiers reference voltage to be targeted +25mV high without compromising DC accuracy. A “Droop Resistor”, implemented
through a PC board trace, connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries
the output current. With no load, there is no DC drop
across this resistor, producing an output voltage tracking
the Error amps, including the +25mV offset. When the full
load current is delivered, a 50mV drop is developed across
this resistor. This results in output voltage being offset 25mV low.
The result of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching
the output voltage specification limits. When load current
suddenly increases from its minimum level, the output is
pre-positioned +25mV. Conversely, when load current suddenly decreases from its maximum level, the output is prepositioned -25mV. For best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used.
Figure 4: Pulse-by-Pulse Regulation during Soft Start (2µs/div).
Channel 1 - Regulator Output Voltage (0.2V/div)
Channel 2 – Inductor Switching Node (5V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
OCP @
VCC > 8.5V
Soft Start @
COMP > 1.06V
Figure 5: Start-up with COMP pre-charged to 2V (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
Slope Compensation
The V2TM control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation, the V2TM control loop monitors this ramp signal,
through the PWM comparator, and terminates the switch
on-time.
The stringent load transient requirements of modern microprocessors require the output capacitors to have very low
ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse
width jitter and variation caused by both random or synchronous noise.
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS5132 overcurrent protection. The following equation can be used to
ensure unconditional start-up.
I
ICHG
–I
< LIM LOAD
CCOMP
COUT
where
ICHG = COMP Source Current (30µA typical);
CCOMP = COMP Capacitor value (0.1µF typical);
9
CS5132
Application Information: continued
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
The scheme that prevents that switching noise prematurely
triggers the PWM circuit consists of adding a positive voltage slope to the output of the Error Amplifier (COMP pin)
during an off-time cycle.
The circuit that implements this function for the synchronous regulator section (VCC(CORE)) is shown in Figure 6.
5
COMP1
CCOMP
CS5132
R2
R1
C1
19
GATE(L)
To Synchronous FET
Figure 6: Small RC filter provides the proper voltage ramp at the beginning of each on-time cycle.
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on-time cycle. The resistors R1 and R2 in the circuit of
Figure 6 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier.
A similar approach can be used also for the non-synchronous regulator section (VI/O) as shown in Figure 7. In
this case, the slope compensation signal is generated directly from the GATE output, through the ac coupling capacitor C1, at the beginning of each on-cycle.
It is important that in both circuits, the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) and GATE
pins.
15
To VI/O
Power Switch
GATE
CS5132
R1
13
Protection and Monitoring Features
Over-Current Protection
A loss-less hiccup mode current limit protection feature is
provided, requiring only the COMP capacitor to implement. The CS5132 provides overcurrent protection by sensing the current through a “Droop” resistor, using an internal current sense comparator. The comparator compares
the voltage drop across the “Droop” resistor to an internal
reference voltage of 86mV (typical).
If the voltage drop across the “Droop” resistor exceeds this
threshold, the current sense comparator allows the fault
latch to be set. This causes the regulator to stop switching.
During this over current condition, the CS5132 stays off for
the time it takes the COMP pin capacitor to discharge to its
lower 0.25V threshold. As soon as the COMP pin reaches
0.25V, the Fault latch is reset (no overcurrent condition present) and the COMP pin is charged with a 30µA current
source to a voltage 1.06V greater than the VFFB voltage.
Only at this point the regulator attempts to restart normally. The CS5132 will operate initially with a duty cycle
whose value depends on how low the VFFB voltage was
during the overcurrent condition (whether hiccup mode
was due to excessive current or hard short). This protection
scheme minimizes thermal stress to the regulator components, input power supply, and PC board traces, as the over
current condition persists. Upon removal of the overload,
the fault latch is cleared, allowing normal operation to
resume.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2TM control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 200ns, causing
the top MOSFET to shut off, disconnecting the regulator
from its input voltage. This results in a “crowbar” action to
clamp the output voltage and prevents damage to the load.
The regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low.
Additionally, a dedicated Overvoltage protection (OVP)
output pin (pin 21) is provided in the CS5132. The OVP signal will go high (overvoltage condition), if the output voltage (VCC(CORE)) exceeds the regulation voltage by 8.5% of
the voltage set by the particular DAC code. The OVP pin
can source up to 25mA of current that can be used to drive
an SCR to crowbar the power supply.
COMP2
CCOMP2
C1
R2
Figure 7: Slope compensation for the non-synchronous regulator section
(VI/O).
Power-Good Circuit
The Power-Good pin (pin 22) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3V) when the regulator output voltage typically exceeds ± 8.5% of the nominal
output voltage. Maximum output voltage deviation before
Power-Good is pulled low is ± 12%.
Output Enable
On/off control of the regulator outputs can be implemented by pulling the COMP pins low. It is required to pull the
COMP pins below the 1.06V PWM comparator offset voltage in order to disable switching on the GATE drivers.
10
Output Capacitor Discharge During Transient - 10mV
CS5132-based Dual Output
Buck Regulator Design Example
Maximum allowable ESR is:
Step 1: Define Specification
0.08V
15A = 5.3mΩ.
ESR =
Input Voltage from “silver box” power supply
• 5V ±5% for conversion to output voltage
• 12V ±5% for NFET Gate Voltage and circuit bias
The ESR for a 1200µF/10V Sanyo capacitor type GX is
44mΩ per capacitor.
Output Voltages
• 2.0V @ 16A for VCC(CORE)
• [email protected] 8A for VI/O
• 5% Overall Voltage accuracy (load, line, temperature,
ripple)
• 2% DC & 5% AC Voltage Accuracy
• < 2% Output Ripple Voltage
• 15A Load Step @ 20A /µs - VCC(CORE)
• 7A Load Step @ 5A/µs - VI/O
44
Number of Capacitors = 5.3 ≅ 8.
Output voltage deviation due to ESR:
∆V = 15A × 5.5mΩ = 82mV.
Thermal Management
• 0 to 50° C ambient temperature range
• Component junction temperatures within manufacturer’s specified ratings at full load & TA(MAX)
The ESL is calculated from
∆I
−6
ESL = ∆V × ∆t = 0.01V × 1 × 10 = 0.5nH.
20
∆I
It is estimated that a 10 × 12 mm Aluminum Electrolytic
capacitor has approximately 4nH of package inductance. In
this case we have eight (8) capacitors in parallel for a total
capacitor ESL:
Step 2: Determine Output Capacitors
ESL =
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key
specifications for input capacitors are their ripple rating,
while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency
and bulk capacitors placed close to the load will be
required.
)
= 0.5nH.
The change in capacitor voltage during the transient is:
∆VC =
∆I × tTR
COUT
,
where tTR is the output voltage transient response time. We
choose tTR = 6µs:
∆VC =
The voltage transient during the load step is
(
8
∆V = ESL × ∆I = 0.5nH × 20A = 10mV.
1µs
∆t
The load transients have slew rates of up to 20A /µs, while
the voltage drop during a transient must be kept to less
than 100mV. The output capacitors must hold the output
voltage within these limits since the inductor current can
not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR.
∆VOUT = ∆IOUT ×
4nΗ
Output voltage deviation due to ESL:
Step 2a: For the 2V Output (VCC(CORE))
tTR
+ ESR + COUT
20A
,
µs
=
∆t
Components
• Low cost is top priority.
• Surface mount when possible
• Small footprint important
• Component Ratings determined at 80% of Maximum
Load
ESL
∆t
44
8 = 5.5mΩ.
Total ESR =
15A × 6µs
8 × 1200µF
= 9mV.
Total change in output voltage as a result of an increase in
load current of a 15A step with a 20A/µs slew rate is:
,
∆VOUT = ( 82mV + 10mV + 9mV ) = 101mV.
where tTR = output voltage transient response time.
The total change in output voltage is divided as follows:
Step 2b: For the 3.3V Output (VI/O)
ESR - 80mV
The VI/O load transients have slew rates of 5A/µs, while
the voltage drop during a transient must be kept to less
ESL - 10mV
11
CS5132
Application Information: continued
CS5132
Application Information: continued
than ±165mV. Repeating step 2a, we select four (4)
1200µF/10V Sanyo GX output capacitors.
Calculate Inductor Value:
L=
(VIN - VOUT) tTR
∆I
Step 3: Duty Cycle, Switching Frequency, TON & TOFF
Duty Cycle ≈ VOUT / VIN.
∆IL=
Step 3a: Calculate On-Time for 2V Output
=
0.40
200kHz
= 2µs
∆VOUT
Total ESR
IL(PEAK) = IOUT +
- TON = 5µs - 2µs = 3µs.
FSW
Period × (1-D)
=
3980
5µs × 0.6
3980
= 750pF.
0.66
D
TON =
=
= 3.3µs
FSW
200kHz
∆IL=
1
- TON = 5µs – 3.3µs = 1.7µs.
FSW
Select COFF2 to be 390pF.
Step 4: Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade
transient response. There are many factors to consider in
selecting the inductor including: cost, efficiency, EMI and
ease of manufacture. The inductor must be able to handle
the peak current at the switching frequency without saturating, and the copper resistance in the winding should be
kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are: ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. We will use a powdered iron core.
Iron powdered cores are very suitable due to their high saturation flux density and have low loss at high frequencies,
a distributed gap and exhibit very low EMI.
= 7.3A,
L
= 12.4A.
( ∆I2 ) = 16A - ( 7.3A
2 )
L
(VIN - VOUT) × D
FSW × L
=
(5V - 2V) × 0.4
200kHz × 1.2µH
= 5A.
The maximum inductor peak current becomes:
IL(PEAK) = 16A +
5A
= 16A + 2.5A = 18.5A.
2
The inductor valley current becomes:
Calculate Off-Time:
TOFF =
5.5mΩ
The selected 1.2µH inductor yields the following ripple
current:
A standard COFF1 capacitance value of 680pF can be used.
The 3980 factor is a characteristic of the CS5132.
Step 3b: Calculate On-Time for 3.3V Output
40mV
= 19.6A,
( ∆I2 )= 16A + ( 7.3A
2 )
IL(VALLEY) = IOUT -
Select the COFF1 capacitor in order to set the Off-Time:
COFF1 =
=
which corresponds to the following maximum Inductor
Peak and Valley currents:
Calculate Off-Time:
1
=1.2µH.
15A
The maximum allowable Inductor Ripple Current for a 2%
ripple on the 2V output is:
Select 200kHz Switching Frequency (FSW).
TOFF =
3V × 6µs
=
15A
∆VOUT = 2% × 2V = 40mV
D = 3.3V / 5V = 66% for 3.3V output.
D
FSW
(5V-2V) × 6µs
Step 4a: Select 2% Ripple on 2V Output
D = 2.0V / 5V = 40% for 2V output.
TON =
=
IL(VALLEY) = 16A -
5A
= 16A - 2.5A = 13.5A.
2
The above values are well within the maximum allowable
inductor peak and valley currents for a 2% output voltage
ripple.
Select Toroid Powdered Iron Core, low cost, low core losses at 200kHz, low EMI.
Select XFMRS Inc, XF0016-VO4 1.2µH inductor with RDC =
0.003Ω typical, 0.008Ω maximum.
Step 4b: Select 2% Ripple on 3.3V Output
Repeating Step 4a for the 3.3V output, we find 3.5µH is a
suitable value for this output.
Step 5: Input Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines. Key specifications for input capacitors are their ripple rating.
Step 5a: VCC(CORE) Buck Regulator Input Capacitors
The input capacitor CIN should also be able to handle the
12
input RMS current IIN(RMS). CIN discharges during the ontime.
Step 6: Power MOSFETs
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance and 2) Its
very fast switching times. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small
capacitor, which the driving circuit must charge at turn on.
The lower the drive impedance, the higher the rate of rise
of VGS, and the faster the turn- on time. Power dissipation
in the switching MOSFET consists of 1) conduction losses,
2) leakage losses, 3) turn-on switching losses, 4) turn-off
switching losses, and 5) gate-transitions losses. The latter
three losses are proportional to frequency. For the conducting power dissipation rms values of current and resistance
are used for true power calculations.
The fast switching speed of the MOSFET makes it indispensable for high-frequency power supply applications.
Not only are switching power losses minimized, but the
maximum usable switching frequency is considerably
higher. Switching time is independent of temperature.
Also, at higher frequencies, the use of smaller and lighter
components (transformer, filter choke, filter capacitor)
reduces overall component cost while using less space for
more efficient packaging at lower weight.
The MOSFET has purely capacitive input impedance. No
DC current is required. It is important to keep in mind the
drain current of the FET has a negative temperature coefficient. Increase in temperature causes higher on-resistance
and greater leakage current.
For switching circuits, VDS(ON) should be low to minimize
power dissipation at a given ID, and VGS should be high to
accomplish this. MOSFET switching times are determined
by device capacitances, stray capacitances, and the
impedance of the gate drive circuit. Thus the gate driving
circuit must have high momentary peak current sourcing
and sinking capability for switching the MOSFET. The
input capacitance, output capacitance and reverse-transfer
capacitance also increase with increased device current
rating.
Two considerations complicate the task of estimating
switching times. First, since the magnitude of the input
capacitance, CISS, varies with VDS, the RC time constant
determined by the gate-drive impedance and CISS changes
during the switching cycle. Consequently, computation of
the rise time of the gate voltage by using a specific gatedrive impedance and input capacitance yields only a rough
estimate. The second consideration is the effect of the
"Miller" capacitance, CRSS, which is referred to as Cdg in the
following discussion. For example, when a device is on,
VDS is fairly small and VGS is about 12V. Cdg is charged to
VDS(ON) - VGS, which is a negative potential if the drain is
considered the positive electrode. When the drain is "off",
Cdg is charged to quite a different potential. In this case the
voltage across Cdg is a positive value since the potential
from gate-to-source is near zero volts and VDS is essentially
the drain supply voltage. During turn-on and turn-off,
The discharge current is given by:
ICINDISRMS =
(IL(PEAK)2 + (IL(PEAK) × IL(VALLEY)) + IL(VALLEY2) × D = 10.2A.
3
CIN charges during the off-time, the average current
through the capacitor over one switching cycle is zero:
D
ICIN(CH) = ICIN(DIS) ×
ICIN(CH) = 10.2A ×
,
1-D
0.4
= 6.8A.
(1-0.4)
So the total Input RMS current is:
ICIN(RMS) = (ICIN(DIS)2 × D) +(ICIN(CH)2 × (1-D)),
ICIN(RMS) = (10.22 × 0.4) + (6.82 (× 0.6)) = 8.3A .
The number of input capacitors required is given by:
NCIN =
ICIN(RMS)
.
IRIPPLE
For Sanyo capacitors type GX:
1200µF/10V, IRIPPLE = 1.25A.
Hence,
NCIN =
8.3
= 6.6.
1.25
The number of input capacitors can be rounded off to 6.
Calculate the Input Capacitor Ripple Voltage:
VRMS = IRMS × Total ESR = 8.3A × 7.3mΩ = 60mV.
Calculate the Input Capacitor Power Loss:
PCIN = IRMS2 × Total ESR = 0.504W.
Step 5b: VI/O Buck Regulator Input Capacitors
Repeating for the 3.3V output, we select 3 GX 1200µF/10V
capacitors.
13
CS5132
Application Information: continued
CS5132
Application Information: continued
these large swings in gate-to-drain voltage tax the current
sourcing and sinking capabilities of the gate drive. In addition to charging and discharging CGS, the gate drive must
also supply the displacement current required by Cdg
(IGATE = Cdg dVdg/dt). Unless the gate-drive impedance is
very low, the VGS waveform commonly plateaus during
rapid changes in the drain-to-source voltage.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (RDSON), which effects
regulator efficiency and FET thermal management requirements. The On- Resistance determines the amount of current a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the continuous rating, the On-Resistance also increases. Its positive temperature coefficient is between +0.6%/C and
+0.85 %/C. The higher the On-Resistance the larger the
conduction loss is.
Both logic level and standard FETs can be used. The reference designs derive gate drive from the 12V supply which
is generally available in most computer systems and utilizes logic level FETs. Multiple FETs may be paralleled to
reduce losses and improve efficiency and thermal management.
Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail-to-rail due to overshoot caused by the capacitive load they present to the controller IC.
We select Mitsubishi’s FS70VSJ-03 (D2 package):
30V withstand voltage; RDSON = 8mΩ; ΘJA = 40°C/W;
Total Gate Charge = 50nC.
Step 6b: Similar calculations apply for the 3.3V output.
Step 6a: For the 2V Output Upper (Switching) FET
Step 6c: Synchronous FET ( 2V Output)
Calculate the 2V Output’s Maximum RMS Current through
the Switch:
Calculate Switch Conduction Losses:
PSW(ON) =
5V × 16A × 60× 10-9
6 × 5 × 10-6
= 0.16W.
Switch Off Losses:
PSW(OFF) =
VIN × IOUT × TFALL
6T
,
TFALL = 160ns,
(from Mitsubishi FS70VSJ-03 switching characteristics performance curves):
PSW(OFF) =
5V × 16A × 160 × 10-9
= 0.43W.
6 × 5 × 10-6
Upper FET Total Losses = Switching Conduction Losses +
Switch On Losses + Switch Off Losses:
PFETH(TOTAL) = 0.83W + 0.16W + 0.43W = 1.42W.
Calculate Maximum NFET Switch Junction Temperature:
TJ = TA + [(PFETH(TOTAL)) × ΘJA ],
TJ = 50C + (1.412W) × 40°C/W = 107°C.
Calculate the Gate Driver Losses:
PGATE(H) = Q × VGATE × FSW
= 50nC × 12V × 200KHz = 120mW.
PRMS = IRMS2 × RDSON = [IOUT2 × (1-D)] × RDSON
IRMS(H) =
= [16A2 × 0.6] × 8mΩ = 1.22W.
(IL(PEAK)2 + (IL(PEAK) × IL(VALLEY)) + IL(VALLEY2) × D = 10.2A.
3
Calculate Switch Conduction Losses:
PRMS = IRMS2 × RDSON = 10.2A2 × 8mΩ = 0.83W.
The synchronous MOSFET has no switching losses, except
for losses in the internal body diode, because it turns on
into near zero voltage conditions. The MOSFET body diode
will conduct during the non-overlap time and the resulting
power dissipation (neglecting reverse recovery losses) can
be calculated as follows:
Calculate Switching Losses:
Switch On Losses:
PSW(ON) =
(VIN × IOUT × TRISE)
6T
PSW = VSD × ILOAD × non-overlap time
× switching frequency.
,
From the Mitsubishi FS70VSJ-03 source-drain diode forward characteristics curve, VSD = 0.8V:
PSW = 0.8V × 16A × 65ns × 200kHz,
TRISE = 60ns,
PSW = 0.16W.
(from Mitsubishi FS70VSJ-03 switching characteristics performance curves):
1
T=
= 5µs,
FSW
14
Lower (Synchronous) FET Total Losses = Switch Conduction Losses + Body Diode Losses:
PFETL(TOTAL) = 1.27W + 0.16W =1.43W.
Calculate Maximum NFET Switch Junction Temperature:
TJ = TA + [(PFETL(TOTAL) ) × ΘJA ],
where
ID = average drive current;
QGATE(X) = total gate charge for each MOSFET;
FSW1, FSW2 = switching frequencies for the synchronous
and non-synchronous sections respectively.
The power dissipation for the IC when VCC1 = VCC2 =
VCC is:
TJ = 50C + (1.43W) × 40°C/W = 107°C.
Calculate the Gate Driver Losses:
PGATE(L) = Q × VGATE × FSW
= 50nC × 12V × 200KHz = 120mW.
PD = ICC × VCC + ID × VCC,
where
ICC = quiescent supply current of the IC (both from VCC1
and VCC2).
For the design example in question,
PD = 19mA × 12V + 0.12W + 0.12W + 0.12W = 0.59W.
Step 7: Free Wheeling Schottky Diode (3.3V Output)
The four most application-important characteristics of a
Schottky are:
1. Forward voltage drop;
2. Reverse leakage current;
3. Reverse blocking voltage;
4. Maximum permissible junction temperature.
We calculate the average Schottky current:
IAVG = IOUT × (1−D) = 8Α × 0.34 = 2.72Α.
We select the Motorola MBRD835L rated at 8A, with 35V
DC blocking voltage and 0.51Vforward voltage drop.
Neglecting reverse losses, the power dissipation is due to
the conduction loss only and can be computed as follows:
PSCHOTTKY = VF × IAVG,
where
VF = maximum instantaneous forward voltage;
PSCHOTTKY = 0.51V × 2.72Α = 1.39W.
Calculate maximum Schottky junction temperature:
TJ = TA + [(PSCHOTTKY ) × ΘJA ],
TJ = 50C + (1.39W × 80°C/W) = 161°C.
Proper heatsinking (copper pad under Schottky) will be
required to reduce Schottky TJ below +125°C.
Step 8: IC Power Dissipation
The power dissipation on the IC varies with the MOSFETs
used, VCC and the CS5132 operating frequency. This power
dissipation is typically dominated by the average gate
charge current for the MOSFETs. The average current is
approximately:
ID = (QGATE(H) + QGATE(L)) × FSW1 + QGATE × FSW2,
The junction temperature of the IC is primarily a function
of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
“Droop” Resistor for Adaptive Voltage Positioning
and Current Limit
Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the
full load current and should be chosen so that both DC and
AC tolerance limits are met. An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation caused by variation in the thickness of the PCB layer; 2) the mismatch of
L/W; and 3) temperature variation.
1) Sheet Resistivity
For one ounce copper, the thickness variation is typically
1.26 mil to 1.48 mil. Therefore the error due to sheet resistivity is:
1.48 - 1.26
= ±8%.
1.37
2) Mismatch due to L/W
The variation in L/W is governed by variations due to the
PCB manufacturing process. The error due to L/W mismatch is typically 1%.
3) Thermal Considerations
Due to I2 × R power losses the surface temperature of the
droop resistor will increase causing the resistance to
increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the
formula:
R = R20 [1+ α20(Τ−20)],
15
CS5132
Application Information: continued
CS5132
Application Information: continued
where
R20 = resistance at 20°C;
α=
Current Limit
The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current
rating of the external power components as these are the
first to fail during an overload condition. The MOSFET
continuous and pulsed drain current rating at a given case
temperature has to be accounted for when setting the current limit trip point.
Temperature curves on MOSFET manufacturers’ data
sheets allow the designer to determine the MOSFET drain
current at a particular VGS and TJ (junction temperature).
This, in turn, will assist the designer to set a proper current
limit, without causing device breakdown during an overload condition.
For future “CPUs” the full load will be 16A. The internal
current sense comparator current limit voltage limits are:
77mV < VTH < 101mV. Also, there is a 21% total variation
in RSENSE as discussed in the previous section.
We compute the value of the current sensing element
(embedded PCB trace) for the minimum current limit setpoint:
RSENSE(MIN) = RSENSE(TYP) × 0.79,
0.00393
;
°C
T= operating temperature;
R = desired droop resistor value.
For temperature T = 50°C, the % R change = 12%.
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
±8%
Tolerance due to L/W error
1%
Tolerance due to temperature variation
12%
Total tolerance for droop resistor
21%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage at full
load is above the minimum DC tolerance spec:
VDROOP(TYP) =
VDAC(MIN)-VDC(MIN)
1+RDROOP(TOLERANCE)
.
Example: for a 450MHz Pentium ®II, the DC accuracy spec
is 1.93 < VCC(CORE) < 2.07V, and the AC accuracy spec is
1.9V < VCC(CORE) < 2.1V. The CS5132 DAC output voltage is
+2.004V < VDAC < +2.045V. In order not to exceed the DC
accuracy spec, the voltage drop developed across the resistor must be calculated as follows:
VDROOP(TYP) =
=
RSENSE(MAX) = RSENSE(TYP) × 1.21,
RSENSE(MAX) =
We select,
[VDAC(MIN)-VDC (MIN)]
1+RDROOP(TOLERANCE)
+2.004V-1.93V
1.21
VTH(MIN)
77mV
=
= 4.8mΩ.
ICL(MIN)
16A
RSENSE(TYP) = 3.3mΩ.
We calculate the range of load currents that will cause the
internal current sense comparator to detect an overload
condition.
= 61mV.
With the CS5132 DAC accuracy being 1%, the internal error
amplifier’s reference voltage is trimmed so that the output
voltage will be 25mV high at no load. With no load, there is
no DC drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including
the offset. When the full load current is delivered, a drop of
-50mV is developed across the resistor. Therefore, the regulator output is pre-positioned at 25mV above the nominal
output voltage before a load turn-on. The total voltage
drop due to a load step is ∆V-25mV and the deviation from
the nominal output voltage is 25mV smaller than it would
be if there was no droop resistor. Similarly at full load the
regulator output is pre-positioned at 25mV below the nominal voltage before a load turn-off. the total voltage increase
due to a load turn-off is ∆V-25mV and the deviation from
the nominal output voltage is 25mV smaller than it would
be if there was no droop resistor. This is because the output
capacitors are pre-charged to a value that is either 25mV
above the nominal output voltage before a load turn-on or,
25mV below the nominal output voltage before a load turnoff .
Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
16
Nominal Current Limit Setpoint
From the overcurrent detection data in the electrical characteristics table:
VTH(TYP) = 86mV,
ICL(NOM) =
VTH(TYP)
= 86mV = 26A.
RSENSE(NOM)
3.3mΩ
Maximum Current Limit Setpoint
From the overcurrent detection data in the electrical characteristics table:
VTH(MAX) = 101mV,
ICL(MAX)=
=
VTH(MAX)
VTH(MAX)
=
RSENSE(MIN) RSENSE(NOM) × 0.79
101mV
= 38.7A.
3.3mΩ × 0.79
where
R = droop resistor value;
ρ = 0.71786mΩ-mil (1 oz. copper);
L = droop resistor length;
W = droop resistor width.
Therefore, the range of load currents that will cause the
internal current sense comparator to detect an overload
condition through a 3.3mΩ embedded PCB trace is: 19.3A
< ICL < 38.7A, with 26A being the nominal overload condition.
Design Rules for Using a Droop Resistor
The basic equation for laying an embedded resistor is:
RAR = ρ ×
L
A
or R = ρ ×
L
(W × t)
RDROOP = 3.3mΩ.
3.3mΩ = 0.71786mΩ-mil ×
,
where
A= W × t = cross-sectional area;
ρ= the copper resistivity (µΩ-mil);
L= length (mils);
W = width (mils);
t = thickness (mils).
L
.
201 mils × 1.37 mils
Hence, L = 1265 mils = 1.265 in.
In layouts where it is impractical to lay out a droop resistor
in a straight line 1265 mils long, the embedded PCB trace
can be “snaked” to fit within the available space.
Thermal Management
For most PCBs the copper thickness, t, is 35µm (1.37 mils)
for one ounce copper; ρ = 717.86µΩ-mil.
For a CPU load of 16A the resistance needed to create a
50mV drop at full load is:
RDROOP =
Thermal Considerations for Power MOSFETs and Diodes
In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a
maximum of 150°C or lower. The thermal impedance
(junction to ambient) required to meet this requirement can
be calculated as follows:
50mV
50mV
=
= 3.1mΩ.
IOUT
16A
Thermal Impedance =
The resistivity of the copper will drift with the temperature
according to the following guidelines:
∆R = 12% @ TA = +50°C;
∆R = 34% @TA = +100°C.
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
Droop Resistor Length, Width, and Thickness
The minimum width and thickness of the droop resistor
should primarily be determined on the basis of the currentcarrying capacity required, and the maximum permissible
droop resistor temperature rise. PCB manufacturer design
charts can be used in determining current- carrying capacity and sizes of etched copper conductors for various temperature rises above ambient.
For single conductor applications, such as the use of the
droop resistor, PCB design charts show that for a droop
resistor with a required current-carrying capacity of 16A,
and a 45°C temperature rise above ambient, the recommended cross section is 275 mil2.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing
for compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions.
These components are not required for regulator operation
and experimental results may allow them to be eliminated.
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
W × t = 275 mil2,
where
W = droop resistor width;
t = droop resistor thickness.
For 1oz. copper, t= 1.37 mils, therefore W = 201 mils =
0.201 in.
R=ρ×
TJ(MAX) - TA
.
Power
L
,
W×t
17
CS5132
Application Information: continued
CS5132
Application Information: continued
Layout Guidelines
When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure
proper operation of the CS5132.
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
8) Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
9) Place the switching MOSFET as close to the +5V input
capacitors as possible.
10) Place the output capacitors as close to the load
as possible.
11) Place the VFFB,VOUT filter resistors (510Ω) in series with
the VFFB and VOUT pins as close as possible to the pins.
2) Keep high currents out of sensitive ground connections.
Avoid connecting the IC Gnd between the source of the
lower FET and the input capacitor Gnd.
12) Place the COFF and COMP capacitors as close as possible to the COFF and COMP pins.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding.
13) Place the current limit filter capacitors between the
VFFB and VOUT pins, as close as possible to the pins.
4) For high power buck regulators on double-sided PCBs a
single ground plane (usually the bottom) is recommended.
14) Connect the filter components of the following pins:
VFB, VFFB, VOUT, COFF, and COMP to the LGnd pin with a
single trace, and connect this local LGnd trace to the output
capacitor Gnd.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the power and Gnd planes, the top layer
for the high current connections and component vias, and
the bottom layer for the noise sensitive traces.
15) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
16) Place the VCC bypass capacitors as close as possible to
the VCC pins and connect them to PGnd.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
7) The MOSFET gate traces to the IC must be as short,
straight, and wide as possible. Ideally, the IC has to be
placed right next to the MOSFETs.
18
CS5132
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
Thermal Data
RΘJC
typ
RΘJA
typ
D
Lead Count
Metric
Max
Min
15.60 15.20
24L SO Wide
English
Max Min
.614 .598
24L SO Wide
16
80
°C/W
°C/W
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
REF: JEDEC MS-013
0.30 (.012)
0.10 (.004)
Ordering Information
Part Number
CS5132GDW24
CS5132GDWR24
ON Semiconductor and the ON Logo are trademarks of
Semiconductor Components Industries, LLC (SCILLC). ON
Semiconductor reserves the right to make changes without
further notice to any products herein. For additional information and the latest available information, please contact
your local ON Semiconductor representative.
Description
24L SO Wide
24L SO Wide (tape & reel)
19
© Semiconductor Components Industries, LLC, 2000
Notes