ETC CS5307/D

Multiphase controllers provide fast, accurate regulation with the
control features required to power the next generation of processors in
desktop, workstation and server applications. Combined with external
gate drivers and power components, the CS5307 implements a
compact, highly integrated buck converter. Enhanced V2 control
inherently compensates for variations in both line and load. Current
sharing between phases is achieved by Peak Current Sharing.
The CS5307 includes Power Good with a programmable lower
threshold.
Applications include Embedded Processor Power and low
voltage/high current power supplies.
Features
• Switching Regulator Controller
– Lossless Current Sensing
– Enhanced V2 Control Method Provides Excellent Regulation
and Fast Transient Response
– Programmable 200 to 800 kHz Switching Frequency (Per Phase)
– Duty Cycle – 0% to 100%
– Programmable Adaptive Voltage Positioning Reduces Output
Capacitor Requirements
– Programmable Soft Start
• Accurate Current Sharing
• Protection Features
– Pulse–by–Pulse Current Limit for Each Phase
– Programmable Hiccup Overcurrent Protection
– All “1” DAC Code Fault
– Processor Overvoltage Protection through Bottom MOSFETs
– Undervoltage Lockout
• System Power Management
– 5–Bit DAC With 1.0% Tolerance Compatible with VRM 9.0
– Power Good Output
– Programmable Power Good Lower Threshold
– Guaranteed Startup at –20°C
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1
SO–24L
DW SUFFIX
CASE 751E
MARKING DIAGRAM
24
CS5307
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
GND
OCSET
ROSC
CS1
CS2
CS3
CS4
CSREF
VDRP
VFB
COMP
SS
1
24
VCC
GATE1
GATE2
GATE3
GATE4
VID0
VID1
VID2
VID3
VID4
PWRGDS
PWRGD
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2002
July, 2002 – Rev. 8
1
Package
Shipping
CS5307GDW24
SO–24L
30 Units/Rail
CS5307GDWR24
SO–24L
1000 Tape & Reel
Publication Order Number:
CS5307/D
CS5307
5.5 V
DRN
CO
6.2 V
BST
TG
+12 V
PGND
VS
BG
ENABLE
NCP5351
NCP5351
ROSC
GATE2
GATE3
CS2
GATE4
VID0
CSREF
VID1
VID2
VDRP
VID3
SS
VID4
PWRGDS
PWRGD
DRN
VFB
COMP
CO
CS4
BST
TG
CS3
CS5307
CS1
PGND
GATE1
VS
BG
OCSET
ENABLE
DRN
CO
VCC
GND
BST
TG
GND
VS
BG
PGND
DRN
CO
BST
TG
ENABLE
NCP5351
PGND
VID4
VS
BG
ENABLE
NCP5351
PWRGD
VID3
VID2
VID1
VID0
Figure 1. Application Diagram, 12 V to 1.5 V/80 A Four–Phase Converter
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2
VOUT
CS5307
MAXIMUM RATINGS*
Rating
Value
Unit
150
°C
–65 to 150
°C
ESD Susceptibility (Human Body Model)
2.0
kV
Package Thermal Resistance
Junction–to–Case, RθJC
Junction–to–Ambient, RθJA
16
80
°C/W
°C/W
230 peak
°C
Level 1
–
Operating Junction Temperature
Storage Temperature Range
Lead Temperature Soldering: Reflow (Note 1.)
MSL
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Number
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
1
GND
N/A
N/A
0.4 A, 1.0 µs, 100 mA DC
N/A
2
OCSET
7.0 V
–0.3 V
1.0 mA
1.0 mA
3
ROSC
7.0 V
–0.3 V
1.0 mA
1.0 mA
4–7
CS1–CS4
7.0 V
–0.3 V
1.0 mA
1.0 mA
8
CSREF
7.0 V
–0.3 V
1.0 mA
1.0 mA
9
VDRP
7.0 V
–0.3 V
1.0 mA
1.0 mA
10
VFB
7.0 V
–0.3 V
1.0 mA
1.0 mA
11
COMP
7.0 V
–0.3 V
1.0 mA
1.0 mA
12
SS
7.0 V
–0.3 V
1.0 mA
1.0 mA
13
PWRGD
18 V
–0.3 V
1.0 mA
10 mA
14
PWRGDS
7.0 V
–0.3 V
1.0 mA
1.0 mA
15–19
VID4–VID0
18 V
–0.3 V
1.0 mA
1.0 mA
20–23
GATE4–GATE1
7.0 V
–0.3 V
0.1 A, 1.0 µs, 25 mA DC
0.1 A, 1.0 µs, 25 mA DC
24
VCC
18 V
–0.3 V
100 mA
1.0 mA
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3
CS5307
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEx = 100 pF,
CCOMP = 0.01µF, CSS = 0.1µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open or Pull–Up to Internal 3.3 V or External Voltage 12 V)
Connect VFB to COMP,
Measure COMP
Accuracy (all codes)
VID code
–1.0
–
+1.0
%
VID4
VID3
VID2
VID1
VID0
1
1
1
1
1
1
1
1
1
0
1.089
1.100
1.111
V
1
1
1
0
1
1.114
1.125
1.136
V
1
1
1
0
0
1.139
1.150
1.162
V
1
1
0
1
1
1.163
1.175
1.187
V
1
1
0
1
0
1.188
1.200
1.212
V
1
1
0
0
1
1.213
1.225
1.237
V
1
1
0
0
0
1.238
1.250
1.263
V
1
0
1
1
1
1.263
1.275
1.288
V
1
0
1
1
0
1.287
1.300
1.313
V
1
0
1
0
1
1.312
1.325
1.338
V
1
0
1
0
0
1.337
1.350
1.364
V
1
0
0
1
1
1.361
1.375
1.389
V
1
0
0
1
0
1.386
1.400
1.414
V
1
0
0
0
1
1.411
1.425
1.439
V
1
0
0
0
0
1.436
1.450
1.465
V
0
1
1
1
1
1.460
1.475
1.490
V
0
1
1
1
0
1.485
1.500
1.515
V
0
1
1
0
1
1.510
1.525
1.540
V
0
1
1
0
0
1.535
1.550
1.566
V
0
1
0
1
1
1.560
1.575
1.591
V
0
1
0
1
0
1.584
1.600
1.616
V
0
1
0
0
1
1.609
1.625
1.641
V
0
1
0
0
0
1.634
1.650
1.667
V
0
0
1
1
1
1.658
1.675
1.692
V
0
0
1
1
0
1.683
1.700
1.717
V
0
0
1
0
1
1.708
1.725
1.742
V
0
0
1
0
0
1.733
1.750
1.768
V
0
0
0
1
1
1.757
1.775
1.793
V
0
0
0
1
0
1.782
1.800
1.818
V
0
0
0
0
1
1.807
1.825
1.843
V
0
0
0
0
0
1.832
1.850
1.869
V
Fault
Input Threshold
VID4, VID3, VID2, VID1, VID0
1.00
1.25
1.5
V
Input Pull–Up Resistance
0 V < VID4, VID3, VID2,VID1,
VID0 < 3.3 V
25
50
100
kΩ
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4
CS5307
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEx = 100 pF,
CCOMP = 0.01µF, CSS = 0.1µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open or Pull–Up to Internal 3.3 V or External Voltage 12 V) (continued)
1.0 MΩ to GND
2.5
2.7
3.0
V
Upper Threshold
Force PWRGDS
1.876 (–5%)
1.975
2.074 (+5%)
V
Lower Threshold
Force PWRGDS
–5%
VID/2
+5%
V
Switch Leakage Current
VCC = 14 V, PWRGDS = 1.4 V
–
0.1
1.0
µA
Delay
PWRGDS low to PWRGD low
100
800
2000
µs
Output Low Voltage
PWRGDS = 1.0 V,
IPWRGD = 4.0 mA
–
0.15
0.4
V
Pull–Up Voltage
Power Good Output
Voltage Feedback Error Amplifier
VFB Bias Current
Note 2
9.9
10.25
10.6
µA
Comp Source Current
COMP = 0.5 V to 2.0 V,
VFB = 1.8 V, DAC = 00000
15
30
60
µA
Comp Sink Current
COMP = 0.5 V to 2.0 V,
VFB = 1.15 V, DAC = 11110
15
30
60
µA
Transconductance
–10 µA < ICOMP < +10 µA, Note 3
200
500
750
µmho
Output Impedance
–
–
2.5
–
MΩ
45
95
–
dB
Open Loop DC Gain
Note 3
Unity Gain Bandwidth
–
–
50
–
kHZ
PSRR @ 1.0 kHz
–
–
60
–
dB
2.4
2.7
–
V
COMP Max Voltage
VFB = 0 V
COMP Min Voltage
VFB = 1.6 V
–
50
150
mV
Minimum Pulse Width
Measured from CSx to GATEx,
VFB = CSREF = 0.5 V,
COMP = 0.5 V,
60 mV step on CSx;
measure at GATEx = 1.0 V
–
40
70
ns
Transient Response Time
Measured from CSREF to GATEx,
COMP = 2.1 V,
CSx = CSREF = 0.5 V,
CSREF stepped
from 1.2 V – 2.0 V
–
40
60
ns
Channel Start–Up Offset
CSx = CSREF = VFB = 0 V,
measure VCOMP when GATEx
switch high
350
600
750
mV
Artificial Ramp Amplitude
50% Duty Cycle, Note 3
–
115
–
mV
2.0
2.6
3.0
V
–
0.5
0.7
V
PWM Comparators
Gates
High Voltage
Measure GATEx
IGATEx = 1.0 mA
Low Voltage
Measure GATEx, IGATEx = 1.0 mA
2. The VFB Bias Current changes with the value of ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
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5
CS5307
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEx = 100 pF,
CCOMP = 0.01µF, CSS = 0.1µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Gates
Rise Time
0.8 V < GATEx < 2.0 V,
VCC = 10 V
–
5.0
20
ns
Fall Time
2.0 V > GATEx > 0.8 V,
VCC = 10 V
–
5.0
20
ns
Oscillator
Switching Frequency
ROSC = 32.4 kΩ
300
400
500
kHz
Switching Frequency
ROSC = 63.4 kΩ, Note 4
150
200
250
kHz
Switching Frequency
ROSC = 16.2 kΩ, Note 4
600
800
1000
kHz
0.90
1.00
1.10
V
75
90
105
deg
ROSC Voltage
Phase Delay
–
Adaptive Voltage Positioning
VDRP Output Voltage to
DACOUT Offset
CSx = CSREF, VFB = COMP,
Measure VDRP – COMP
–5.0
0
5.0
mV
Maximum VDRP Voltage
CSx – CSREF = 50 mV,
VFB = COMP, TA = 25°C,
Measure VDRP – COMP
500
555
610
mV
Current Sense Input
to VDRP Gain
CSx – CSREF = 50 mV,
VFB = COMP, TA = 25°C,
Measure VDRP – COMP
2.5
2.78
3.05
V/V
([email protected] * [email protected]) @ 106
DT @ [email protected]
–
–685
–
ppm/°C
CSx – CSREF = 50 mV,
VFB = COMP, Measure VDRP –
COMP VDRP = 1.5 V
1.0
7.0
14
mA
SS Source Current
VCC = 10 V
130
160
200
µA
SS Sink Current
VCC = 7.0 V
4.0
5.0
6.25
µA
SS Min Threshold
VCC = 10 V
0.25
0.3
0.35
V
SS Max Threshold
VCC = 10 V
2.4
2.7
–
V
20
32
48
–
200
900
3000
µA
Temperature Coefficient
of VDRP Gain
VDRP Source Current Limit
Soft Start
SS Source/Sink Ratio
SS COMP Pull Down Current
–
VCC = 10 V
Current Sense Amplifiers
CSREF Input Bias Current
CSREF = CSx = 0 V
–
3.4
4.0
µA
CSx Input Bias Current
CSREF = CSx = 0 V
–
0.1
1.0
µA
Sense Amp Gain
CSREF = 0 V, CSx = 0.05 V,
Measure V(COMP) when GATEx
switches high
–
2.65
–
V/V
Common Mode Input Range
Note 4
0
–
2.0
V
–
7.0
–
MHz
75
85
100
mV
Bandwidth
Single Phase Pulse by Pulse
Current Limit
–
VFB = CSREF = 0.5 V, COMP =
2.0 V, Measure CSx – CSREF
when GATEx goes low
4. Guaranteed by design. Not tested in production.
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CS5307
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEx = 100 pF,
CCOMP = 0.01µF, CSS = 0.1µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
–
0.1
1.0
µA
Current Sense Amplifiers
OCSET Input Bias Current
OCSET = 0 V
Current Sense Input to OCSET
Gain
OCSET/(CSx–CSREF), 0.25 V <
OCSET < 0.6 V, GATEx not
switching
2.5
2.8
3.1
V/V
Current Limit Filter Slew Rate
CSREF = 1.1 V, CSx = 1.0 V, pulse
CSx to 1.16 V, Note 5.
2.0
5.0
13
mV/µs
General Electrical Specification
VCC Operating Current
COMP = 0.3 V (no switching)
–
20
30
mA
UVLO Start Threshold
SS Charging Gates Switching
8.5
9.0
9.5
V
UVLO Stop Threshold
Gates not switching, SS & COMP
discharging
7.5
8.0
8.5
V
UVLO Hysteresis
Start–Stop
0.8
1.0
1.2
V
5. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
Pin Number
Pin Symbol
Pin Name
1
GND
Ground
2
OCSET
Overcurrent Set
3
ROSC
Oscillator Frequency
Adjust
ROSC is a regulated 1.0 V output and programs the oscillator frequency
with a resistor to GND.
4–7
CS1–CS4
Current Sense Inputs
Non–inverting inputs to the current sense amplifiers.
8
CSREF
Current Sense Reference
9
VDRP
Current Sense Amp
Output
10
VFB
Voltage Feedback
11
COMP
Error Amp Output and
PWM Comparator Input
12
SS
Soft Start
13
PWRGD
Power Good Output
Open collector output, which is “low” when the converter output is out of
regulation.
14
PWRGDS
Power Good Sense
A resistor divider from VOUT to GND programs the Power Good lower
threshold.
15–19
VID4–VID0
DAC VID Inputs
TTL–compatible logic input used to program the converter output voltage.
Internal 50 kΩ pull–ups to 3.3 V via a blocking diode are provided. All high
generates fault.
20–23
GATE4–1
Channel Outputs
24
VCC
Supply Input
Function
IC power supply return. Connected to IC substrate.
Resistor divider from ROSC to GND. Programs the threshold of the hiccup
overcurrent protection.
Inverting input to the current sense amplifiers and reference for Power Good.
Programs the voltage drop due to loading. A resistor from VDRP to FB
programs the amount of Adaptive Voltage Positioning. Omitting this
resistor defeats the AVP function.
Error Amplifier inverting input. Input bias current is used to program AVP
light load offset via a resistor connected to the converter output voltage.
Provides loop compensation and is clamped by SS.
Controls fault timing and startup.
PWM outputs to drive FET driver IC.
IC bias input.
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CS4
CS3
CS2
CS1
CSREF
PWRGDS
PWRGD
VDRP
VID0
VID1
VID2
VID3
VID4
OCSET
50 k
−
+
−
+
−
+
−
+
AVP Amp
×4
×4
CO2
×4
CO3
×4
CO4
× 2.65
CO4F
−
+
× 2.65
CO3F
−
+
× 2.65
CO2F
−
+
*0.75 V
1.975 V
*0.5 V
DAC OUTPUT
VID = 11111 ?
3.3 V
OC
Filter
UVLO
Comparator
Start
Stop
DAC
+
CO1
× 2.65
CO1F
−
+
Delay
SS
0.3 V
OC
Comparator
−
+
0.6 V
+
−
5.0 µA
160 µA
3.3 V
VFB
Discharge
Comparator
Set Dominant
Soft Start
Latch
+
−
+
−
3.3 V
IBIAS
COMP
1.0 V
Art
Ramp 4
Art
Ramp 3
Art
Ramp 2
Art
Ramp 1
CO4F
CO3F
CO2F
CO1F
+
−
FAULT
ILIM2
Comparator
ILIM3
Comparator
ROSC
Pulseout4
Ramp4
Pulseout3
Ramp3
Pulseout2
Ramp2
Pulseout1
Ramp1
Oscillator
ILIM4
Comparator
0.33 V
+
−
PWM4
Comparator
−
+
0.33 V
+
−
PWM3
Comparator
−
+
0.33 V
+
−
PWM2
Comparator
−
+
0.33 V
ILIM1
Comparator
Current
Source IOSC
Generator
CO4
CO3
CO2
CO1
+
−
PWM1 Comparator
−
+
PWM4
Latch
PWM3
Latch
PWM2
Latch
PWM1
Latch
Reset
Dominant
Reset
Dominant
Reset
Dominant
Reset
Dominant
9.0 V
8.0 V
−
+
−
−
−
+
−
+
−
+
Figure 2. Block Diagram
−
+
+
−
+
−
+
8
−
+
−
+
−
+
−
+
−
+
VCC
VCC
VCC
VCC
VCC
GND
GATE4
GATE3
GATE2
GATE1
CS5307
CS5307
TYPICAL PERFORMANCE CHARACTERISTICS
900
25
VFB Bias Current (µA)
800
Frequency (kHz)
700
600
500
400
300
20
15
10
5
200
100
10
20
30
40
50
ROSC Value (kΩ)
60
0
10
70
Figure 3. Oscillator Frequency
20
30
40
50
ROSC Value (kΩ)
60
70
80
Figure 4. VFB Bias Current vs. ROSC Value
410
24
409
23
408
FOSC (kHz)
ICC (mA)
22
21
407
406
405
404
20
403
19
402
18
0
20
40
60
TA (°C)
80
401
120
100
Figure 5. ICC vs. Temperature
0
20
40
60
TA (°C)
80
100
120
Figure 6. Oscillator Frequency vs. Temperature
(ROSC = 32.4 kW)
0.20
700
VID = 1.1 V
VID = 1.3 V
650
Offset Voltage (mV)
0.15
Error (%)
VID = 1.5 V
0.10
0.05
0.00
600
550
500
450
400
350
–0.05
0
20
40
60
TA (°C)
80
300
120
100
Figure 7. DAC Output Error vs. Temperature
0
20
40
60
TA (°C)
80
100
120
Figure 8. Current Sense Amplifier Channel Startup
Offset Voltage vs. Temperature
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9
CS5307
TYPICAL PERFORMANCE CHARACTERISTICS
1.00
2.9
Current Sense Amp
to OC Comparator
Gain (V/V)
2.7
0.95
Power Good Delay (ms)
2.8
Current Sense Amp
to VDRP Gain
2.6
2.5
Current Sense Amp
to PWM Comparator
2.4
2.3
2.2
0.90
0.85
0.80
0.75
0.70
0.65
0
20
40
60
TA (°C)
80
0.60
120
100
Figure 9. Sense Amp Gains vs. Temperature
0
20
40
60
TA (°C)
80
100
120
Figure 10. Power Good Delay vs. Temperature
0.3
–3.55
0.2
VDRP Source Current (mA)
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–3.60
–3.65
–3.70
–3.75
–0.7
–0.8
0
20
40
60
TA (°C)
80
100
–3.80
120
Figure 11. VDRP to DAC Output Offset Voltage
vs. Temperature
0
20
40
10.28
VFB = 1.0 V
10.26
10.24
VFB = 1.9 V
10.22
10.20
10.18
0
20
40
60
TA (°C)
80
100
120
Figure 12. VDRP Source Current vs. Temperature
10.30
VFB Bias Current (µA)
Offset Voltage (mV)
0.1
60
TA (°C)
80
100
Figure 13. VFB Bias Currents vs. Temperature
(ROSC = 32.4 kW)
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CS5307
APPLICATIONS INFORMATION
Overview
previous phase. Normally, GATEx transitions to a high
voltage at the beginning of each oscillator cycle. Inductor
current ramps up until the combination of the current sense
signal, the internal ramp and the output voltage ripple trip
the PWM comparator and bring GATEx low. Once GATEx
goes low, it will remain low until the beginning of the next
oscillator cycle. While GATEx is high, the Enhanced V2
loop will respond to line and load variations. On the other
hand, once GATEx is low, the loop cannot respond until the
beginning of the next PWM cycle. Therefore, constant
frequency Enhanced V2 will typically respond to
disturbances within the off–time of the converter.
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional input (CSx) for
inductor current information has been added to the V2 loop
for each phase as shown in Figure 14. The triangular
inductor current is measured differentially across RS,
amplified by CSA and summed with the channel startup
offset, the internal ramp and the output voltage at the
non–inverting input of the PWM comparator. The purpose
of the internal ramp is to compensate for propagation delays
in the CS5307. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The CS5307 provides a CSx
input for each phase, but the CSREF and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CSREF and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.
The CS5307 DC/DC controller from ON Semiconductor
was developed using the Enhanced V2 topology. Enhanced
V2 combines the original V2 topology with peak
current–mode control for fast transient response and current
sensing capability. The addition of an internal PWM ramp
and implementation of fast–feedback directly from Vcore
has improved transient response and simplified design. The
CS5307 includes Power Good (PWRGD), providing a
highly integrated solution to simplify design, minimize
circuit board area, and reduce overall system cost.
Two advantages of a multi–phase converter over a
single–phase converter are current sharing and increased
apparent output frequency. Current sharing allows the designer
to use less inductance in each phase than would be required in
a single–phase converter. The smaller inductor will produce
larger ripple currents but the total per–phase power dissipation
is reduced because the RMS current is lower. Transient
response is improved because the control loop will measure
and adjust the current faster in a smaller output inductor.
Increased apparent output frequency is desirable because the
off– time and the ripple voltage of the multi–phase converter
will be less than that of a single–phase converter.
Fixed Frequency Multi–Phase Control
In a multi–phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5307 controller uses four–phase, fixed–frequency,
Enhanced V2 architecture to measure and control currents in
individual phases. Each phase is delayed 90° from the
x = 1, 2, 3, or 4
SWNODE
Lx
RLx
CSx
+
CSA
–
RSx
COx
Internal Ramp
VOUT
(VCORE)
+
–
CSREF
“Fast–Feedback”
Connection
+
VFB
–
E.A.
+
DAC
Out
Channel
Start–Up
Offset
To F/F
Reset
+
–
PWM
COMP
COMP
+
Figure 14. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp
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CS5307
Enhanced V2 responds to disturbances in VCORE by
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in one or two PWM cycles. Fast voltage
feedback is implemented by a direct connection from Vcore
to the non–inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp and
offset. A rapid increase in output current will produce a
negative offset at Vcore and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in one PWM cycle.
As shown in Figure 14, an internal ramp (nominally 115 mV
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty–cycles may be achieved at higher frequencies. Also,
the additional ramp reduces the reliance on the inductor
current ramp and allows greater flexibility when choosing
the output inductor and the RCSxCCSx time constant of the
feedback components from VCORE to the CSx pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
DV + RS @ GCSA @ DIOUT
The single–phase power stage output impedance is:
Single Stage Impedance + DVOUTńDIOUT + RS @ GCSA
The total output impedance will be the single stage
impedance divided by 4.
The output impedance of the power stage determines how
the converter will respond during the first few microseconds
of a transient before the feedback loop has repositioned the
COMP pin.
The peak output current can be calculated from:
IOUT,PEAK + (VCOMP * VOUT * Offset)ń(RS @ GCSA)
Figure 15 shows the step response of the COMP pin at a
fixed level. Before T1, the converter is in normal
steady–state operation. The inductor current provides a
portion of the PWM ramp through the current sense
amplifier. The PWM cycle ends when the sum of the current
ramp, the “partial” internal ramp voltage signal and offset
exceed the level of the COMP pin. At T1, the output current
increases and the output voltage sags. The next PWM cycle
begins and the cycle continues longer than previously while
the current signal increases enough to make up for the lower
voltage at the VFB pin and the cycle ends at T2. After T2, the
output voltage remains lower than at light load and the
average current signal level (CSx output) is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system, the COMP pin would
move higher to restore the output voltage to the original
level.
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset
) Int_Ramp ) GCSA @ Ext_Rampń2
Int_Ramp is the “partial” internal ramp value at the
corresponding duty cycle, Ext_Ramp is the peak–to–peak
external steady–state ramp at 0 A, GCSA is the current sense
amplifier gain (nominally 2.65 V/V) and the channel startup
offset is typically 0.60 V. The magnitude of the Ext_Ramp
can be calculated from:
SWNODE
Ext_Ramp + D @ (VIN * VOUT)ń(RCSx @ CCSx @ fSW)
VFB (VOUT)
For example, if VOUT at 0 A is set to 1.700 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.700/12.0 or 14.2%. Int_Ramp will be 115 mV/50% ⋅ 14.2%
= 33 mV. Realistic values for RCSx, CCSx and fSW are 10 kΩ,
0.015 µF and 650 kHz. Using these and the previously
mentioned formula, Ext_Ramp will be 15.0 mV.
Internal Ramp
CSA Out w/
Exaggerated
Delays
VCOMP + 1.700 V ) 0.60 V ) 33 mV
COMP–Offset
) 2.65 VńV @ 15.0 mVń2
+ 2.353 Vdc.
CSA Out + Ramp + CSREF
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
T1
T2
Figure 15. Open Loop Operation
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CS5307
RCSx
SWNODE
x = 1, 2, 3, or 4
CSx
+
CSA
–
Lx
CCSx
COx
Internal Ramp
RLx
VOUT
(VCORE)
+
–
CSREF
“Fast–Feedback”
Connection
+
VFB
–
E.A.
+
DAC
Out
Channel
Start–Up
Offset
To F/F
Reset
+
–
PWM
COMP
COMP
+
Figure 16. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp
Inductive Current Sensing
accuracy of the current sharing between phases. The worst
case CSA input mismatch is ±10 mV and will typically be
within 4.0 mV. The difference in peak currents between
phases will be the CSA input mismatch divided by the
current sense resistance. If all current sense components are
of equal resistance, a 3.0 mV mismatch with a 2.0 mΩ sense
resistance will produce a 1.5 A difference in current between
phases.
For lossless sensing, current can be sensed across the
inductor as shown in Figure 16. In the diagram, L is the output
inductance and RL is the inherent inductor resistance. To
compensate the current sense signal, the values of RCSx and
CCSx are chosen so that L/RL = RCSx ⋅ CCSx. If this criteria
is met, the current sense signal will be the same shape as the
inductor current and the voltage signal at CSx will represent
the instantaneous value of inductor current. Also, the circuit
can be analyzed as if a sense resistor of value RL was used.
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
considered when setting the OCSET threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 14.
External Ramp Size and Current Sensing
The internal ramp allows flexibility in setting the current
sense time constant. Typically, the current sense RCSx ⋅ CCSx
time constant should be equal to or slightly slower than the
inductor’s time constant. If RC is chosen to be smaller
(faster) than L/RL, the AC or transient portion of the current
sensing signal will be scaled larger than the DC portion. This
will provide a larger steady–state ramp, but circuit
performance will be affected and must be evaluated
carefully. The current signal will overshoot during transients
and settle at the rate determined by RCSx ⋅ CCSx. It will
eventually settle to the correct DC level, but the error will
decay with the time constant of RCSx ⋅ CCSx. If this error is
excessive, it will affect transient response, adaptive
positioning and current limit. During a positive current
transient, the COMP pin will be required to undershoot in
response to the current signal in order to maintain the output
voltage. Similarly, the VDRP signal will overshoot which
will produce too much transient droop in the output voltage.
The single–phase pulse–by–pulse overcurrent protection
will trip earlier than it would if compensated correctly and
hiccup–mode current limit will have a lower threshold for
fast rising step loads than for slowly rising output currents.
The waveforms in Figure 17 show a simulation of the
current sense signal and the actual inductor current during a
positive step in load current with values of L = 500 nH, RL
= 1.6 mΩ, RCSx = 20 kΩ and CCSx = .01 µF. In this case, ideal
current signal compensation would require RCSx to be 31 kΩ.
Current Sharing Accuracy
Printed circuit board (PCB) traces that carry inductor
current can be used as part of the current sense resistance
depending on where the current sense signal is picked off.
For accurate current sharing, the current sense inputs should
sense the current at relatively the same point for each phase
and the connection to the CSREF pin should be made so that
no phase is favored. In some cases, especially with inductive
sensing, resistance of the PCB can be useful for increasing
the current sense resistance. The total current sense
resistance used for calculations must include any PCB trace
resistance between the CSx input and the CSREF input that
carries inductor current.
Current Sense Amplifier (CSA) input mismatch and the
value of the current sense component will determine the
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CS5307
Due to the faster than ideal RC time constant, there is an
overshoot of 50% and the overshoot decays with a 200 µs
time constant. With this compensation, the OCSET pin
threshold must be set more than 50% above the full load
current to avoid triggering current limit during a large output
load step.
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients.
Adaptive voltage positioning can reduce peak–peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is applied. Similarly, the output
voltage can be set lower than nominal during heavy loads to
reduce overshoot when the load current is removed. For low
current applications, a droop resistor can provide fast,
accurate adaptive positioning. However, at high currents,
the loss in a droop resistor becomes excessive. For example,
a 50 A converter with a 1 mΩ resistor would provide a 50
mV change in output voltage between no load and full load
and would dissipate 2.5 W.
Lossless adaptive voltage positioning (AVP) is an
alternative to using a droop resistor, but it must respond to
changes in load current. Figure 18 shows how AVP works.
The waveform labeled “normal” shows a converter without
AVP. On the left, the output voltage sags when the output
current is stepped up and later overshoots when current is
stepped back down. With fast (ideal) AVP, the peak–to–peak
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded.
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application diagram in Figure 1). To set the no–load
positioning, a resistor is placed between the output voltage
and VFB pin. The VFB bias current will develop a voltage
across the resistor to adjust the no–load output voltage. The
VFB bias current is dependent on the value of ROSC as shown
in the datasheets.
During no–load conditions, the VDRP pin is at the same
voltage as the VFB pin, so none of the VFB bias current flows
through the VDRP resistor. When output current increases,
the VDRP pin voltage increases proportionally. Current set
by the VDRP resistor offsets the VFB bias current, causing the
output voltage to decrease.
The response during the first few microseconds of a load
transient is controlled primarily by power stage output
impedance, and by the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
ramp size is too large or the error amp too slow, there will be
a long transition to the final voltage after a transient. This
will be most apparent with low capacitance output filters.
Figure 17. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50 µs/div)
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 18. Adaptive Voltage Positioning
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V2 control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This results in a “crowbar” action to
clamp the output voltage and prevent damage to the load.
The regulator will remain in this state until the overvoltage
condition ends or the input voltage is pulled low.
Power Good
According to the latest specifications, the Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 19.
The PWRGDS pin is provided to allow the PWRGD
comparators to accurately sense the output voltage. The
effect of the PWRGD lower threshold can be modified using
a resistor divider from the output to PWRGDS to ground, as
shown in Figure 20.
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CS5307
PWRGD
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
PWRGD
low
HIGH
LOW
PWRGD
high
–5.0% +5.0%
VLOWER
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
VOUT
PWRGD
low
–5.0% +5.0%
R1
PWRGDS
R2
VOUT
1.975 V
Figure 19. PWRGD Assertion Window
Figure 20. Adjusting the PWRGD Threshold
Current Limit
Since the internally–set thresholds for PWRGDS are
VID/2 for the lower threshold and a fixed 1.975V for the
upper threshold, a simple equation can be provided to assist
the designer in selecting a resistor divider to provide the
desired PWRGD performance.
Two levels of over–current protection are provided. First,
if the voltage on the Current Sense pins (CSx) exceeds
CSREF by more than a fixed threshold (Single Pulse Current
Limit), the PWM comparator is turned off. This provides
fast peak current protection for individual phases. Second,
the individual phase currents are summed and low–pass
filtered to compare an averaged current signal to a user
adjustable voltage on the OCSET pin. If the OCSET voltage
is exceeded, the fault latch trips and the Soft Start capacitor
discharges until the Soft Start pin reaches 0.3 V. Then Soft
Start begins. The converter will continue to operate in a low
average current hiccup–mode until the fault condition is
corrected.
V
R ) R2
VLOWER + VID @ 1
2
R1
VUPPER + 1.975 V
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 500 µs. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low.
In order to use the PWRGD pin as specified, the user is
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
Fault Protection Logic
The CS5307 includes fault protection circuitry to prevent
harmful modes of operation from occurring. The fault logic
is described in Table 1.
Undervoltage Lockout
Gate Outputs
The CS5307 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until VCC
applied to the IC reaches 9 V. The GATE outputs are disabled
when VCC drops below 8 V.
The CS5307 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
Soft Start and Hiccup Mode
The output voltage of the CS5307 is set by means of a
5–bit, 1% DAC. The DAC pins are internally pulled up to a
3.3 V rail through a blocking diode and a set of 50 kΩ
resistors. The blocking diode allows external pull up to a
bias voltage greater than 3.3 V and less than 13 V.
The output of the DAC is described in the Electrical
Characteristics section of the data sheet. These outputs are
consistent with the latest VRM and processor specifications.
The DAC output is equal to the VID code specification.
In order to produce a workable power supply using the
CS5307, the designer is expected to use AVP as described
earlier to position the output voltage above the DAC output,
resulting in an output voltage somewhere in the middle of
the acceptable range.
At initial power–up, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 160 µA. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper start–up behavior. All GATE outputs are
held low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally. In current limit, the internal fault latch will
initiate a 5 µA discharge current on the SS pin, and the
internal clamp will discharge the capacitor connected to the
COMP pin at a similar rate. This performance will result in
GATE pulses being generated until the overcurrent
condition reoccurs and the discharge/soft start cycle begins
anew.
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CS5307
Table 1. Fault Protection Logic
Fault Modes
Stop Switching
SS Pin Characteristics
Undervoltage Lockout
Yes
–5.0 µA
SS < 0.3 V
VID–11111
Yes
–5.0 µA
Change VID Code
Phase Over Current
(0.33 V Limit)
No
Not Affected
Automatic
magnetic saturation, temperature, physical size and cost
(usually the primary concern).
In general, the output inductance value should be
elecrrically and physically as small as possible to provide the
best transient response at minimum cost. If a large
inductance value is used, the converter will not respond
quickly to rapid changes in the load current. On the other
hand, too low an inductance value will result in very large
ripple currents in the power components (MOSFETs,
capacitors, etc.) resulting in increased dissipation and lower
converter efficiency. Increased ripple currents force the
designer to use higher rated MOSFETs, oversize the thermal
solution, and use more, higher rated input and output
capacitors, adversely affecting converter cost.
One method of calculating an output inductor value is to
size the inductor to produce a specified maximum ripple
current in the inductor. Lower ripple currents will result in
less core and MOSFET losses and higher converter
efficiency. Equation 3 may be used to calculate the
minimum inductor value to produce a given maximum
ripple current (α) per phase. The inductor value calculated
by this equation is a minimum because values less than this
will produce more ripple current than desired. Conversely,
higher inductor values will result in less than the selected
maximum ripple current.
The latest VRM and processor specifications require a
power supply to turn its output off in the event of a 11111
VID code. When the DAC sees such a code, the GATE pins
stop switching and go low. This condition is described in
Table 1.
Design Procedure
1. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady–state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
Choose the number of bulk output capacitors to meet the
peak transient requirements. The formula below can be used
to provide a starting point for the minimum number of bulk
capacitors (NOUT,MIN):
NOUT,MIN + ESR per capacitor @
DIO,MAX
DVO,MAX
Reset Method
(1)
(VIN * VOUT) @ VOUT
LoMIN +
(a @ IO,MAX @ VIN @ fSW)
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to:
(3)
α is the ripple current as a percentage of the maximum
output current per phase (α = 0.15 for ±15%, α = 0.25 for
±25%, etc.). If the minimum inductor value is used, the
inductor current will swing ± α% about its value at the
center. Therefore, for a four–phase converter, the inductor
must be designed or selected such that it will not saturate
with a peak current of (1 + α) ⋅ IO,MAX/4.
The maximum inductor value is limited by the transient
response of the converter. If the converter is to have a fast
transient response, the inductor should be made as small as
possible. If the inductor is too large its current will change
too slowly, the output voltage will droop excessively, more
bulk capacitors will be required and the converter cost will
be increased. For a given inductor value, it is useful to
determine the times required to increase or decrease the
current.
For increasing current:
DVO,MAX + (DIO,MAXńDt) @ ESL ) DIO,MAX @ ESR (2)
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
2. Output Inductor Selection
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady–state and
transient performance of the converter. When selecting an
inductor, the designer must consider factors such as DC
current, peak current, output voltage ripple, core material,
DtINC + Lo @ DIOń(VIN * VOUT)
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(3.1)
CS5307
For decreasing current:
ILo,MIN is the minimum output inductor current:
DtDEC + Lo @ DIOń(VOUT)
ILo,MIN + IO,MAXń4 * DILoń2
(3.2)
(9)
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. Thus, it may be
more difficult for the converter to stay within the regulation
limits when the load is removed than when it is applied and
excessive overshoot may result.
The output voltage ripple can be calculated using the
output inductor value derived in this Section (LoMIN), the
number of output capacitors (NOUT,MIN) and the per
capacitor ESR determined in the previous Section:
∆ILo is the peak–to–peak ripple current in the output
inductor of value Lo:
VOUT,P–P + (ESR per cap ń NOUT,MIN) @
NJ(VIN * #Phases @ VOUT) @ D ń (LoMIN @ fSW)Nj
Select the number of input capacitors (NIN) to provide the
RMS input current (ICIN,RMS) based on the RMS ripple
current rating per capacitor (IRMS,RATED):
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
For the four–phase converter, the input capacitor(s) RMS
current is then:
ICIN,RMS + [4D @ (IC,MIN2 ) IC,MIN @ DIC,IN
(4)
NIN + ICIN,RMSńIRMS,RATED
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors, one must first determine the
total RMS input ripple current. To this end, begin by
calculating the average input current to the converter:
PCIN + ICIN,RMS2 @ ESR_per_capacitorńNIN (13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10°C rise in the
capacitor’s temperature.
(5)
where:
D is the duty cycle of the converter, D = VOUT/VIN;
η is the specified minimum efficiency;
IO,MAX is the maximum converter output current.
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 21.
The following equations will determine the maximum and
minimum currents delivered by the input capacitors:
(6)
IC,MIN + ILo,MINńh * IIN,AVG
(7)
IC,MAX
∆IC,IN = IC,MAX – IC,MIN
IC,MIN
0A
tON
T/4
FET Off,
Caps Charging
–IIN,AVG
FET On,
Caps Discharging
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAXń4 ) DILoń2
(12)
For a four–phase converter with perfect efficiency (η = 1),
the worst case input ripple–current will occur when the
converter is operating at a 12.5% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 12.5% of the
converter’s DC output current. At other duty cycles, the
ripple–current will be less. For example, at a duty cycle of
either 6% or 19%, the four–phase input ripple–current will
be approximately 10% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple–current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should know the ESR of the input
capacitors. The input capacitor power loss can be calculated
from:
3. Input Capacitor Selection
IC,MAX + ILo,MAXńh * IIN,AVG
(11)
) DIC,IN2ń3) ) IIN,AVG2 @ (1 * 4D)]1ń2
This formula assumes steady–state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the four individual phase currents that are 90
degrees out–of–phase. As the inductor current in one phase
ramps upward, current in the other phase ramps downward
and provides a canceling of currents during part of the
switching cycle. Therefore, the total output ripple current
and voltage are reduced in a multi–phase converter.
IIN,AVG + IO,MAX @ Dńh
(10)
(8)
Figure 21. Input Capacitor Current for a
Four–Phase Converter
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CS5307
VOUT
MAX dI/dt occurs in
first few PWM cycles.
ILi
Vi(t = 0) = 12 V
Q1
SWNODE
Li
TBD
Vo(t = 0) = 1.5 V
Lo
NCi × Ci
+
–
ILo
+ VCi
+
NCo × Co
Q2
Vi
12 V
ESRCi/NCi
14 u(t)
ESRCo/NCo
Figure 22. Calculating the Input Inductance
4. Input Inductor Selection
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step–load
change is applied as shown in Figure 22. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously, so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (IO,MAX), the per capacitor ESR of the output
capacitors (ESROUT) and the number of the output
capacitors (NOUT) as shown in Figure 22. Assuming the load
current is shared equally between the four phases, the output
voltage at full transient load will be:
VOUT,FULL–LOAD +
dILońdt + DVLońLo
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (∆VCi) is determined by the number of input
capacitors (NIN), their per capacitor ESR (ESRIN) and the
current in the output inductor according to:
DVCi + ESRINńNIN @ dILońdt @ tON
(17)
+ ESRINńNIN @ dILońdt @ DńfSW
Before the load is applied, the voltage across the input
inductor (VLi) is very small and the input capacitors charge
to the input voltage VIN. After the load is applied, the voltage
drop across the input capacitors, ∆VCi, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
LiMIN + VLi ń dIINńdtMAX
(18)
+ DVCi ń dIINńdtMAX
(14)
VOUT,NO–LOAD * (IO,MAXń4) @ ESROUTńNOUT
dIIN/dtMAX is the maximum allowable input current slew
rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will help
reduce the slew rate of the input current.
When the control MOSFET (Q1 in Figure 22) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
DVLo + VIN * VOUT,FULL–LOAD
(16)
(15)
+ VIN * VOUT,NO–LOAD
) (IO,MAXń4) @ ESROUTńNOUT
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CS5307
As with the output inductor, the input inductor must
support the maximum current without saturating the
inductor. Also, for an inexpensive iron powder core, such as
the –26 or –52 from Micrometals, the inductance “swing”
with DC bias must be taken into account and inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
ID
VGATE
VGS_TH
5. MOSFET & Heatsink Selection
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the non–overlap
time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
QGS1
D + VOUTńVIN
(23)
∆ILo is the peak–to–peak ripple current in the output
inductor of value Lo:
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
(24)
RDS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Qswitch is the post gate threshold portion of the
gate–to–source charge plus the gate–to–drain charge. This
may be specified in the data sheet or approximated from the
gate–charge curve as shown in the Figure 23.
(19)
Qswitch + Qgs2 ) Qgd
(25)
Ig is the output current from the gate driver IC.
VIN is the input voltage to the converter.
fsw is the switching frequency of the converter.
QG is the MOSFET total gate charge to obtain RDS(on).
Commonly specified in the data sheet.
Vg is the gate drive voltage.
QRR is the reverse recovery charge of the lower MOSFET.
Qoss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the loss associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
IRMS,CNTL is the RMS value of the trapezoidal current in
the control MOSFET:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
) (Vfdiode @ IO,MAXń4 @ t_nonoverlap @ fSW)
(20)
(26)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non–overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2
ILo,MAX is the maximum output inductor current:
(21)
(27)
IRMS,SYNCH + Ǹ1 * D
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAXń4 * DILoń2
VDRAIN
D is the duty cycle of the converter:
) (Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
ILo,MAX + IO,MAXń4 ) DILoń2
QGD
Figure 23. MOSFET Switching Characteristics
) (ILo,MAX @ QswitchńIg @ VIN @ fSW)
IRMS,CNTL + ǸD
QGS2
(22)
IO,MAX is the maximum converter output current.
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CS5307
where:
Vfdiode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non–overlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
(28)
6. Adaptive Voltage Positioning
where:
θT is the total thermal impedance (θJC + θSA);
θJC is the junction–to–case thermal impedance of the
MOSFET;
θSA is the sink–to–ambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
TJ is the specified maximum allowed junction
temperature;
TA is the worst case ambient operating temperature.
For TO–220 and TO–263 packages, standard FR–4
copper clad circuit boards will have approximate thermal
resistances (θSA) as shown below:
Pad Size
(in2/mm2)
Single–Sided
1 oz. Copper
0.50/323
60–65°C/W
0.75/484
55–60°C/W
1.00/645
50–55°C/W
1.50/968
45–50°C/W
RCS1
L1
0A
CCS1
RCSx
Lx
0A
CS1
CSx
CCSx
There are two resistors that determine the Adaptive
Voltage Positioning: RFB and RDRP. RFB establishes the
no–load “high” voltage position and RDRP determines the
full–load “droop” voltage.
Resistor RFB is connected between VCORE and the VFB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the VFB pin and develop a voltage
drop from VCORE to the VFB pin. Because the error amplifier
regulates VFB to the DAC setting, the output voltage,
VCORE, will be lower by the amount IBIASVFB ⋅ RFB. This
condition is shown in Figure 24.
To calculate RFB, the designer must specify the no–load
voltage decrease below the VID setting (∆VNO–LOAD) and
determine the VFB bias current. Usually, the no–load voltage
increase is specified in the design guide for the processor
that is available from the manufacturer. The VFB bias current
is determined by the value of the resistor from ROSC to
ground (see Figure 4 in the data sheet for a graph of
IBIASVFB versus ROSC). The value of RFB can then be
calculated:
RFB + DVNO–LOADńIBIASVFB
+–
+
–
GVDRP
COMP
Σ
–
+
qT t (TJ * TA)ńPD
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET RDS(on)). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require re–design to add heatsinking.
Error
Amp
IBIASVFB
RDRP
+
–
GVDRP
VDRP = VID
RFB
VFB = VID
IDRP = 0
CSREF
VID Setting
IFB = IBIASVFB
VCORE = VID + IBIASVFB w RFB
Figure 24. AVP Circuitry at No–Load
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20
VCORE
(29)
CS5307
L1
IMAX/2
+–
+
–
GVDRP
COMP
Σ
Error
Amp
CCS1
RCSx
Lx
IMAX/2
CS1
CSx
–
+
RCS1
VID Setting
IBIASVFB
RDRP
+
–
GVDRP
RFB
VDRP = VID +
VFB = VID
IMAX • RL • GVDRP
VCORE
CCSx
IDRP
IFB
IDRP = IMAX • RL • GVDRP/RDRP
IFBK = IDRP – IBIASVFB
CSREF
VCORE = VID – (IDRP – IBIASVFB) w RFB
= VID – IMAX w RL w GVDRP w RFB/RDRP + IBIASVFB w RFB
Figure 25. AVP Circuitry at Full–Load
Resistor RDRP is connected between the VDRP and the
VFB pins. At no–load, the VDRP and the VFB pins will both
be at the DAC voltage. This resistor will conduct zero
current. However, at full–load, the voltage at the VDRP pin
will increase proportional to the output inductor’s current
while VFB will still be regulated to the DAC voltage. Current
will be conducted from VDRP to VFB by RDRP. This current
will be large enough to supply the VFB bias current and cause
a voltage drop from VFB to VCORE across RFB. The
converter’s output voltage will be reduced. This condition is
shown in Figure 25.
To determine the value of RDRP, the designer must specify
the full–load voltage reduction from the VID (DAC) setting
(∆VOUT,FULL–LOAD) and predict the voltage increase at the
VDRP pin at full–load. Usually, the full–load voltage
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
voltage increase at the VDRP pin at full–load (∆VDRP), the
designer must consider the output inductor’s resistance
(RL), the PCB trace resistance between the current sense
points (RPCB) and the controller IC’s gain from the current
sense to the VDRP pin (GVDRP):
Figure 26. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Long
(Slow): VDRP and VOUT Respond Too Slowly.
DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP
(30)
The value of RDRP can then be calculated:
RDRP +
DVDRP
(IBIASVFB ) DVOUT,FULL–LOADńRFB)
(31)
∆VOUT,FULL–LOAD is the full–load voltage reduction
from the VID (DAC) setting. ∆VOUT,FULL–LOAD is not the
voltage change from the no–load AVP setting.
Figure 27. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Short
(Fast): VDRP and VOUT Both Overshoot.
7. Current Sensing
For inductive current sensing, choose the current sense
network (RCSx, CCSx, x = 1, 2, 3, or 4) to satisfy
RCSx @ CCSx + Loń(RL ) RPCB)
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(32)
CS5307
Figure 28. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Optimal:
VDRP and VOUT Respond to the Load Current Quickly
Without Overshooting.
Figure 29. The Value of CAMP Is Too High and the
Loop Gain/Bandwidth Too Low. COMP Slews Too
Slowly Which Results in Overshoot in VOUT.
operating at full steady–state load, the peak–to–peak voltage
ripple (VPP) on the COMP pin should be less than 20 mVPP
as shown in Figure 31. Less than 10 mVPP is ideal. Excessive
ripple on the COMP pin will contribute to jitter.
For resistive current sensing, choose the current sense
network (RCSx, CCSx, x = 1, 2, 3, or 4) to satisfy
RCSx @ CCSx + Loń(Rsense)
(33)
This will provide an adequate starting point for RCSx and
CCSx. After the converter is constructed, the value of RCSx
(and/or CCSx) should be fine–tuned in the lab by observing
the VDRP signal during a step change in load current. Tune
the RCSx ⋅ CCSx network to provide a “square–wave” at the
VDRP output pin with maximum rise time and minimal
overshoot as shown in Figure 28.
9. Current Limit Setting
When the output of the current sense amplifier (COx in the
block diagram) exceeds the voltage on the ILIM pin, the part
will enter hiccup mode. For inductive sensing, the OCSET
pin voltage should be set based on the inductor’s maximum
resistance (RLMAX). The design must consider the
inductor’s resistance increase due to current heating and
ambient temperature rise. Also, depending on the current
sense points, the circuit board may add additional resistance.
In general, the temperature coefficient of copper is +0.39%
per _C. If using a current sense resistor (RSENSE), the
OCSET pin voltage should be set based on the maximum
value of the sense resistor. To set the level of the OCSET pin:
8. Error Amplifier Tuning
After the steady–state (static) AVP has been set and the
current sense network has been optimized, the Error
Amplifier must be tuned. The gain of the Error Amplifier
should be adjusted to provide an acceptable transient
response by increasing or decreasing the Error Amplifier’s
feedback capacitor (CAMP in the Applications Diagram).
The bandwidth of the control loop will vary directly with the
gain of the error amplifier.
If CAMP is too large, the loop gain/bandwidth will be low,
the COMP pin will slew too slowly and the output voltage
will overshoot as shown in Figure 29. On the other hand, if
CAMP is too small, the loop gain/bandwidth will be high, the
COMP pin will slew very quickly and overshoot will occur.
Integrator “wind up” is the cause of the overshoot. In this
case, the output voltage will transition more slowly because
COMP spikes upward as shown in Figure 30. Too much loop
gain/bandwidth increases the risk of instability. In general,
one should use the lowest loop gain/bandwidth possible to
achieve acceptable transient response. This will insure good
stability. If CAMP is optimal, the COMP pin will slew
quickly but not overshoot and the output voltage will
monotonically settle as shown in Figure 32.
After the control loop is tuned to provide an acceptable
transient response, the steady–state voltage ripple on the
COMP pin should be examined. When the converter is
Figure 30. The Value of CAMP Is Too Low and the
Loop Gain/Bandwidth Too High. COMP Moves Too
Quickly, Which Is Evident from the Small Spike in Its
Voltage When the Load Is Applied or Removed. The
Output Voltage Transitions More Slowly Because of
the COMP Spike.
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CS5307
Figure 32. The Value of CAMP Is Optimal. COMP Slews
Quickly Without Spiking or Ringing. VOUT Does Not
Overshoot and Monotonically Settles to Its Final Value.
Figure 31. At Full–Load the Peak–to–Peak Voltage
Ripple on the COMP Pin Should Be Less than 20 mV
for a Well–Tuned/Stable Controller. Higher COMP
Voltage Ripple Will Contribute to Output Voltage Jitter.
VOCSET + (IOUT,LIM ) DILoń2) @ R @ GILIM
(34)
11. Soft Start Time
The Soft Start time (TSS) can be calculated from:
where:
IOUT,LIM is the current limit threshold of the converter;
∆ILo/2 is half the inductor ripple current;
R is either (RLMAX + RPCB) or RSENSE;
GILIM is the current sense to OCSET gain.
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
a step load change will cause the sensed current waveform
to appear larger than the actual inductor current and will trip
the current limit at a lower level than expected.
(36)
TSS + CSS @ DV
ISS
+ CSS @
VCOMP * Channel_Startup_Offset
160 mA
where:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset
) Int_Ramp ) GCSA @ Ext_Rampń2
+ 2.353 Vdc (from page 12)
If CSS = 0.1 µF, then the Soft Start time will be:
10. PWM Comparator Input Voltage
The voltage at the positive input terminal of the PWM
comparator (see Figure 14 or 16) is limited by the internal
voltage supply of the controller (3.3 V), the size of the
internal ramp and the magnitude of the channel startup offset
voltage. To prevent the PWM comparator from saturating,
the differential input voltage from CSREF to CSn (n = 1, 2,
3, or 4) must satisfy the following equation:
VCSREF,MAX ) VCOx,MAX ) 600 mV @ D v 2.45 V
TSS + 0.1 mF @
1.753 Vdc
+ 1.1 ms
160 mA
(37)
The Channel_Startup_Offset is subtracted from VCOMP
as the output does not begin to rise until VCOMP exceeds this
voltage. As the internal and external ramp values are small,
the Soft Start time may be approximated by:
TSS + CSS @
(35)
where:
VCSREF,MAX + Max VID Setting wń AVP @ Full Load
VCOn,MAX + [VCSx * VCSREF] @ GCSA,MAX
+ (IO,MAXń2 ) DILoń2) @ RMAX
@ GCSA,MAX
RMAX + RSENSE or (RL,MAX ) RPCB,MAX)
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VOUT @ 0 A
ISS
(38)
CS5307
PACKAGE DIMENSIONS
SO–24L
DW SUFFIX
CASE 751E–04
ISSUE E
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V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
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CS5307/D