CS8183
Dual Micropower 200 mA
Low Dropout Tracking
Regulator/Line Driver
The CS8183 is a dual low dropout tracking regulator designed to
provide adjustable buffered output voltages that closely track
(±10 mV) the reference inputs. The outputs deliver up to 200 mA
while being able to be configured higher, lower or equal to the
reference voltages.
The outputs have been designed to operate over a wide range (2.8 V
to 45 V) while still maintaining excellent DC characteristics. Because
of the CS8183’s high voltage capability, the part will fit into today’s
new 42 V automotive systems. The CS8183 is protected from reverse
battery, short circuit and thermal runaway conditions. The device also
can withstand 45 V load dump transients and –50 V reverse polarity
input voltage transients. This makes it suitable for use in automotive
environments.
The VREF/ENABLE leads serve two purposes. They are used to
provide the input voltage as a reference for the output and they also
can be pulled low to place the device in sleep mode where it nominally
draws less than 30 µA from the supply.
20
1
SO–20L
DWF
SUFFIX
CASE 751D
PIN CONNECTIONS AND
MARKING DIAGRAM
1
VIN
VOUT1
NC
NC
GND
GND
NC
NC
VADJ1
VREF/ENABLE1
A
WL, L
YY, Y
WW, W
CS8183
AWLYYWW
Features
Two Regulated Outputs 200 mA, ±10 mV Track Worst Case
Low Dropout (0.35 V typ. @ 200 mA)
Low Quiescent Current
Independent Thermal Shutdown
Short Circuit Protection
Wide Operating Range
Internally Fused Leads in the SO–20L Package
•
•
•
•
•
•
•
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VOUT2
VIN2
NC
NC
GND
GND
NC
NC
VREF/ENABLE2
VADJ2
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 9
1
Package
Shipping
CS8183YDWF20
SO–20L
37 Units/Rail
CS8183YDWFR20
SO–20L
1000 Tape & Reel
Publication Order Number:
CS8183/D
CS8183
BLOCK DIAGRAM
VIN1
VOUT1
ESD
Current Limit &
VSAT Sense
Adj1
–
ESD
ENABLE
+
VREF/ENABLE1
ESD
+
GND
Independent
Thermal
Shutdown
–
2.0 V
VIN2
VOUT2
ESD
Current Limit &
VSAT Sense
Adj2
–
ESD
ENABLE
+
VREF/ENABLE2
ESD
+
Independent
Thermal
Shutdown
–
2.0 V
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
–65 to 150
°C
Supply Voltage Range (continuous)
15 to 45
V
Supply Voltage Range (normal, continuous)
3.4 to 45
V
45
V
–10 to 45
V
Maximum Junction Temperature
150
°C
ESD Capability (Human Body Model)
2.0
kV
230 peak
°C
Storage Temperature
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V)
Voltage Range (Adj, VREF/ENABLE, VOUT)
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
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CS8183
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; –40°C ≤ TJ ≤ +125°C; COUT ≥ 10 µF;
0.1 Ω < COUT – ESR < 1.0 Ω @ 10 kHz; unless otherwise stated.)
Test Conditions
Parameter
Min
Typ
Max
Unit
–10
–
10
mV
Regular Output 1, 2
VREF – VOUT
VOUT Tracking Error
4.5 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 200 mA, Note 1.
Dropout Voltage (VIN – VOUT)
IOUT = 100 µA
IOUT = 200 mA
–
–
100
350
150
600
mV
mV
Line Regulation
4.5 V ≤ VIN ≤ 26 V, Note 1.
–
–
10
mV
Load Regulation
100 µA ≤ IOUT ≤ 200 mA, Note 1.
–
–
10
mV
Adj Lead Current
Loop in Regulation
–
0.2
1.0
µA
Current Limit
VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 1.
225
–
700
mA
Quiescent Current (IIN – IOUT)
VIN = 12 V, IOUT = 200 mA
VIN = 12 V, IOUT = 100 µA
VIN = 12 V, VREF/ENABLE = 0 V
–
–
–
15
75
30
25
150
55
mA
µA
µA
Reverse Current
VOUT = 5.0 V, VIN = 0 V
–
0.2
1.5
mA
Ripple Rejection
f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V
60
–
–
dB
–
150
180
210
°C
–
0.80
2.00
2.75
V
–
0.2
1.0
µA
Thermal Shutdown
VREF/ENABLE 1, 2
Enable Voltage
Input Bias Current
VREF/ENABLE 1, 2 > 2.0 V
1. VOUT connected to Adj lead.
PACKAGE PIN DESCRIPTION
Package Lead Number
SO–20L
Lead Symbol
1
VIN1
2
VOUT1
3, 4, 7, 8, 13, 14, 17, 18
NC
5, 6, 15, 16
GND
Ground (4 leads fused)
9
VADJ1
Adjust lead for VOUT1.
10
VREF/ENABLE1
11
VADJ2
12
VREF/ENABLE2
19
VIN2
20
VOUT2
Function
Input voltage for VOUT1.
Regulated output voltage 1.
No connection.
Reference voltage and ENABLE input for VOUT1.
Adjust lead for VOUT2.
Reference voltage and ENABLE input for VOUT2.
Input voltage for VOUT2.
Regulated output voltage 2.
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CS8183
CIRCUIT DESCRIPTION
ENABLE Function
The outputs are capable of supplying 200 mA to the load
while configured as a similiar (Figure 1), lower (Figure 3),
or higher (Figure 2) voltage as the reference lead. The Adj
lead acts as the inverting terminal of the op amp and the
VREF lead as the non–inverting.
The device can also be configured as a high–side driver as
displayed in Figure 6.
By pulling the VREF/ENABLE 1, 2 lead below 2.0 V
typically, (see Figure 4 or Figure 5), the IC is disabled and
enters a sleep state where the device draws less than 30 µA
from supply. When the VREF/ENABLE lead is greater than
2.75 V, VOUT tracks the VREF/ENABLE lead normally.
Output Voltage
Figures 1 through 6 only display one channel of the
device for simplicity. The configurations shown apply
for both channels.
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
GND
GND
GND
C1*
1.0 µF
RA
VOUT, 200 mA
GND
GND
B+
VIN
C2**
10 µF
C1*
1.0 µF
VOUT
B+
VIN
GND
GND
GND
GND
VREF/
ENABLE
Adj
VREF
VREF/
ENABLE
VREF
C1*
1.0 µF
R
R1
Adj
GND
Figure 2. Tracking Regulator at Higher Voltages
Figure 1. Tracking Regulator at the Same Voltage
GND
GND
C1*
1.0 µF
R
VOUT VREF(1 E)
RA
VOUT VREF
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
B+
VIN
VREF/
ENABLE
Adj
5.0 V
VREF/
ENABLE
Adj
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
RF
GND
B+
VIN
R2
VREF
from MCU
VOUT VREF( R2 )
R1 R2
Figure 3. Tracking Regulator at Lower Voltages
VOUT, 200 mA
C2**
10 µF
VOUT
GND
GND
GND
Adj
B+
VIN
GND
VREF/
ENABLE
Figure 4. Tracking Regulator with ENABLE Circuit
200 mA
C1*
1.0 µF
VREF
VOUT
VIN
GND
GND
GND
GND
Adj
100 k
from MCU
VREF/
ENABLE
VOUT B VSAT
Figure 5. Alternative ENABLE Circuit
Figure 6. High–Side Driver
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
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B+
MCU
CS8183
APPLICATION NOTES
External Capacitors
The value of RΘJA can then be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
Output capacitors for the CS8183 are required for
stability. Without them, the regulator outputs will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst–case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitors can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitors must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to –40°C, a capacitor rated at that temperature
must be used.
More information on capacitor selection for SMART
REGULATORs is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators.”
IIN
VIN
IOUT
VOUT
Control
Features
IQ
Figure 7. Dual Output Regulator with Key
Performance Parameters Labeled
Calculating Power Dissipation in a Dual Output Linear
Regulator
Heatsinks
The maximum power dissipation for a dual output
regulator (Figure 5) is:
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA:
PD(max) {VIN(max) VOUT1(min)} IOUT1(max)
{VIN(max) VOUT2(min)}IOUT2(max2)
VIN(max)IQ
(1)
where:
VIN(max) is the maximum input voltage,
VOUT1(min) is the minimum output voltage from VOUT1,
VOUT2(min) is the minimum output voltage from VOUT2,
IOUT1(max) is the maximum output current, for the
application,
IOUT2(max) is the maximum output current, for the
application,
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
RJA 150°C TA
PD
SMART
REGULATOR
RJA RJC RCS RSA
(3)
where:
RΘJC = the junction–to–case thermal resistance,
RΘCS = the case–to–heatsink thermal resistance, and
RΘSA = the heatsink–to–ambient thermal resistance.
RΘJC appears in the package section of the data sheet. Like
RΘJA, it is a function of package type. RΘCS and RΘSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
(2)
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CS8183
PACKAGE DIMENSIONS
SO–20L
DWF SUFFIX
CASE 751D–05
ISSUE F
A
20
X 45 h
1
10
20X
B
0.25
DIM
A
A1
B
C
D
E
e
H
h
L
B
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
PACKAGE THERMAL DATA
Parameter
SO–20L
Unit
RΘJC
Typical
18
°C/W
RΘJA
Typical
73
°C/W
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MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
CS8183
Notes
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CS8183
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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CS8183/D