MAXIM MAX9169EUE

19-2616; Rev 0; 10/02
4-Port LVDS and LVTTL-to-LVDS Repeaters
Ultra-low 150ps (max) pulse skew and 200psP-P (max)
added deterministic jitter ensure reliable communication in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data
recovery or serializers and deserializers. The highspeed switching performance guarantees 630Mbps
data rate and less than 120ps channel-to-channel skew
over the 3.0V to 3.6V operating supply range.
Supply current is 30mA (max) for the MAX9169, and
25mA (max) for the MAX9170. LVDS inputs and outputs
conform to the ANSI EIA/TIA-644 standard. A fail-safe
feature on the MAX9169 sets the output high when the
input is undriven and open, terminated, or shorted. The
MAX9169/MAX9170 are offered in 16-pin TSSOP and
SO packages, and operate over an extended -40°C to
+85°C temperature range.
Refer to the MAX9130 data sheet for an LVDS line
receiver in an SC70 package.
Applications
Point-to-Point Baseband Data Transmission
Features
♦ 150ps (max) Pulse Skew
♦ 200psP-P (max) Added Deterministic Jitter at
630Mbps (223 - 1) PRBS Pattern
♦ 8psRMS (max) Added Random Jitter
♦ 120ps (max) Channel-to-Channel Skew
♦ 630Mbps Data Rate
♦ Conforms to ANSI EIA/TIA-644 LVDS Standard
♦ 30mA (max) (MAX9169), 25mA (max) (MAX9170)
Supply Current, a 15% Improvement vs.
Competition
♦ LVDS (MAX9169) or +5V Tolerant LVTTL/LVCMOS
(MAX9170) Input Versions
♦ Fail-Safe Circuit Sets Output High for Undriven
Differential Input
♦ Output Rated for 10pF Load
♦ Individual Output Enables
♦ Single 3.3V Supply
♦ Improved Second Source of the SN65LVDS104
(MAX9169)/SN65LVDS105 (MAX9170)
♦ 16-Pin SO and TSSOP Packages
Ordering Information
PART
TEMP RANGE
PINPACKAGE
INPUT
MAX9169ESE
-40°C to +85°C
16 SO
LVDS
MAX9169EUE
-40°C to +85°C
16 TSSOP
LVDS
MAX9170ESE
-40°C to +85°C
16 SO
LVTTL
MAX9170EUE
-40°C to +85°C
16 TSSOP
LVTTL
Cellular Phone Base Stations
Typical Application Circuit
Add/Drop Muxes
Digital Cross-Connects
LVDS
Network Switches/Routers
MAX9169
Backplane Interconnect
1
Rx
100Ω
LVDS
Clock Distribution
BACKPLANE
OR CABLE
100Ω
4
MAX9130
Rx
100Ω
MAX9180
MAX9130
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9169/MAX9170
General Description
The MAX9169/MAX9170 low-jitter, low-voltage differential signaling LVDS/LVTTL-to-LVDS repeaters are ideal
for applications that require high-speed data or clock
distribution while minimizing power, space, and noise.
The devices accept a single LVDS (MAX9169) or LVTTL
(MAX9170) input and repeat the input at four LVDS outputs. Each differential output drives 100Ω, allowing
point-to-point distribution of signals on transmission
lines with 100Ω termination at the receiver input. The
MAX9169 and MAX9170 are pin compatible with the
SN65LVDS104 and SN65LVDS105, respectively, and
offer improved pulse-skew performance.
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
ESD Protection
Human Body Model (MAX9169)
(IN+, IN-, OUT_+, OUT_-) ..............................................≥16kV
Human Body Model (MAX9170)
(OUT_+, OUT_-) .............................................................≥10kV
Lead Temperature (soldering, 10s) .................................+300°C
VCC to GND ..............................................................-0.5V to +4V
Inputs
IN+, IN- to GND....................................................-0.5V to +4V
IN, EN_ to GND ....................................................-0.5V to +6V
Outputs
OUT_+, OUT_- to GND.........................................-0.5V to +4V
Continuous Power Dissipation (TA = +70°C)
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input commonmode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID |
= 0.2V, VCM = 1.25V, TA = +25°C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA = +25°C for MAX9170.)
(Notes 1 and 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5
50
-50
-5
-2
-11.8
-1.2
-3.2
UNITS
LVDS INPUTS (IN+, IN-) (MAX9169)
Differential Input High Threshold
VTH
Differential Input Low Threshold
VTL
Input Current
(IN+ or IN-, Single Ended)
IIN+, IIN-
Power-Off Input Current
(IN+ or IN-, Single Ended)
IINO+, IINO-
Input Current
Power-Off Input Current
Fail-Safe Input Resistor
Input Capacitance
IIN+, IINIINO+, IINO-
VIN = 0V, other input open, Figure 1
VIN = +2.4V, other input open, Figure 1
VCC = +1.5V, VIN = +2.4V, other input open,
Figure 1
3.2
mV
mV
-20
20
0.05V ≤VID≤ 0.6V, Figure 1
-15
+15
0.6V <VID≤ 1.2V, Figure 1
-20
+20
0.05V ≤VID≤ 0.6V, VCC = 1.5V, Figure 1
-15
+15
0.6V <VID≤ 1.2V, VCC = 1.5V, Figure 1
-20
+20
RIN1
VCC = 3.6V, 0 or open, Figure 1
103
138
190
RIN2
VCC = 3.6V, 0 or open, Figure 1
154
210
260
CIN
IN+ or IN- to GND (Note 3)
2.2
µA
µA
µA
µA
kΩ
pF
+5V TOLERANT LV TTL/LVCMOS INPUTS (IN, EN_)
Input High Voltage
VIH
2.0
5.5
V
Input Low Voltage
VIL
0
0.8
V
Input Current
Input Capacitance (MAX9170)
IIH
VIN = 2V to 5.5V
20
IIL
VIN = 0 to 0.8V
10
CIN
IN to GND (Note 3)
Differential Output Voltage
VOD
Figures 3, 4, 6, 7
Change in VOD Between
Complementary Output States
∆VOD
Figures 3, 4, 6, 7
2.2
µA
pF
LVDS OUTPUTS (OUT_+, OUT_-)
Steady-State Output Offset
Voltage
2
VOS
Figures 2, 4, 5, 7, 8, 9
250
1.125
350
450
mV
1.5
25
mV
1.26
1.375
V
_______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, EN_ = high, MAX9169 differential input voltage | VID | = 0.05V to 1.2V, LVDS input commonmode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, | VID |
= 0.2V, VCM = 1.25V, TA = +25°C for MAX9169. Typical values are at VCC = 3.3V, VIN = 0 or VCC, TA = +25°C for MAX9170.)
(Notes 1 and 2)
PARAMETER
Change in VOS Between
Complementary Output States
Peak-to-Peak Output Offset
Voltage
Output Voltage
Fail-Safe Differential Output
Voltage (MAX9169)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
∆VOS
Figures 2, 4, 5, 7, 8, 9
1.5
25
mV
VOS(P-P)
Figures 8, 9 (Note 4)
40
150
mV
VOH
Figures 3, 4, 6, 7
VOL
Figures 3, 4, 6, 7
VOD+
1.65
0.9
IN+, IN- open, undriven and shorted, or
undriven and parallel terminated
V
+250
+350
+450
mV
High-Impedance Output Current
IOZ
EN_ = low, VOUT_+ = +3.6V or 0,
VOUT_- = +3.6V or 0
-0.5
0.01
+0.5
µA
Power-Off Output Current
IOFF
VCC = +1.5V, VOUT_+ = +3.6V or 0,
VOUT_- = +3.6V or 0
-0.5
0.01
+0.5
µA
Output Short-Circuit Current
IOS
VID = +50mV or -50mV,
VOUT+ = 0 or VCC, VOUT- = 0 or VCC
-10
±5.8
+10
mA
VID = +50mV or -50mV, VOD = 0 (Note 5)
5.8
10
mA
OUT_+ or OUT_- to GND (Note 6)
3.6
Magnitude of Differential Output
Short-Circuit Current
Output Capacitance
IOSD
CO
pF
POWER SUPPLY
DC, RL = 100Ω,
Figures 10, 13
Supply Current
ICC
Disabled Supply Current
ICCZ
315MHz (630Mbps),
RL = 100Ω, Figures 10, 13
EN_ = low
MAX9169
22
30
MAX9170
18
25
MAX9169
43
60
MAX9170
41
55
MAX9169
6.8
8.0
MAX9170
4.3
6.4
mA
mA
_______________________________________________________________________________________
3
MAX9169/MAX9170
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, CL = 10pF, EN_ = high, MAX9169 differential input voltage | VID | = 0.15V to 1.2V, LVDS input
common-mode voltage VCM = | VID/2 | to +2.4V - | VID/2 |, TA = -40°C to +85°C, unless otherwise noted. Typical values are at | VID | =
0.2V, VCM = 1.25V, VCC = 3.3V, TA = +25°C for MAX9169. Typical values are at VIN = 0 or VCC, VCC = 3.3V, TA = +25°C for
MAX9170.) (Notes 5, 7, and 8)
MIN
TYP
MAX
UNITS
Rise Time
PARAMETER
SYMBOL
tR
Figures 10–15
CONDITIONS
0.6
0.8
1.2
ns
Fall Time
Added Deterministic Jitter
tF
Figures 10–15
0.6
0.8
1.2
ns
tDJ
(Note 9)
110
200
ps
Added Random Jitter
tRJ
(Note 10)
6
8
ps
MAX9169
2.2
3.5
4.2
MAX9170
1.5
2.6
3.2
MAX9169
2.2
3.5
4.2
MAX9170
1.5
2.6
3.2
Differential Propagation Delay
High to Low
tPHL
Figures 10, 11, 13, 14
Differential Propagation Delay
Low to High
tPLH
Figures 10, 11, 13, 14
tSKEW
Figures 10, 11, 13, 14
40
250
ps
tSK(P)
Figures 10, 12, 13, 15 (Note 11)
40
150
ps
MAX9169, Figures 10, 11, 12
25
120
MAX9170, Figures 13, 14, 15
15
100
MAX9169, Figures 10, 11, 12
0.28
1.2
MAX9170, Figures 13, 14, 15
0.19
1.2
tPHZ
High to high-Z, Figures 16–19
11
15
tPLZ
Low to high-Z, Figures 16–19
11.8
15
tPZH
High-Z to high, Figures 16–19
2.3
10
tPZL
High-Z to low, Figures 16–19
5.8
10
Pulse Skew  tPLH - tPHL
Pulse Skew  tPLH - tPHL
Channel-to-Channel Skew
(Note 12)
tSK(0)
Differential Part-to-Part Skew
(Note 13)
tSK(PP)
Disable Time
Enable Time
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
4
ns
ns
ps
ns
ns
ns
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and ∆VOD.
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Signal generator output for IN+, IN-, or single-ended IN: VIN = 0.4 sin(4E6πt) + 0.5.
All input pulses are supplied by a generator having the following characteristics: tR or tF ≤ 1ns, pulse repetition rate (PRR) =
0.5 Mpps, pulsewidth = 500 ±10ns.
Guaranteed by design and characterization.
Signal generator output for OUT+ or OUT-: VIN = 0.4 sin(4E6πt) + 0.5, EN_ = low.
CL includes scope probe and test jig capacitance.
Signal generator output for differential inputs IN+, IN- (unless otherwise noted): frequency = 50MHz, 49% to 51% duty cycle,
RO = 50Ω, tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for single-ended input IN (unless otherwise noted):
frequency = 50MHz, 49% to 51% duty cycle, RO = 50Ω, VIH = VCC, VIL = 0V, tR = 1.0ns, and tF = 1.0ns (0% to 100%).
Signal generator output for MAX9169 tDJ: VOH = +1.3V, VOL = +1.1V, data rate = 630Mbps, 223 -1 PRBS, RO = 50Ω,
tR = 1.0ns and tF = 1.0ns (0% to 100%). Signal generator output for MAX9170 tDJ: VOH = VCC, VOL = 0V, data rate =
630Mbps, 223 -1 PRBS, RO = 50Ω, tR = 1.0ns, and tF = 1.0ns (0% to 100%).
Signal generator output for MAX9169 tRJ: VOH = +1.3V, VOL = +1.1V, frequency = 315MHz, 50% duty cycle, RO = 50Ω,
tR = 1.0ns, and tF = 1.0ns (0% to 100%). Signal generator output for MAX9170 tRJ: VOH = VCC, VOL = 0V, frequency =
315MHz, 50% duty cycle, RO = 50Ω, tR = 1.0ns, and tF = 1.0ns (0% to 100%).
Signal generator output for MAX9169 tSK(P): VOH = +1.4V, VOL = +1.0V, RO = 50Ω, tR = 1.0ns, and tF = 1.0ns (0% to 100%).
Signal generator output for MAX9170 tSK(P): VOH = +3.0, VOL = 0V, RO = 50Ω, tR = 1.0ns, and tF = 1.0ns (0% to 100%).
tSK(0) is the magnitude of the time difference between tPLH or tPHL of all drivers of a single device with all of their inputs
connected together.
tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
_______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
30
20
3 CHANNELS ACTIVE
2 CHANNELS ACTIVE
20
10
1 CHANNEL ACTIVE
10
30
1 CHANNEL ACTIVE
ALL CHANNELS DISABLED
90
135
180
225
270
240
VCC = 3.0V
45
90
135
180
225
270
315
0
45
90
135
180
225
270
FREQUENCY (MHz)
FREQUENCY (MHz)
TRANSITION TIME
vs. TEMPERATURE
MAX9169 PROPAGATION DELAY
vs. TEMPERATURE
MAX9170 PROPAGATION DELAY
vs. TEMPERATURE
800
tr
tf
780
760
3.7
740
3.6
tPHL
3.5
tPLH
3.4
3.2
10
35
60
85
2.7
tPLH
tPHL
2.6
2.4
-40
-15
TEMPERATURE (°C)
10
35
85
60
-40
-15
10
TEMPERATURE (°C)
85
400
300
950
MAX9169/70 toc08
500
60
TRANSITION TIME
vs. CAPACITIVE LOAD
MAX9169/70 toc07
600
35
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
DIFFERENTIAL OUTPUT VOLTAGE (mV)
2.8
2.5
3.3
720
2.9
315
MAX9169/70 toc06
3.8
PROPAGATION DELAY (ns)
MAX9169/70 toc04
820
-15
VCC = 3.3V
FREQUENCY (MHz)
840
-40
280
200
0
315
MAX9169/70 toc05
45
VCC = 3.6V
320
ALL CHANNELS DISABLED
PROPAGATION DELAY (ns)
0
TRANSITION TIME (ns)
360
0
0
900
TRANSITION TIME (ps)
SUPPLY CURRENT (mA)
2 CHANNELS ACTIVE
4 CHANNELS ACTIVE
MAX9169/70 toc03
3 CHANNELS ACTIVE
40
40
DIFFERENTIAL OUTPUT AMPLITUDE
vs. FREQUENCY
DIFFERENTIAL OUTPUT AMPLITUDE (mV)
4 CHANNELS ACTIVE
SUPPLY CURRENT (mA)
MAX9169/70 toc01
50
MAX9170 SUPPLY CURRENT
vs. FREQUENCY
MAX9169/70 toc02
MAX9169 SUPPLY CURRENT
vs. FREQUENCY
850
tr
800
tf
750
200
700
100
50
75
100
LOAD RESISTOR (Ω)
125
150
5
7
9
11
13
15
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
5
MAX9169/MAX9170
Typical Operating Characteristics
(VCC = 3.3V, RL = 100Ω, CL = 10pF, | VID | = 150mV, VCM = 1.25V, fIN = 50MHz, TA = +25°C, unless otherwise noted.)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
Pin Description
PIN
NAME
FUNCTION
MAX9169
MAX9170
1
1
EN1
OUT1+/OUT1- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN1 high to enable
OUT1+/OUT1-. Set EN1 low to disable OUT1+/OUT1- (high-impedance mode). Integrated
pulldown to GND.
2
2
EN2
OUT2+/OUT2- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN2 high to enable
OUT2+/OUT2-. Set EN2 low to disable OUT2+/OUT2- (high-impedance mode). Integrated
pulldown to GND.
3
3
EN3
OUT3+/OUT3- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN3 high to enable
OUT3+/OUT3-. Set EN3 low to disable OUT3+/OUT3- (high-impedance mode). Integrated
pulldown to GND.
4
4
VCC
Power-Supply Voltage. Bypass with 0.1µF and 0.001µF capacitors to ground.
5
5
GND
Ground
6
—
IN+
Noninverting Differential LVDS Input
7
—
IN-
Inverting Differential LVDS Input
8
8
EN4
OUT4+/OUT4- Enable. +5V tolerant LVTTL/LVCMOS input. Set EN4 high to enable
OUT4+/OUT4-. Set EN4 low to disable OUT4+/OUT4- (high-impedance mode). Integrated
pulldown to GND.
9
9
OUT4-
Inverting Differential LVDS Output
10
10
OUT4+
Noninverting Differential LVDS Output
11
11
OUT3-
Inverting Differential LVDS Output
12
12
OUT3+
Noninverting Differential LVDS Output
13
13
OUT2-
Inverting Differential LVDS Output
14
14
OUT2+
Noninverting Differential LVDS Output
15
15
OUT1-
Inverting Differential LVDS Output
16
16
OUT1+
—
6
IN
—
7
N.C.
Noninverting Differential LVDS Output
Data Input, 5V Tolerant LVTTL/LVCMOS. Integrated pulldown to GND.
No Connection
Table 1. MAX9169 Input/Output Functions
INPUT
6
Table 2. MAX9170 Input/Output Functions
INPUT
OUTPUT
OUTPUT
VID = VIN+ - VIN-
EN_
VOD
VIN
EN_
VOD
X
Low or open
High-Z
X
Low or open
High-Z
+50mV
High
High
High
High
High
-50mV
High
Low
Low
High
Low
Open
High
High
Open
High
Low
Undriven short
High
High
Undriven parallel terminated
High
High
_______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
The MAX9169/MAX9170 outputs use a current-steering
configuration to generate a 2.5mA to 4.5mA output current. This current-steering approach induces less ground
bounce and shoot-through current, enhancing noise
margin and system speed performance. The outputs are
short-circuit current limited and are high impedance
when disabled or when the device is not powered.
The MAX9169/MAX9170 current-steering output requires
a resistive load to terminate the signal and complete the
transmission loop. Because the devices switch the direction of current flow and not voltage levels, the output voltage swing is determined by the value of the termination
resistor multiplied by the output current. With a typical
3.5mA output current, the MAX9169/MAX9170 produce
a 350mV output voltage when driving a transmission line
terminated with a 100Ω resistor (3.5mA ✕ 100Ω =
350mV). Logic states are determined by the direction of
current flow through the termination resistor.
Fail-Safe Circuitry
The fail-safe feature of the MAX9169 sets the outputs
high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when an LVDS driver
output is in high impedance. A shorted input can occur
because of cable failure.
MAX9169/MAX9170
Detailed Description
LVDS is a signaling method for point-to-point and
multidrop data communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and
IEEE 1596.3 standards. LVDS uses a lower voltage swing
than other common standards, achieving higher data
rates with reduced power consumption, while reducing
EMI emissions and system susceptibility to noise.
The MAX9169/MAX9170 are 630Mbps, four-port
repeaters for high-speed, low-power applications. The
MAX9169 accepts an LVDS input and has a fail-safe
input circuit. The MAX9170 features a +5V tolerant single-ended LVTTL/LVCMOS input. Both devices repeat
the input at four LVDS outputs. The MAX9169 detects
differential signals as low as 50mV and as high as 1.2V
over a |VID|/2 to 2.4V - |VID|/2 common-mode range.
The MAX9170’s +5V tolerant LVTTL/LVCMOS input
includes circuitry to hold the decision threshold constant at +1.5V over temperature and supply voltage.
VCC
MAX9169
RIN2
COMPARATOR
OUT1+
VCC - 0.3V
OUT1-
IN+
RIN1/2
RIN1/2
RECEIVER
IN-
OUT4+
OUT4-
Figure 1. MAX9169 Input Fail-Safe Circuit
When the input is driven with signals meeting the LVDS
standard, the input common-mode voltage is less than
V CC - 0.3V and the fail-safe circuit is not activated
(Figure 1). If the input is open, undriven and shorted, or
undriven and parallel terminated, an internal resistor in
the fail-safe circuit pulls both the inputs above VCC 0.3V, activating the fail-safe circuit and forcing the outputs high.
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smaller value capacitor
closest to the VCC pin. Use multiple parallel vias to minimize parasitic inductance.
Traces, Cables, and Connectors
The characteristics of differential input and output connections affect the performance of the MAX9169/
MAX9170. Use controlled-impedance traces, cables,
and connectors with matched characteristic impedance.
Ensure that noise couples as common mode by running the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between traces
of a differential pair to avoid discontinuities in differen-
_______________________________________________________________________________________
7
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
tial impedance. Minimize the number of vias to further
prevent impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
LVDS receiver.
Termination
The MAX9169/MAX9170 LVDS outputs are specified for
a 100Ω load but can drive 90Ω to 132Ω to accommo-
date various types of interconnect. The termination
resistor at the driven receiver should match the differential characteristic impedance of the interconnect and
be located close to the receiver input. Use a ±1% surface-mount termination resistor.
Board Layout
A four-layer PC board with separate layers for power,
ground, and LVDS signals is recommended. Keep
LVTTL/LVCMOS signals separated from the LVDS signals to prevent crosstalk to the LVDS lines.
Test Circuits and Timing Diagrams
OUT1+
MAX9169
10pF
50Ω
VOS
50Ω
OUT1-
50Ω
10pF
IN+
PULSE
GENERATOR
OUT4+
50Ω
IN10pF
VOS
50Ω
50Ω
OUT410pF
Figure 2. MAX9169 Output Offset Voltage Test Circuit
8
_______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
MAX9169
3.75kΩ
OUT1+
VOD
100Ω
0V ≤ VTEST ≤ 2.4V
OUT1-
3.75kΩ
50Ω
IN+
PULSE
GENERATOR
3.75kΩ
OUT4+
IN-
VOD
100Ω
0V ≤ VTEST ≤ 2.4V
50Ω
OUT4-
3.75kΩ
Figure 3. MAX9169 Differential Output Voltage Test Circuit
VCM = ((VIN+) - (VIN-)) / 2
IN0V
DIFFERENTIAL
VID
IN+
OUT_-
VOH
VOS(-)
VOS(+)
VOS(-)
VOL
OUT_+
∆VOS = | (VOS(+)) - (VOS(-)) |
VOD_+
VOD_-
∆VOD = | (VOD_+) - (VOD_-) |
VOD = 0V
(OUT_+) - (OUT_-)
Figure 4. MAX9169 Output DC Parameters
_______________________________________________________________________________________
9
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
4-Port LVDS and LVTTL-to-LVDS Repeaters
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
OUT1+
MAX9170
50Ω
10pF
VOS
50Ω
OUT110pF
OUT4+
IN
PULSE
GENERATOR
50Ω
10pF
50Ω
VOS
50Ω
OUT410pF
Figure 5. MAX9170 Output Offset Voltage Test Circuit
MAX9170
3.75kΩ
OUT1+
VOD
100Ω
0V ≤ VTEST ≤ 2.4V
OUT1-
3.75kΩ
IN
PULSE
GENERATOR
3.75kΩ
OUT4+
50Ω
VOD
100Ω
0V ≤ VTEST ≤ 2.4V
OUT4-
3.75kΩ
Figure 6. MAX9170 Differential Output Voltage Test Circuit
10
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
VIH
IN
VIL
OUT_-
VOH
VOS(-)
VOS(+)
VOS(-)
VOL
OUT_+
∆VOS = | (VOS(+)) - (VOS(-)) |
VOD_+
VOD = 0V
∆VOD = | (VOD_+) - (VOD_-) |
VOD_(OUT_+) - (OUT_-)
Figure 7. MAX9170 LVDS Output DC Parameters
IN-
1.25V
VID = 50mV
1.20V
IN+
∆VOS
VOS(+)
VOS(P-P)
VOS(-)
VOS(-)
Figure 8. MAX9169 Output Offset Voltage Waveforms
3V
IN
0V
∆VOS
VOS(+)
VOS(-)
VOS(P-P)
VOS(-)
Figure 9. MAX9170 Output Offset Voltage Waveforms
______________________________________________________________________________________
11
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
4-Port LVDS and LVTTL-to-LVDS Repeaters
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
MAX9169
CL
10pF
OUT1+
RL
100Ω
OUT1CL
10pF
50Ω
IN+
PULSE
GENERATOR
CL
10pF
OUT4+
INRL
100Ω
50Ω
OUT4-
CL
10pF
Figure 10. MAX9169 Propagation Delay and Transition Time Test Circuit
INVCM
0V
DIFFERENTIAL
VID
VCM =
(VIN+) - (VIN-)
2
IN+
tPHL
tPLH
80%
80%
0V
VOD
VOD = (VOUT_+) - (VOUT_-)
0V
20%
20%
tR
tF
Figure 11. MAX9169 Propagation Delay and Transition Time Waveforms
12
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
IN-
1.4V
VCM = 1.2V
VCM = 1.2V
1.0V
IN+
tPHL
tPLH
80%
80%
VOD = (VOUT_+) - (VOUT_-)
0V
0V
20%
20%
VOD
tR
tF
Figure 12. MAX9169 Propagation Delay and Transition Time Waveforms, tSK(p)
MAX9170
CL
10pF
OUT1+
RL
100Ω
OUT1CL
10pF
IN
PULSE
GENERATOR
CL
10pF
OUT4+
RL
100Ω
50Ω
CL
10pF
OUT4-
Figure 13. MAX9170 Propagation Delay and Transition Time Test Circuit
______________________________________________________________________________________
13
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
Test Circuits and Timing Diagrams (continued)
VCC
IN
VCC/2
VCC/2
0V
tPHL
tPLH
80%
80%
VOD = (VOUT_+) - (VOUT_-)
0V
VOD
0V
20%
20%
tR
tF
Figure 14. MAX9170 Propagation Delay and Transition Time Waveforms
3.0V
IN
1.5V
1.5V
0V
tPHL
tPLH
80%
80%
VOD = (VOUT_+) - (VOUT_-)
0V
VOD
0V
20%
20%
tR
tF
Figure 15. MAX9170 Propagation Delay and Transition Time Waveforms, tSK(p)
14
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
MAX9169
CL
10pF
1.25V
1.20V
1.25V
50Ω
IN+
INCL
10pF
1.20V
PULSE
GENERATOR
OUT_+
50Ω
1.2V
OUT_-
EN_
50Ω
Figure 16. MAX9169 Enable and Disable Time Test Circuit
MAX9170
CL
10pF
2.0V
50Ω
IN
0.8V
CL
10pF
PULSE
GENERATOR
OUT_+
50Ω
1.2V
OUT_-
EN_
50Ω
Figure 17. MAX9170 Enable and Disable Time Test Circuit
______________________________________________________________________________________
15
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
4-Port LVDS and LVTTL-to-LVDS Repeaters
MAX9169/MAX9170
Test Circuits and Timing Diagrams (continued)
3V
EN_
1.5V
1.5V
OV
tPHZ
tPZH
~1.4V
1.25V
VOUT_+ WHEN VID = +50mV
VOUT_- WHEN VID = -50mV
1.25V
1.2V
1.2V
VOUT_+ WHEN VID = -50mV
VOUT_- WHEN VID = +50mV
1.15V
1.15V
~1.0V
tPZL
tPLZ
Figure 18. MAX9169 Enable and Disable Time Waveforms
3V
EN_
1.5V
1.5V
OV
tPZH
tPHZ
~1.4V
1.25V
1.25V
VOUT_+ WHEN VIN = 2.0V
VOUT_- WHEN VIN = 0.8V
1.2V
1.2V
VOUT_+ WHEN VIN = 0.8V
VOUT_- WHEN VIN = 2.0V
1.15V
tPLZ
1.15V
tPZL
~1.0V
Figure 19. MAX9170 Enable and Disable Time Waveforms
16
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
TOP VIEW
MAX9169
MAX9170
EN1 1
16
OUT1+
EN1 1
16
OUT1+
EN2 2
15
OUT1-
EN2 2
15
OUT1-
EN3 3
14
OUT2+
EN3 3
14
OUT2+
VCC 4
13
OUT2-
VCC 4
13
OUT2-
GND 5
12
OUT3+
GND 5
12
OUT3+
IN+ 6
11
OUT3-
IN 6
11
OUT3-
IN- 7
10
OUT4+
N.C. 7
10
OUT4+
EN4 8
9
OUT4-
EN4 8
9
OUT4-
TSSOP/SO
TSSOP/SO
Chip Information
TRANSISTOR COUNT: 1187
PROCESS: CMOS
______________________________________________________________________________________
17
MAX9169/MAX9170
Pin Configurations
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9169/MAX9170
4-Port LVDS and LVTTL-to-LVDS Repeaters
18
______________________________________________________________________________________
4-Port LVDS and LVTTL-to-LVDS Repeaters
16L SOIC.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9169/MAX9170
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)