19-6224; Rev 2; 3/12 Spread-Spectrum EconOscillator The DS1086 EconOscillator™ is a programmable clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 260kHz to 133MHz. The selectable dithered output reduces radiated-emission peaks by dithering the frequency 2% or 4% below the programmed frequency. The DS1086 has a power-down mode and an output-enable control for power-sensitive applications. All the device settings are stored in nonvolatile (NV) EEPROM memory allowing it to operate in stand-alone applications. Applications Printers Features o User-Programmable Square-Wave Generator o Frequencies Programmable from 260kHz to 133MHz o 2% or 4% Selectable Dithered Output o Glitchless Output-Enable Control o 2-Wire Serial Interface o Nonvolatile Settings o 5V Supply o No External Timing Components Required o Power-Down Mode Copiers PCs o 10kHz Master Frequency Step Size Computer Peripherals o EMI Reduction Cell Phones Ordering Information Cable Modems PART DS1086U TEMP RANGE PIN-PACKAGE 0°C to +70°C 8 µSOP DS1086U+ 0°C to +70°C 8 µSOP DS1086Z 0°C to +70°C 8 SO DS1086Z+ 0°C to +70°C 8 SO Note: Contact the factory for custom settings. +Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration Typical Operating Circuit MICROPROCESSOR XTL1/OSC1 XTL2/OSC2 VCC DITHERED 260kHz TO 133MHz OUTPUT VCC N.C. OUT SCL* SPRD SDA* DS1086 VCC PDN GND OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. TOP VIEW OUT 1 8 SCL 7 SDA 3 6 PDN GND 4 5 OE SPRD 2 DS1086 VCC µSOP/SO EconOscillator is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1086 General Description DS1086 Spread-Spectrum EconOscillator ABSOLUTE MAXIMUM RATINGS Voltage on VCC Relative to Ground ......................-0.5V to +6.0V Voltage on SPRD, PDN, OE, SDA, SCL Relative to Ground (See Note 1).......-0.5 to (VCC + 0.5V) Continuous Power Dissipation (TA = +70°C) µSOP (derate 4.5mW/°C above +70°C)........................362mW SO (derate 5.9mW/°C above +70°C) .........................470.6mW Note 1: Junction Temperature ......................................................+150°C Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature (reflow) Lead(Pb)-free................................................................+260°C Containing lead(Pb) .....................................................+240°C This voltage must not exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER Supply Voltage SYMBOL (Note 1) MIN TYP 4.75 5.00 MAX UNITS 5.25 V VIH 0.7 x VCC VCC + 0.3 V Low-Level Input Voltage (SDA, SCL) VIL -0.3 0.3 x VCC V High-Level Input Voltage (SPRD, PDN, OE) VIH 2 VCC + 0.3 V Low-Level Input Voltage (SPRD, PDN, OE) VIL -0.3 0.8 V MAX UNITS High-Level Input Voltage (SDA, SCL) VCC CONDITIONS DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS High-Level Output Voltage (OUT) VOH IOH = -4mA, VCC = min Low-Level Output Voltage (OUT) VOL IOL = 4mA MIN TYP 2.4 V 0.4 V 1 µA High-Level Input Current IIH VCC = 5.25V Low-Level Input Current Supply Current (Active) IIL VIL = 0V ICC CL = 15pF (output at default frequency) 35 mA Power-down mode 35 µA Standby Current (Power-Down) 2 ICCQ -1 _______________________________________________________________________________________ µA Spread-Spectrum EconOscillator DS1086 MASTER OSCILLATOR CHARACTERISTICS (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER Master Oscillator Range Default Master Oscillator Frequency SYMBOL fOSC CONDITION (Note 2) MIN TYP 66 f0 MAX UNITS 133 MHz 97.1 MHz Master Oscillator Frequency Tolerance ∆f0 f0 VCC = 5V, TA = +25°C (Notes 3,17) Default frequency (f0) -0.75 +0.75 DAC step size -0.75 +0.75 Voltage Frequency Variation ∆fV f0 Over voltage range, TA = +25°C (Note 4) Default frequency -0.75 +0.75 DAC step size -0.75 +0.75 ∆fT f0 Over temperature range, VCC = 5V (Note 5) Default frequency -0.5 +0.5 Temperature Frequency Variation 133MHz -0.5 +0.5 66MHz -1.0 Dither Frequency Range ∆f f0 Prescaler bit J0 = 1 (Note 6) 2 Prescaler bit J0 = 0 (Note 6) 4 Integral Nonlinearity of Frequency DAC INL % Entire range (Note 7) DAC Step Size ∆ between two consecutive DAC values (Note 8) DAC Span Frequency range for one offset setting (see Table 2) % % +1.0 -0.4 % +0.4 % 10 kHz 10.24 MHz DAC Default Factory default register setting 500 decimal Offset Step Size ∆ between two consecutive offset values (see Table 2) 5.12 MHz Offset Default Dither Rate OS Factory default OFFSET register setting (5 LSBs) (see Table 2) RANGE (5 LSBs of RANGE register) hex f0/4096 Hz _______________________________________________________________________________________ 3 DS1086 Spread-Spectrum EconOscillator AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS 1 Period 0.2 1 ms 0.1 0.5 ms Frequency Stable After Prescaler Change Frequency Stable After DAC or Offset Change Power-Up Time (Note 9) tpor + tstab (Note 10) Enable of OUT After Exiting Power-Down Mode tstab 500 µs OUT High-Z After Entering Power-Down Mode tpdn 0.1 ms 50 pF Load Capacitance CL (Note 11) 15 Output Duty Cycle (OUT) 40 PDN Rise/Fall Time 60 % 1 µs MAX UNITS 400 100 kHz AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between a STOP and START Condition tBUF Hold Time (Repeated) START Condition tHD:STA LOW Period of SCL tLOW HIGH Period of SCL tHIGH Setup Time for a Repeated START tSU:STA Data Hold Time tHD:DAT Data Setup Time tSU:DAT Rise Time of Both SDA and SCL Signals tR Fall Time of Both SDA and SCL Signals tF 4 CONDITION Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode MIN TYP (Note 12) (Note 12) (Notes 12, 13) (Note 12) (Note 12) (Note 12) (Notes 12, 14, 15) (Note 12) (Note 16) (Note 16) 1.3 µs 4.7 0.6 µs 4.0 1.3 4.7 0.6 4.0 0.6 µs µs µs 4.7 0 0.9 100 250 20 + 0.1CB 300 20 + 0.1CB 1000 ns 20 + 0.1CB 300 20 + 0.1CB 1000 _______________________________________________________________________________________ µs ns ns Spread-Spectrum EconOscillator (VCC = 5V ±5%, TA = 0°C to +70°C.) PARAMETER Setup Time for STOP SYMBOL tSU:STO Capacitive Load for Each Bus Line CB NV Write-Cycle Time tWR Input Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: CI CONDITION MIN Fast mode 0.6 Standard mode 4.0 TYP MAX UNITS µs (Note 16) 5 400 pF 10 ms pF All voltages are referenced to ground. DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range. Correct operation of the device is not guaranteed if these limits are exceeded. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25°C. This is the percentage frequency change from the +25°C frequency due to temperature at VCC = 5V. The maximum temperature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequency (fdefault). The maximum occurs at the extremes of the master oscillator frequency range (66MHz or 133MHz) (see Figure 2). The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. The integral nonlinearity of the frequency adjust DAC is a measure of the deviation from a straight line drawn between the two endpoints of a range. The error is in percentage of the span. This is true when the prescaler = 1. Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original value to the new value. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. Output voltage swings can be impaired at high frequencies combined with high output loading. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr max VCC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr 121°C/2 ATM Steam/Unbiased Autoclave. _______________________________________________________________________________________ 5 DS1086 AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (continued) Typical Operating Characteristics (VCC = 5.0V, TA = 25°C, unless otherwise noted) SUPPLY CURRENT vs. VOLTAGE 18 18 19 18 16 15 14 17 CURRENT (mA) CURRENT (mA) 16 15 14 16 15 13 13 13 12 12 12 11 11 11 10 10 10 20 30 40 50 60 4.85 4.95 5.05 5.15 5.25 0 100 150 200 250 VOLTAGE (V) PRESCALER SUPPLY CURRENT vs. PRESCALER SUPPLY CURRENT vs. TEMPERATURE WITH OE = 0 SUPPLY CURRENT vs. TEMPERATURE WITH PDN = 0 10 DS1086 toc04 19 18 10 9 8 9 8 7 CURRENT (mA) 16 70°C, 25°C, AND 0°C 14 CURRENT (µA) 7 17 6 5 4 6 5 4 13 3 3 12 2 2 11 1 1 10 0 0 50 TEMPERATURE (°C) 20 15 5.25V 10 4.75 70 5.0V 50 100 150 200 0 0 250 10 20 30 40 50 60 0 70 10 FREQUENCY PERCENT CHANGE vs. SUPPLY VOLTAGE 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 DS1086 toc08 0.6 1.0 FREQUENCY PERCENT CHANGE FROM 25°C 0.8 30 FREQUENCY PERCENT CHANGE vs. TEMPERATURE DS1086 toc07 1.0 20 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 4.75 4.85 4.95 5.05 VOLTAGE (V) 5.15 5.25 0 40 50 TEMPERATURE (°C) TEMPERATURE (°C) PRESCALER FREQUENCY PERCENT CHANGE FROM 5V DS1086 toc06 0 4.75V 14 DS1086 toc05 CURRENT (mA) 19 17 17 6 20 DS1086 toc02 DS1086 toc01 19 SUPPLY CURRENT vs. PRESCALER 20 DS1086 toc03 SUPPLY CURRENT vs. TEMPERATURE 20 CURRENT (mA) DS1086 Spread-Spectrum EconOscillator 10 20 30 40 50 60 70 TEMPERATURE (°C) _______________________________________________________________________________________ 60 70 Spread-Spectrum EconOscillator PIN NAME 1 OUT FUNCTION 2 SPRD 3 VCC Power Supply 4 GND Ground 5 OE Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the master oscillator is still on. 6 PDN Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator is disabled (power-down mode). 7 SDA 2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and can be wire-OR’ed with other open-drain or open-collector interfaces. 8 SCL 2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on falling edges. Oscillator Output Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. MAXIMUM TEMPERATURE VARIATION vs. MASTER FREQUENCY CLOCK SPECTRUM COMPARISON (9kHz BW, PEAK DETECT) RELATIVE AMPLITUDE (dBm) 2.0 -10 -15 DS1086 4% DITHER -20 -25 -30 -35 91 92 93 94 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 66.00 -40 90 DS1086 fig02 DS1086 NO DITHER FREQUENCY % CHANGE FROM 25°C CRYSTAL OSC DS1086 fig01 0 -5 95 82.75 99.50 116.25 133.00 FREQUENCY (MHz) FREQUENCY (MHz) Figure 2. Temperature Variation Over Frequency Figure 1. Clock Spectrum Dither Comparison Stand-Alone Mode Processor-Controlled Mode VCC MICROPROCESSOR 4.7kΩ DITHERED 260kHz TO 133MHz OUTPUT VCC 4.7kΩ SCL OUT SPRD VCC GND SDA DS1086 VCC 2-WIRE INTERFACE VCC N.C. OUT SCL* SPRD SDA* DS1086 VCC PDN GND OE PDN OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) XTL1/OSC1 XTL2/OSC2 VCC DITHERED 260kHz TO 133MHz OUTPUT DECOUPLING CAPACITORS (0.1µF and 0.01µF) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086 NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. _______________________________________________________________________________________ 7 DS1086 Pin Description DS1086 Spread-Spectrum EconOscillator Table 1. Register Summary REGISTER ADDR MSB PRESCALER DAC HIGH DAC LOW OFFSET ADDR RANGE WRITE EE 02h 08h 09h 0Eh 0Dh 37h 3Fh X1 b9 b1 X1 X1 XX BINARY X1 b8 b0 X1 X1 XX XX b7 X0 X1 X1 XX J0 P3 b6 b5 X0 X0 b4 b3 X1 WC b4 b3 NO DATA P2 b4 X0 b2 A2 b2 P1 b3 X0 b1 A1 b1 LSB FACTORY DEFAULT ACCESS P0 b2 X0 b0 A0 b0 11100000b 01111101b 00000000b 111- ----b 11110000b xxx- - - - - b R/W R/W R/W R/W R/W R — — X0 = Don’t care, reads as zero. X1 = Don’t care, reads as one. XX = Don’t care, reads indeterminate. X = Don’t care. Table 2. Offset Settings OFFSET FREQUENCY RANGE (MHz) OS - 6 61.44 to 71.67 OS - 5 66.56 to 76.79 OS - 4 71.68 to 81.91 OS - 3 76.80 to 87.03 OS - 2 81.92 to 92.15 OS - 1 87.04 to 97.27 OS* 92.16 to 102.39 OS + 1 97.28 to 107.51 OS + 2 102.40 to 112.63 OS + 3 107.52 to 117.75 OS + 4 112.64 to 122.87 OS + 5 117.76 to 127.99 OS + 6 122.88 to 133.11 *Factory default setting. OS is the integer value of the 5 LSBs of the RANGE register. Detailed Description A block diagram of the DS1086 is shown in Figure 3. The internal master oscillator generates a square wave with a 66MHz to 133MHz frequency range. The frequency of the master oscillator can be programmed with the DAC register over a two-to-one range in 10kHz steps. The master oscillator range is larger than the range possible with the DAC step size, so the OFFSET register is used to select a smaller range of frequencies over which the DAC spans. The prescaler can then be set to divide the master oscillator frequency by 2 x 8 (where x equals 0 to 8) before routing the signal to the output (OUT) pin. A programmable triangle-wave generator injects an offset element into the master oscillator to dither its output 2% or 4%. The dither is controlled by the J0 bit in the PRESCALER register and enabled with the SPRD pin. The maximum spectral attenuation occurs when the prescaler is set to 1. The spectral attenuation is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This happens because the prescaler’s divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. The external control input, OE, gates the clock output buffer. The PDN pin disables the master oscillator and turns off the clock output for power-sensitive applications*. On power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled, and a constant time interval (for a given frequency setting) from an enable signal to the first output transition. The control registers are programmed through a 2-wire interface and are used to determine the output frequency and settings. Once programmed into EEPROM, since the register settings are NV, the settings only need to be reprogrammed if it is desired to reconfigure the device. *The power-down command must persist for at least two output frequency cycles plus 10µs for deglitching purposes. _______________________________________________________________________________________ Spread-Spectrum EconOscillator DS1086 VCC SDA SCL 2-WIRE INTERFACE EEPROM CONTROL REGISTERS DS1086 DAC OFFSET DAC ADDR RANGE PRESCALER FREQUENCY CONTROL VOLTAGE VOLTAGE-CONTROLLED OSCILLATOR PDN MASTER OSCILLATOR OUTPUT DITHER CONTROL PRESCALER BY 1, 2, 4...256 OUT OE SPRD GND TRIANGLE WAVE GENERATOR DITHER SIGNAL Figure 3. DS1086 Block Diagram The output frequency is determined by the following equation: fOUTPUT = (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE × 10 kHz STEP SIZE) PRESCALER (1) where: min frequency of selected OFFSET range is the lowest frequency (shown in Table 2 for the corresponding offset). DAC value is the value of the DAC register (0 to 1023). Prescaler is the value of 2x where x = 0 to 8. See the Example Frequency Calculations section for a more in-depth look at using the registers. PRESCALER Register The PRESCALER register controls the prescaler (bits P3 to P0) and dither (bit J0). The prescaler divides the master oscillator frequency by 2x where x can be from 0 to 8. Any prescaler value entered that is greater than 8 decodes as 8. The dither applied to the output is controlled with bit J0. When J0 is high, 2% peak dither is selected. When J0 is low, 4% peak dither is selected. DAC HIGH/DAC LOW Register The 2-byte DAC register sets the frequency of the master oscillator to a particular value within the current offset range. Each step of the DAC changes the master oscillator frequency by 10kHz. The first byte is the MSB (DAC HIGH) and the second byte is the LSB (DAC LOW). ________________Register Definitions OFFSET Register The DS1086 registers are used to determine the output frequency and dither amount. A summary of the registers is shown in Table 1. Using the default register settings below, the default output frequency is 97.1MHz. See the Example Frequency Calculations section for an example on how to determine the register settings for a desired output frequency. The OFFSET register determines the range of frequencies that can be obtained for a given DAC setting. The factory default offset is copied into the RANGE register so the user can access the default offset after making changes to the OFFSET register. See Table 2 for OFFSET ranges. Correct operation of the device is not guaranteed outside the range 66MHz to 133MHz. _______________________________________________________________________________________ 9 DS1086 Spread-Spectrum EconOscillator ADDR Register The A0, A1, A2 bits determine the 2-wire slave address. The WC bit determines if the EEPROM is to be written to after register contents have been changed. If WC = 0 (default), EEPROM is written automatically after a WRITE EE command. If WC = 1, the EEPROM is only written when the WRITE EE command is issued. In applications where the register contents are frequently written, the WC bit should be set to 1. Otherwise, it is necessary to wait for an EEPROM write cycle to complete between writing to the registers. This also prevents wearing out the EEPROM. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers are written into the EEPROM, thus locking in the register settings. RANGE Register This read-only register contains a copy of the factoryset offset (OS). This value can be read to determine the default value of the OFFSET register when programming a new master oscillator frequency. WRITE EE Command This command is used to write data from RAM to EEPROM when the WC bit in ADDR register is 1. See the ADDR Register section for more details. Example Frequency Calculations Example #1: Calculate the register values needed to generate a desired output frequency of 11.0592MHz. Since the desired frequency is not within the valid master oscillator range of 66MHz to 133MHz, the prescaler must be used. Valid prescaler values are 2x where x equals 0 to 8 (and x is the value that is programmed into the P3 to P0 bits of the PRESCALER register). Equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler. f fDESIRED = MASTER OSCILLATOR prescaler fMASTER OSCILLATOR = (2) 2X By trial and error, x is incremented from 0 to 8 in Equation 2, finding values of x that yield master oscillator frequencies within the range of 66MHz to 133MHz. Equation 2 shows that a prescaler of 8 (x = 3) and a master oscillator frequency of 88.4736MHz generates our desired frequency. In terms of the device register, x = 3 is programmed in the lower four bits of the PRESCALER register. Writing 03h to the PRESCALER register sets the PRESCALER to 8 (and 4% peak dither). Be aware that the J0 bit also resides in the PRESCALER register. fMASTER OSCILLATOR = fDESIRED x prescaler = fDESIRED x 2X fMASTER OSCILLATOR = 11.0592MHz x 23 = 88.4736MHz (3) Once the target master oscillator frequency has been calculated, the value of offset can be determined. Using Table 2, 88.4736MHz falls within both OS - 1 and OS - 2. However, choosing OS - 1 would be a poor choice since 88.4736MHz is so close to OS - 1’s minimum frequency. On the other hand, OS - 2 is ideal since 88.4736MHz is very close to the center of OS - 2’s frequency span. Before the OFFSET register can be programmed, the default value of offset (OS) SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 START CONDITION 6 7 8 9 1 2 3–7 8 ACK 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED STOP CONDITION OR REPEATED START CONDITION Figure 4. 2-Wire Data Transfer Protocol 10 ______________________________________________________________________________________ Spread-Spectrum EconOscillator The expected output frequency is not exactly equal to the desired frequency of 11.0592MHz. The difference is 450Hz. In terms of percentage, Equation 6 shows that the expected error is 0.004%. The expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables. %ERROREXPECTED = fDESIRED − fEXPECTED × 100 fDESIRED fMASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC value x 10kHz) Valid values of DAC are 0 to 1023 (decimal) and 10kHz is the step size. Equation 4 is derived from rearranging Equation 3 and solving for DAC. MIN FREQUENCY OF SELECTED OFFSET RANGE) 10kHz STEP SIZE (88.4736MHz − 81.92MHz) 10kHz STEP SIZE = 655.36 ≈ 655 (decimal) DAC VALUE = (4) Since the two-byte DAC register is left justified, 655 is converted to hex (028Fh) and bit-wise shifted left six places. The value to be programmed into the DAC register is A3C0h. In summary, the DS1086 is programmed as follows: PRESCALER = 03h (4% peak dither) or 13h (2% peak dither) OFFSET = OS - 2 or 10h (if range was read as 12h) DAC = A3C0h Notice that the DAC value was rounded. Unfortunately, this means that some error is introduced. In order to calculate how much error, a combination of Equation 1 and Equation 3 is used to calculate the expected output frequency. See Equation 5. (MIN FREQUENCY OF SELECTED OFFSET RANGE) + (DAC VALUE x 10kHz STEP SIZE) fOUTPUT = prescaler (81.92MHz) + (655 x 10kHz) fOUTPUT = = 8 88.47MHz = 11.05875MHz 8 11.0592MHz − 11.05875MHz 11.0592MHz 450Hz × 100 = × 100 = 0.004% 11.0592MHz %ERROREXPECTED = Example #2: Calculate the register values needed to generate a desired output frequency of 100MHz. Since the desired frequency is already within the valid master oscillator frequency range, the prescaler is set to divide by 1, and hence, PRESCALER = 00h (for 4% peak dither) or 10h (for 2% peak dither). (7) (fMASTER OSCILLATOR − DAC VALUE = (6) fMASTER OSCILLATOR = 100.0MHz x 20 = 100.0MHz Next, looking at Table 2, OS + 1 provides a range of frequencies centered around the desired frequency. In order to determine what value to write to the OFFSET register, the RANGE register must first be read. Assuming 12h was read in this example, 13h (OS + 1) is written to the OFFSET register. Finally, the DAC value is calculated as shown in Equation 8. (8) DAC VALUE = (100.0MHz − 97.28MHz) = 272.00 (decimal) 10kHz STEP SIZE The result is then converted to hex (0110h) and then left-shifted, resulting in 4400h to be programmed into the DAC register. In summary, the DS1086 is programmed as follows: PRESCALER = 00h (4% peak dither) or 10h (2% peak dither) OFFSET = OS + 1 or 13h (if RANGE was read as 12h) DAC = 4400h (9) (5) fOUTPUT = (97.28MHz) + (272 × 10kHz) = 20 100.0MHz = 100.0MHz 1 ______________________________________________________________________________________ 11 DS1086 must be read from the RANGE register (last five bits). In this example, 12h (18 decimal) was read from the RANGE register. OS - 2 for this case is 10h (16 decimal). This is the value that is written to the OFFSET register. Finally, the two-byte DAC value needs to be determined. Since OS - 2 only sets the range of frequencies, the DAC selects one frequency within that range as shown in Equation 3. DS1086 Spread-Spectrum EconOscillator MSB LSB 1 1 A1 A0 R/W DEVICE ADDRESS REA D/W DEVICE IDENTIFIER A2 IT 0 RIT EB 1 Figure 5. Slave Address SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 6. 2-Wire AC Characteristics Since the expected output frequency is equal to the desired frequency, the calculated error is 0%. _______2-Wire Serial Port Operation 2-WIRE SERIAL DATA BUS The DS1086 communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1086 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figures 4 and 6): • Data transfer can be initiated only when the bus is not busy. 12 • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. ______________________________________________________________________________________ Spread-Spectrum EconOscillator 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1086 can operate in the following two modes: Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1086 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Slave Address Figure 5 shows the first byte sent to the device. It includes the device identifier, device address, and the R/W bit. The device address is determined by the ADDR register. Registers/Commands See Table 1 for the complete list of registers/commands and Figure 7 for an example of using them. __________Applications Information Power-Supply Decoupling To achieve the best results when using the DS1086, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to pins 3 and 4 as possible. Stand-Alone Mode SCL and SDA cannot be left floating when they are not used. If the DS1086 never needs to be programmed incircuit, including during production testing, SDA and SCL can be tied high. The SPRD pin must be tied either high or low. ______________________________________________________________________________________ 13 DS1086 Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1086 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1086 EEPROM is being written to, it is not able to perform additional responses. In this case, the slave DS1086 sends a not acknowledge to any data transfer request made by the master. It resumes normal operation when the EEPROM operation is complete. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. DS1086 Spread-Spectrum EconOscillator TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 LSB 0 1 1 A2* A1* A0* R/W DEVICE IDENTIFIER DEVICE ADDRESS MSB SLAVE ACK b7 READ/ WRITE b5 b4 b3 B0h START 1 0 1 1 0 0 0 0 b2 b1 b0 SLAVE ACK b7 LSB b6 COMMAND/REGISTER ADDRESS EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 0Eh SLAVE SLAVE A) SINGLE BYTE WRITE 1 0 1 10000 00001110 START ACK ACK -WRITE OFFSET REGISTER B) SINGLE BYTE READ -READ OFFSET REGISTER MSB LSB b6 0Eh SLAVE SLAVE 00001110 ACK ACK C) TWO BYTE WRITE -WRITE DAC REGISTER B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK D) TWO BYTE READ -READ DAC REGISTER B0h 08h START 1 0 1 1 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 SLAVE ACK ACK b5 b4 b3 b2 b1 b0 SLAVE ACK STOP DATA DATA OFFSET SLAVE ACK STOP DATA B1h REPEATED START SLAVE ACK 10110001 SLAVE ACK DAC LSB B1h REPEATED START STOP DATA DATA DAC MSB MASTER NACK OFFSET 10110001 SLAVE ACK STOP DATA SLAVE ACK DATA MASTER ACK DAC MSB DAC LSB MASTER NACK STOP *THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER. Figure 7. 2-Wire Transactions Package Information Chip Information SUBSTRATE CONNECTED TO GROUND 14 For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 µSOP U8-1 21-0036 90-0092 8 SO S8-4 21-0041 90-0096 ______________________________________________________________________________________ Spread-Spectrum EconOscillator REVISION NUMBER REVISION DATE 0 10/02 1 9/03 Corrected the dither rate in the Master Oscillator Characteristics table; updated Table 2 2 3/12 Updated the Ordering Information, Absolute Maximum Ratings, and Package Information DESCRIPTION PAGES CHANGED Initial release 3, 8 1, 2, 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 15 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. DS1086 Revision History