FastEdge™ Series CY2PP318 PRELIMINARY 1 of 2:8 Differential Fanout Buffer Features Description The CY2PP318 is a low-skew, low propagation delay 1-to-8 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. • Eight ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50-ps output-to-output skew • < 500-ps device-to-device skew • Less than 10 ps intrinsic jitter • 500-ps propagation delay (typical) • Operation up to 1.5 GHz • PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V • ECL mode supply range: VE E = –2.375V to –3.465V with VCC = 0V • Industrial temperature range: –40°C to 85°C • 28-pin PLCC package • Temperature compensation as 100K ECL The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2PP318 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to eight ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Since the CY2PP318 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP318 delivers consistent, guaranteed performance over different platforms. Pin Configuration Block Diagram Q0 Q0# CLKA CLK_SEL VEE 1 28 27 26 25 24 23 22 21 20 19 CY2PP318 17 18 VCCO Q3# Q3 Q4# Q4 Q5 16 14 Q5# 15 12 13 Q5 Q5# VEE CLK_SEL VCCO Q4# TOP VIEW Q6 2 CLKB CLKB# 10 11 Q 6# Q4 9 Q7 CLKA# VCCO 3 Q3# 8 VCCOVEE 7 Q 7# Q3 6 NC VBB CLKB# 5 Q2 Q2# CLKA CLKA# 4 VCCO CLKB Q1 Q1# Q0 Q 0# Q1 VCCO Q 1# Q2 Q 2# Q6 Q6# VEE Q7 Q7# VBB Cypress Semiconductor Corporation Document #: 38-07501 Rev.*B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 8, 2004 FastEdge™ Series CY2PP318 PRELIMINARY Pin Description[1, 2, 3] Pin Name I/O Type Description 3 VBB O Bias Reference Voltage Output 26 VEE –PWR Power Negative Supply 1, 8, 15, 22 VCCO +PWR Power Positive Supply 28, 2 CLKA,CLKA# I, PD ECL/PECL ECL/PECL Differential Input Clocks 4,5 CLKB,CLKB# I, PD ECL/PECL ECL/PECL Differential Input Clocks 27 CLK_SEL I, PD ECL/PECL ECL/PECL Input Clock Select 6 NC 25,23,20,18,16,13,11,9 Q(0:7) O/OE ECL/PECL ECL/PECL Differential Output Clocks 24,21,19,17,14,12,10,7 Q(0;7)# O/OE ECL/PECL ECL/PECL Differential Output Clocks No Connect Table 1. Control Operation CLK_SEL 0 Default condition (no connection to the pin) 0 CLKA, CLKA# input pair is active. CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations 1 CLKB, CLKB# input pair is active. CLKB can be driven with ECL- or PECL-compatible signals with respective power configurations Governing Agencies The following agencies provide specifications that apply to the CY2PP318. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name Specification JEDEC JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–A (skew,jitter) IEEE 1596.3 (Jitter specs) UL 94 (Flammability Rating) Mil-Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, PC for Pull-Center, O for output, OS for open emitter and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode when VCC is +3.3V. Document #: 38-07501 Rev.*B Page 2 of 12 FastEdge™ Series CY2PP318 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition VCC Supply Voltage Non-Functional VCC Operating Voltage Functional VBB Output Reference Voltage Relative to VCC IBB Output Reference Current Relative to VBB VTT Output Termination Voltage VIN Input Voltage VOUT LUI Min. Max. Unit –0.3 4.6 VDC 2.5 – 5% 3.3 + 5% VDC VCC – 1.620 VCC – 1.220 VDC 200 uA VCC – 2 VDC VCC + 0.3 VDC VCC + 0.3 VDC Relative to VCC –0.3 Output Voltage Relative to VCC –0.3 Latch Up Immunity Functional TS Temperature, Storage Non-Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C ØJc Dissipation, Junction to Case Functional TBD TBD °C/W ØJa Dissipation, Junction to Ambient Functional 40 60 °C/W ESDh ESD Protection (Human Body Model) 2000 Volts MSL Moisture Sensitivity Level TBD N.A. GATES Total Functional Gate Count Assembled Die 50 Each UL–94 Flammability Rating @ 1/8 in. V0 N.A. FIT Failure in Time Manufacturing test 1 ppm 100 mA Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. PECL DC Electrical Specifications Parameter Description Condition Min. Max. Unit 2.375 2.625 V Control pin CLK_SEL (Single-ended) VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V VCC3.3V 3.3 Operating Voltage 3.3V ± 5%, VEE = 0.0V VIL Input Voltage, Low VIH Input Voltage, High Define VCC and load current IIN Input Current[4] VIN = [VILMIN = 1.655V or VIH max = 2.72V] at VCC = 3.6V 3.135 3.465 V VCC – 1.945 VCC – 1.625 V VCC – 1.165 VCC – 0.880 V l150l uA Clock Input Pair CLKA,CLKA#,CLKB,CLKB#,CLK_SEL (PECL Differential Signals) VPP Differential Input Voltage[5] Differential operation 0.1 1.3 V VCMR Differential Cross Point Voltage[6] Differential operation 1.2 VCC V l150l uA IIN Input Current[4] VIN = [VILMIN = 1.655V or VIH max = 2.72V] at VCC = 3.6V PECL Outputs Q(0:7), Q(0:7)# (PECL Differential Signals) VOH Output High Voltage IOH = –30 mA[7] VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 ma[7] VCC – 1.2 VCC – 0.7 V VCC – 1.945 VCC –1.945 VCC – 1.5 VCC – 1.3 V Notes: 4. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. Equivalent to a termination of 50Ω to VTT. Document #: 38-07501 Rev.*B Page 3 of 12 PRELIMINARY FastEdge™ Series CY2PP318 PECL DC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 100 mA Supply Current and VBB IEE Maximum Quiescent Supply Current without output termination current[8] VEE pin VBB[9] Output reference voltage IBB = 200 µA[6] VCC – 1.620 VCC – 1.220 V IPUP Internal Pull-up Current Define VIL and state TBD TBD mA IPDWN Internal Pull-down Current Define VIH and state TBD TBD mA CIN Input pin capacitance 3 pF LIN Pin Inductance ZOUT Output impedance 1 nH TBD 30 Ω Min. Max. Unit ECL DC Electrical Specifications Parameter Description Condition Control pin CLK_SEL (Single-ended) VEE –2.5 Negative Power Supply –2.5V ± 5%, VEE = 0.0V –2.375 –2.625 V VEE –3.3 Negative Power Supply –3.3V ± 5%, VEE = 0.0V –3.135 –3.465 V VIL Input Voltage, Low –1.945 –1.625 V VIH Input Voltage, High –1.165 –0.880 V l150l uA 1.3 V IIN Input Define VCC and load current Current[4] VIN = VIL or Vin = VIH Clock input pair CLKA,CLKA#,CLKB,CLKB#,CLK_SEL (ECL Differential Signals) VPP Differential input voltage[5] VCMR Differential cross point IIN Input Current[4] voltage[6] Differential operation 0.1 Differential operation VEE + 1.2 0V V l150l uA –1.2 –0.7 V –1.945 –1.945 –1.5 –1.3 V 100 mA VIN = VIL or VIN = VIH ECL Outputs Q(0:7), Q(0:7)# (ECL Differential Signals) VOH VOL Output High Voltage Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOH = –30 mA[7] IOL = –5 ma[7] Supply Current and VBB Control pin CLK_SEL (Single-ended) IEE Maximum Quiescent Supply Current without output termination current[8] VEE pin Output reference voltage IBB = 200 uA –1.620 –1.220 V VBB Notes: 8. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH – VTT)/Rload + (VOL–-VTT)/Rload +IEE. 9. VBB is limited to VCC of 3.3V only. See Note 11. Document #: 38-07501 Rev.*B Page 4 of 12 FastEdge™ Series CY2PP318 PRELIMINARY AC Electrical Specifications Parameter Description Condition Min. Max. Unit Differential operation 0.1 1.3 V Differential operation VEE + 1.2 Clock Input Pair CLKA,CLKA#,CLKB,CLKB# (ECL Differential Signals) VPP Differential Input Voltage[10] Voltage[11] VCMR Differential Cross Point FCLK Input Frequency[12] 50% duty cycle Standard load TPD Propagation Delay CLKA or CLKB to Q0-Q7 pair 660-MHz 50% duty cycle Standard load Differential Operation VCC V 2200 MHz 650 ps 0.8 V 50 ps 400 ECL/PECL Clock Outputs Q(0:7), Q(0:7)# (Differential Signal) Vo(P-P) Differential Output Voltage (peak-to-peak) VCMR Common Voltage Range (typical) tsk(0) Output-to-output Skew 660-MHz 50% duty cycle Standard load Differential Operation 20 tsk(PP) Output-to-output Skew (part-to-part) 660-MHz 50% duty cycle Standard load Differential Operation TBD TCCJ Output Cycle-to-cycle Jitter (Intrinsic) 660-MHz 50% duty cycle Standard load Differential Operation TBD TBD ps tsk(P) Output Pulse Skew[13] 660-MHz 50% duty cycle Standard load Differential Operation TBD 35 ps TR,TF Output Rise/Fall Time 660-MHz 50% duty cycle Differential 20% to 80% TBD 0.3 ps TTB Total Timing Budget 660-MHz 50% duty cycle Standard load 100 200 ps Dj Deterministic/Intrinsic Jitter 660-MHz 50% duty cycle Standard load TBD 2 ps r.m.s. Differential PRBS of < 50 MHz of < 0.8 MHz of < 1.0 MHz 0.45 0.4 0.375 VCC – 1.425 V ps Timing Definitions VCC VCC = 3.3V VCM R M ax = VCC VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCM R M in = 1.2V VEE VEE = 0.0V Figure 1. PECL Waveform Definitions Notes: 10. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 11. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 12. The CY2PP318 is fully operation up to 1.5 GHz. 13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07501 Rev.*B Page 5 of 12 FastEdge™ Series CY2PP318 PRELIMINARY VCC V C C = 0 .0 V VCM R m ax = 0 V IH VPP VCMR V P P r a n g e = 0 .1 to 1 .3 V V IL V C M R m in = V E E - 1 .2 V V E E = - 2 .5 V o r - 3 .3 V VEE Figure 2. ECL Differential Waveform Definitions tr, tf, 20-80% VO Figure 3. ECL/LVPECL Output V0 TPD V0 Figure 4. TPD Propagation Delay of Both CLKA or CLKB to Q0–Q7 Pair PECL/ECL to PECL/ECL Document #: 38-07501 Rev.*B Page 6 of 12 FastEdge™ Series CY2PP318 PRELIMINARY VDIF tPLH tPHL VO tsk(P) Output pulse skew = | tPLH - tPHL | Figure 5. Output Pulse Skew VDIF Qn VO tsk(0) Qn+m VO Figure 6. Output-to-output Skew Document #: 38-07501 Rev.*B Page 7 of 12 FastEdge™ Series CY2PP318 PRELIMINARY Test Configurations Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT RT = 50 ohm RT = 50 ohm P u ls e G e n e ra to r Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" DUT C Y2PP318 RT = 50 ohm RT = 50 ohm VTT VTT Figure 7. CY2PP318 AC Test Reference Applications Information Termination Examples CY2PP318 1 .3 V V C C = 3 .3 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm 1 .3 V VEE = 0V Figure 8. Standard LVPECL – PECL Output Termination CY2DP318 -2 V V C C = 0 .0 V RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm -2 V V E E = -3 .3 V Figure 9. Standard ECL Output Termination Document #: 38-07501 Rev.*B Page 8 of 12 FastEdge™ Series CY2PP318 PRELIMINARY CY2PP318 VTT RT = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm VBB VEE Figure 10. Driving a PECL/ECL Single-ended Input CY2PP318 3 .3 V V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 11. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface Document #: 38-07501 Rev.*B Page 9 of 12 PRELIMINARY FastEdge™ Series CY2PP318 Evaluation Material Figure 12. Demonstration PCB Ordering Information Part Number Package Type Product Flow CY2PP318JI 28-pin PLCC Industrial, –40° to 85°C CY2PP318JIT 28-pin PLCC – Tape and Reel Industrial, –40° to 85°C Document #: 38-07501 Rev.*B Page 10 of 12 PRELIMINARY FastEdge™ Series CY2PP318 Package Drawing and Dimensions 28-lead Plastic Leaded Chip Carrier J64 51-85001-*A FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07501 Rev.*B Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. FastEdge™ Series CY2PP318 PRELIMINARY Document History Page Document Title: CY2PP318 FastEdge™ Series 1 of 2:8 Differential Fanout Buffer Document Number: 38-07501 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 122041 02/13/03 RGL New Data Sheet *A 125923 06/11/03 RGL Shifted the pin location Changed the title (ComLink to FastEdge) Corrected Specs that does not match EROS/IROS *B 204240 See ECN RGL Change pin 1 from VCC to VCCO Document #: 38-07501 Rev.*B Page 12 of 12