CY241V08-01,-04,-05,-06 PRELIMINARY MPEG Clock Generator with VCXO Features • • • • Advance Features Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3V operation • Lower drive strength settings (CY241V08-04, -06) Benefits • Electromagnetic interference (EMI) reduction for standards compliance Benefits • Highest-performance PLL tailored for multimedia applications • Meets critical timing requirements in complex system designs • Application compatibility for a wide variety of designs Frequency Table Part Number Outputs CY241V08-01 1 13.5-MHz pullable crystal input One copy of 27 MHz linear per Cypress specification Pinout compatible with MK3727 CY241V08-04 1 13.5-MHz pullable crystal input One copy of 27 MHz linear per Cypress specification Same as CY241V08-01 except lower drive strength settings CY241V08-05 1 13.5-MHz pullable crystal input One copy of 27 MHz nonlinear per Cypress specification Mimics MK3727 nonlinear VCXO Control Curve CY241V08-06 1 13.5-MHz pullable crystal input One copy of 27 MHz nonlinear per Cypress specification Same as CY241V08-05 except lower drive strength settings Input Frequency Range Output Frequencies VCXO Control Curve Other Features Block Diagram 13.5 XIN OSC PLL OUTPUT DIVIDER 27 MHz XOUT VCXO VDD VSS Pin Configuration CY241V08-01,-04,-05,-06 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC or VSS 3 6 NC or VDD VSS 4 5 27 MHz Cypress Semiconductor Corporation Document #: 38-07520 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2003 PRELIMINARY CY241V08-01,-04,-05,-06 Pin Descriptions for CY241V08 –01, –04, –05, –06 Name Pin Number Description XIN 1 Reference crystal input VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No connect or voltage supply NC/VSS 7 No connect or ground XOUT 8 Reference crystal output Absolute Maximum Conditions Supply Voltage (VDD) ........................................–0.5 to +7.0V Data Retention @ Tj = 125°C................................> 10 years DC Input Voltage...................................... –0.5V to VDD + 0.5 Package Power Dissipation...................................... 350 mW Storage Temperature (Non-condensing).....–55°C to +125°C ESD (Human Body Model) MIL-STD-883................. > 2000V Junction Temperature ................................ –40°C to +125°C (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications[1] Parameter Description FNOM Nominal crystal frequency CLNOM Nominal load capacitance Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut – 13.5 – MHz – 14 – pF R1 Equivalent series resistance (ESR) Fundamental mode – – 25 Ω R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 values to fundamental mode ESR are much less than the maximum spec 3 – – – DL Crystal drive level No external series resistor assumed – – 150 µW F3SEPHI Third overtone separation from 3*FNOM High side 400 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – -200 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 – C1 Crystal motional capacitance 14.4 18 21.6 fF Recommended Operating Conditions Parameter Description VDD Operating Voltage Min. Typ. Max. Unit 3.135 3.3 3.465 V TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Note: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. Document #: 38-07520 Rev. *A Page 2 of 6 PRELIMINARY CY241V08-01,-04,-05,-06 DC Electrical Specifications Parameter Name Description Min. Typ. Max. Unit IOH Output HIGH Current –001, –005 VOH = VDD – 0.5V, VDD = 3.3V 12 24 – mA IOL Output LOW Current –001, –005 VOL = 0.5V, VDD = 3.3V 12 24 – mA IOH Output HIGH Current –004, –006 VOH = VDD – 0.5V, VDD = 3.3V 6 18 – mA IOL Output LOW Current –004, –006 VOL = 0.5V, VDD = 3.3V 6 18 – mA CIN Input Capacitance Except XIN, XOUT pins VVCXO VCXO Input Range f∆XO VCXO Pullability Range IVDD Supply Current – – 7 pF 0 – VDD V ±150 – – ppm – 30 35 mA AC Electrical Specifications (VDD = 3.3V)[2] Parameter[2] Name Description Min. Typ. Max. Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 55 % ER Rising Edge Rate –001, –005 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns EF Falling Edge Rate –001, –005 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns ER Rising Edge Rate –004, –006 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.7 1.1 – V/ns EF Falling Edge Rate –004, –006 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.7 1.1 – V/ns t9 Clock Jitter –001, –005 Peak-to-peak period jitter – 140 – ps t9 Clock Jitter –004, –006 Peak-to-peak period jitter – 150 – ps t10 PLL Lock Time – – 3 ms Test and Measurement Setup VDD Outputs 0.1 µF DUT CLOAD GND Note: 2. Not 100% tested. Document #: 38-07520 Rev. *A Page 3 of 6 PRELIMINARY CY241V08-01,-04,-05,-06 Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage Features CY241V08SC-01 S8 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V08SC-01T S8 8-pin SOIC – Tape and Reel Commercial 3.3V Linear VCXO control curve CY241V08SC-04 S8 8-pin SOIC Commercial 3.3V Lower drive strength version of CY241V08-01 CY241V08SC-04T S8 8-pin SOIC – Tape and Reel Commercial 3.3V Lower drive strength version of CY241V08-01 CY241V08SC-05 S8 8-pin SOIC Commercial 3.3V Mimics nonlinear MK3727 VCXO control curve CY241V08SC-05T S8 8-pin SOIC – Tape and Reel Commercial 3.3V Mimics nonlinear MK3727 VCXO control curve CY241V08SC-06 S8 8-pin SOIC Commercial 3.3V Lower drive strength version of CY241V08-05 CY241V08SC-06T S8 8-pin SOIC – Tape and Reel Commercial 3.3V Lower drive strength version of CY241V08-05 Document #: 38-07520 Rev. *A Page 4 of 6 PRELIMINARY CY241V08-01,-04,-05,-06 Package Drawing and Dimensions 8-lead (150-Mil) SOIC – S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] 5 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0138[0.350] 0.0192[0.487] 0.0075[0.190] 0.0098[0.249] 51-85066-*B All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07520 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY241V08-01,-04,-05,-06 Document History Page Document Title: CY241V08-01,-04,-05,-06 MPEG Clock Generator with VCXO Document Number: 38-07520 Issue Date Orig. of Change REV. ECN NO. ** 123982 03/05/03 CKN *A 128430 07/31/03 IJATMP Document #: 38-07520 Rev. *A Description of Change New Data Sheet Changed “Advance Information” to “Preliminary” on top of every page. Added dashes to empty field in tables. Changed Part numbers Page 6 of 6