CY24204 MediaClock™ DTV, STB Clock Generator Features • • • • Benefits Integrated phase-locked loop (PLL) Low jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation • Internal PLL with up to 400MHz internal operation • Meets critical timing requirements in complex system designs • Large ±150ppm range, better linearity • Enables application compatibility Part Number Outputs Input Frequency Output Frequency Range CY24204-1 3 27-MHz Crystal Input One copy of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.175 MHz (frequency selectable) CY24204-2 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.175 MHz (frequency selectable) CY24204-3 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable) CY24204-4 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased VCXO pull range) CY24204-5 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased output drive strength) Pin Configurations Block Diagram 16-pin TSSOP OSC. Q Φ VCO VCXO OUTPUT MULTIPLEXER AND DIVIDERS P CLK1 CLK2 PLL REFCLK1 REFCLK2 (-2,-3,-4,-5) FS0 XIN 1 16 XOUT VDD 2 15 13 OE FS1 VSS 12 CLK1 AVDD 3 VCXO 4 AVSS 5 VSSL 6 NC REFCLK1 24204-1 XIN XOUT 14 11 VDDL 7 10 FS0 8 9 CLK2 16-pin TSSOP FS1 OE VDD Cypress Semiconductor Corporation Document #: 38-07450 Rev. *A AVDD • AVSS VSS VSSL 3901 North First Street • 1 16 XOUT 2 15 13 OE FS1 VSS 12 CLK1 AVDD 3 VCXO 4 AVSS 5 VSSL 6 REFCLK2 7 REFCLK1 8 24204-2,3,4,5 VDDL XIN VDD 14 11 VDDL 10 FS0 9 CLK2 San Jose, CA 95134 • 408-943-2600 Revised September 8, 2003 CY24204 Frequency Select Options OE FS1 FS0 CLK1/CLK2 (-1,-2)[1] CLK1/CLK2 (-3,-4,-5)[1] REFCLK 1/2 Unit 0 0 0 off off 27 MHz 0 0 1 off off 27 MHz 0 1 0 off off 27 MHz 0 1 1 off off 27 MHz 1 0 0 27 27 27 MHz 1 0 1 27.027 27.027 27 MHz 1 1 0 74.250 74.250 27 MHz 1 1 1 74.175 74.17582418 27 MHz Pin Description Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. VCXO 4 Input Analog Control for VCXO. AVSS 5 Analog Ground. VSSL 6 CLK Ground. N/C (-1) 7 No Connect. REFCLK2 (-2,-3,-4,-5) 7 Reference Clock Output. REFCLK1 8 Reference Clock Output. CLK1 (-1, -2) 9 27-/27.027-/74.250-/74.175-MHz Clock Output (Frequency Selectable). CLK1 (-3,-4,-5) 9 27-/27.027-/74.250-/74.17582418-MHz Clock Output (Frequency Selectable). FS0 10 Frequency Select 0, Weak Internal Pull-up. VDDL 11 CLK Voltage Supply. CLK2 (-1, -2) 12 27-/27.027-/74.250-/74.175-MHz Clock Output (Frequency Selectable). CLK2 (-3,-4,-5) 12 27-/27.027-/74.250-/74.17582418-MHz Clock Output (Frequency Selectable). VSS 13 Ground. FS1 14 Frequency Select 1, Weak Internal Pull-up. OE 15 Output Enable, Weak Internal Pull-up. XOUT 16 Reference Crystal Output. Note: 1. “off” = output is driven high. Document #: 38-07450 Rev. *A Page 2 of 6 CY24204 Data Retention @ Tj=125°C..................................> 10 years Absolute Maximum Conditions Package Power Dissipation...................................... 350 mW Supply Voltage (VDD, AVDDL, VDDL)..................–0.5 to +7.0V ESD (Human Body Model) MIL-STD-883.................... 2000V DC Input Voltage...................................... –0.5V to VDD + 0.5 (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-Condensing) .... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Pullable Crystal Specifications Parameter Description Comments Min. FNOM Nominal crystal frequency Parallel resonance, fundamental mode, AT cut CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec DL Crystal drive level No external series resistor assumed F3SEPHI Third overtone separation from 3*FNOM High side F3SEPLO Third overtone separation from 3*FNOM Low side C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance 180 C1 Crystal motional capacitance 14.4 Typ. Max. Unit 27.0 MHz 14 pF 25 Ω 2 mW 3 0.5 300 ppm –150 ppm 7 pF 250 18 21.6 fF Recommended Operating Conditions Parameter Description VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDD‘s to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 0.05 70 °C 15 pF 500 ms DC Electrical Specifications Parameter[2] Min. Typ. IOH1 Output High Current for -1,-2,-3,-4 Name VOH = VDD – 0.5, VDD/VDDL = 3.3V Description 12 24 Max. Unit mA IOL1 Output Low Current for -1,-2,-3,-4 VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA IOH2 Output High Current for -5 VOH = VDD – 0.5, VDD/VDDL = 3.3V 18 26 mA IOL2 Output Low Current for -5 VOL = 0.5, VDD/VDDL = 3.3V 18 26 VIH Input High Voltage CMOS levels, 70% of VDD 0.7 VIL Input Low Voltage CMOS levels, 30% of VDD 0.3 VDD IVDD Supply Current AVDD/VDD Current 25 mA IVDDL Supply Current VDDL Current (VDDL = 3.47V) 20 mA CIN Input Capacitance 7 pF f∆XO VCXO pullability range Nominal pullability for -1,-2,-3,-5 f∆XO VCXO pullability range Extended pullability for -4 VVCXO VCXO input range RUP Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured at VIN = 0V mA VDD ±150 ppm ±200 0 100 ppm VDD V 150 kΩ Note: 2. Not 100% tested. Document #: 38-07450 Rev. *A Page 3 of 6 CY24204 AC Electrical Specifications Parameter[2] Description Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 45 50 55 % ER1 Rising Edge Rate for -1,-2,-3,-4 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 V/ns EF1 Falling Edge Rate for -1,-2,-3,-4 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 V/ns ER2 Rising Edge Rate for -5 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 1.0 1.8 V/ns EF2 Falling Edge Rate for -5 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 1.0 1.8 V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter t10 PLL Lock Time 120 ps 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Document #: 38-07450 Rev. *A Page 4 of 6 CY24204 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24204ZC-1 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-1T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-2 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-2T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-3 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-3T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-4 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-4T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-5 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-5T Z16 16-Pin TSSOP Commercial 3.3V Package Drawing and Dimensions 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07450 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24204 Document History Page Document Title: CY24204 MediaClock™ DTV, STB Clock Generator Document Number: 38-07450 REV. ECN NO. Issue Date Orig. of Change ** 123842 04/10/03 CKN *A 128775 09/0803 IJA Document #: 38-07450 Rev. *A Description of Change New Data Sheet Added -4 and -5 parts Page 6 of 6