Ordering number : ENN*5926A CMOS IC LC87F65C8A 8-Bit Single Chip Microcontroller with 128KB ROM and 2048 Byte RAM On Chip Preliminary Overview The LC876572A/64A is an 8 bit single chip microcontroller with the following on-chip functional blocks : - CPU: operable at a minimum bus cycle time of 100 ns - 128K bytes flash ROM(rewriteable on-board) - On-chip RAM: 2048 bytes - VFD automatic display controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / PWM (can be divided into two 8 bit timers) - timer for use as date / time clock - synchronous serial I/O port (with automatic block transmit / receive function) - asynchronous / synchronous serial I/O port - 12-channel × 8-bit AD converter - Weak signal detector - 15-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Read-Only Memory (Flash ROM) -single 5V power supply, writeable on-board -block erase in 128 byte units -131072 × 8bits (LC87F65C8A) (2) Random Access Memory (RAM): 2048 × 9 bits (LC87F65C8A) Ver.1.07 12000 91400 RM (IM) SK-1/24 LC87F65C8A (3) Minimum Bus Cycle Time: 100 ns (10 MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time: 300 ns (10MHz) (5) Ports - Input/output ports Data direction programmable for each bit individually : 20 (P1n, P70 to P73, P8n) - 15V withstand input/output ports Data direction programmable in nibble units : 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) Data direction programmable for each bit individually : 8 (P3n) - Input ports : 2 (XT1,XT2) - VFD output ports Large current outputs for digits : 9 (S0 / T0 to S8 / T8) Large current outputs for digits / segments : 7 (S9 / T9 to S15 / T15) digit / segment outputs : 8 (S16 to S23) segment outputs : 28 (S24 to S51) Other functions Input/output ports : 12(PFn, PG0 to 3) Input ports : 24 (PCn, PDn, PEn) - Oscillator pins : 2 (CF1,CF2) - Reset pin : 1 (RES#) - Power supply : 6 (VSS1 to 2, VDD1 to4) - VFD power supply : 1 (VP) (6) VFD automatic display controller - Programmable segment/digit output pattern Output can be switched between digit/segment waveform output (pins 9–24 can be used for output of digit waveforms. parallel-drive available for large current VFD. - 16-step dimmer function available (7) Weak signal detection (MIC signals etc) - Counts pulses with width greater than a preset value - 2 bit counter (8) Timers - Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer 1: PWM / 16 bit timer toggle output Mode 0: 2 channel 8 bit timer (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Base Timer 1) The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts can be selected to occur at one of five different times. 2/24 LC87F65C8A (9) Serial-interface - SIO 0: 8 bit synchronous serial Interface 1) LSB first / MSB first function available 2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc) 3) Continuous automatic data communication (1-256 bits) - SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (10) AD converter -8 bits × 12 channels (11) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal) -Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc) (12) Watchdog timer - The watching timer period is set using an external RC. - Watchdog timer can produce interrupt, system reset (13) Interrupts: 15-source, 10-vectored interrupts 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. (14) Subroutine stack levels: 1024 levels max. Stack is located in RAM. (15) Multiplication and division - 16 bit × 8 bit (executed in 5 cycles) - 24 bit × 16 bit (12 cycles) - 16 bit ÷ 8 bit (8 cycles) - 24 bit ÷ 16 bit (12 cycles) (16) Oscillation circuits - On-chip RC oscillation circuit for system clock use. - On-chip CF oscillation circuit for system clock use. (Rf built in) - On-chip Crystal oscillation circuit low speed system clock use. (Rd, Rf external) (17) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate but VFD display and some serial transfer operations stop. 1) Oscillation circuits are not stopped automatically. 2) Release occurs on system reset or by interrupt. -HOLD mode HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped. 1)CF, RCand crystal oscillation circuits stop automatically. 2) Release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of INT0, INT1, INT2 (3) an interrupt condition arises at port 0 3/24 LC87F65C8A -X’tal HOLD made X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator is maintained in its state at HOLD mode inception. 3) Release occurs on any an any of the following conditions (1) input to the reset pin goes low (2) a specified level is input to at least one of INT0, INT1, INT2 (3) an interrupt condition arises at port 0 (4) an interrupt condition arises at the base-timer (18) Factory shipment - package: QIP100E (19) Development tools - Evaluation chip: LC876096 - Emulator: EVA62S + ECB876500 (Evaluation chip board) + SUB876500 + POD100QFP (20) Same package and pin arrangement as mask ROM version. 1) LC876500 series options can be set using flash ROM data.(But certain options don’t correspond exactly.) Thus testing and evaluation of mass production boards is possible. 2) When using mask ROM software version, the usable ROM/RAM capacity is the same as the mask ROM version. However some options are different. Please note the following points. Differences between LC87F65C8A and LC876500 series options Parameter High voltage terminal pull-down resister option Pins LC87F65C8A LC876500 series mask ROM version S0/T0 – S6/T6 OFF Option can be set S7/T7–S15/T15 ON ON S16–S31 ON ON S32–S47 OFF Option can be set S48–S51 OFF OFF 4/24 P16/T1PWML P17/T1PWMH/BUZ P30 P31 P32 P33 P34 P35 P36 P37 RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN S0/T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 VP LC87F65C8A Pin Assignment S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 SANYO : QIP-100E Package Dimension (unit : mm) 3151 SANYO : QIP-100E 5/24 LC87F65C8A System Block Diagram Interrupt Control IR CF RC Flash ROM Clock Generator Stand-by Control PLA PC X’tal Bus Interface ACC SIO0 Port 0 B Register SIO1 Port 1 C Register Timer 0 Port 3 ALU Timer 1 Port 7 Base Timer Port 8 PSW VFD Controller ADC RAR INT0 - 3 Noise Rejection Filter Weak Signa Detector RAM Stack Pointer Watch Dog Timer 6/24 LC87F65C8A Pin Assignment Pin name I/O Function Option VSS1 VSS2 - • Power supply (-) No VDD1 VDD2 VDD3 VDD4 - • Power supply (+) No - VP • Power supply (-) No PORT0 P00 to P07 I/O • 8bit input/output port • data direction programmable in nibble units • Use of pull-up resistor can be specified in nibble units • Input for HOLD release • Input for port 0 interrupt • 15V withstand at N-channel open drain output Yes PORT1 P10 to P17 I/O • 8bit input/output port • data direction programmable for each bit • Use of pull-up resistor can be specified for each bit • Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output Yes PORT3 P30 to P33 I/O • 8bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit • 15V withstand at N-channel open drain output Yes PORT7 P70 to P73 I/O • 4bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit • Other functions P70: INT0 input/HOLD release input/Timer0L capture Input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input P73: INT3 input(noise rejection filter attached input)/timer 0 event input/Timer0H capture input AD input port: AN8(P70), AN9(P71) The following types of interrupt detection are possible: No INT0 INT1 INT2 INT3 Rising Falling Rising/ falling H level L level Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes No No 7/24 LC87F65C8A Pin name I/O Function description Option I/O • 8bit Input/output port • Input/output can be specified in a bit unit • Other functions: AD input port: AN0 to AN7 Weak signal detector input port: MICIN(P87) No S0/T0 to S8/T8 O • Large current output for VFD display controller digit (can be used for segment) No S9/T9 to S15/T15 O • Large current output for VFD display controller segment/digit No S16 to S23 I/O • Output for VFD display controller segment/digit • Other functions: High voltage input port: PC0 to PC7 No S24 to S31 I/O • Output for VFD display controller segment • Other functions: High voltage input port: PD0 to PD7 No S32 to S39 I/O • Output for VFD display controller segment • Other functions High voltage input port: PE0 to PE7 No S40 to S47 I/O • Output for VFD display controller segment • Other functions: High voltage input/output port: PF0 to PF7 No S48 to S51 I/O • Output for VFD display controller segment • Other functions: High voltage input/output port: PG0 to PG3 No PORT8 P80 to P87 RES I Reset terminal No XT1 I • Input for 32.768kHz crystal oscillation • Other functions: General purpose input port When not in use, connect to VDD1. AD input port: AN10 No XT2 I/O • Output for 32.768kHz crystal oscillation • Other functions: General purpose input port When not in use, set to oscillation mode and leave open circuit. AD input port: AN11 No CF1 I Input terminal for ceramic oscillator No CF2 O Output terminal for ceramic oscillator No 8/24 LC87F65C8A Port Output Configuration Output configuration and pull-up/pull-down resistor options are shown in the following table. Input /output is possible even when port is set to output mode. Terminal P00 to P07 P10 to P17 P30 to P37 Option applies to: Options 1 bit units 1 CMOS 2 15 voltage Nch-open drain 1 each bit each bit Output Format Pull-up resistor Pull-down resistor Programmable (Note 1) – None – CMOS Programmable – 2 Nch-open drain Programmable – 1 CMOS Programmable – 2 15V Nch-open drain None – P70 – None Nch-open drain Programmable – P71 to P73 – None CMOS Programmable – P80 to P87 – None Nch-open drain None – each bit None High voltage Pch-open drain – None S7/T7 to S15/T15 S16 to S31 – None High voltage Pch-open drain – fixed S32 to S51 – None High voltage Pch-open drain – None XT1 – None Input only None – XT2 – None Output for 32.768kHz crystal oscillation None – S0/T0 to S6/T6 Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). * Note 1: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, and VSS2 must be connected together and grounded. *Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. LSI VDD1 Power Back-up capacitors *2 VDD2 VDD3 VDD4 VSS1 VFD VSS2 9/24 LC87F65C8A 1. Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max. Supply voltage VDDMAX VDD1,VDD2,VDD3,V VDD1=VDD2= DD4 VDD3=VDD4 -0.3 +6.5 Input voltage VI(1) XT1,XT2,CF1, RES -0.3 VDD+0.3 VDD+0.3 VI(2) VP VDD-45 Output voltage VO(1) S0/T0 to S15/T15 VDD-45 VDD+0.3 Input/Output voltage VIO(1) •Port 0: CMOS output option •Port 1 •Port 3: CMOS output option •Port 7 •Port 8 -0.3 VDD+0.3 VIO(2) •Port 0 open drain •Port 3 open drain -0.3 15 VDD-45 VDD+0.3 High level output current Peak output current Total output current Low level output current Peak output current Total output current VIO(3) S16 to S51 IOPH(1) Port 0, 1, 3 •CMOS output selected •Current at each pin -10 IOPH(2) Port71,72,73 Current at each pin -3 unit V mA IOPH(3) S0/T0 to S15/T15 Current at each pin -30 IOPH(4) S16 to S51 Current at each pin -15 ΣIOAH(1) Port 0 Total of all pins -30 ΣIOAH(2) Port 1,3 Total of all pins -30 ΣIOAH(3) Port 7 Total of all pins -5 ΣIOAH(4) S0/T0 to S15/T15 Total of all pins -65 ΣIOAH(5) S16 to S27 Total of all pins -60 ΣIOAH(6) S28 to S39 Total of all pins -60 ΣIOAH(7) IOPL(1) S40 to S51 Total of all pins -60 Port 02, 03 For each pin 30 IOPL(2) •Port 00,01,04 to 07 •Port 1,3 For each pin 20 IOPL(3) Port 7,8 For each pin 5 ΣIOAL(1) Port 0 For each pin 60 ΣIOAL(2) Ports 1,3 For each pin 50 ΣIOAL(3) Ports 7,8 For each pin 20 QIP100E Ta = -20 to+70°C 500 mW °C Maximum power Pdmax dissipation Operating temperature range Topg -20 70 Storage temperature range Tstg -55 125 10/24 LC87F65C8A 2. Recommended Operating Range at Ta=-20°C to +70°C, VSS1=VSS2=0V Parameter Symbol Pins Conditions Operating VDD(1) supply voltage range Hold voltage VHD VDD1=VDD2=VDD3 =VDD4 0.294µs ≤ tCYC ≤ 200µs VDD1 RAM and the register data are kept in HOLD mode. Pull-down voltage Input high voltage VP VP VIH(1) •Port 0,3: CMOS output option •Port 8 Port 0,3: N-ch open drain output •Port 1 •Port71,72,73 •P70 port input/interrupt S16 to S51 VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) VIL(7) Operation tCYC cycle time External system fEXCF(1) clock frequency P70 Weak signal input Port 70 Watchdog timer XT1, XT2, CF1, RES •Port 0,3: CMOS output option •Port 8 Port 0,3: N-ch open drain output •Port 1 •Port 71,72,73 •P70 port input/interrupt S16 to S51 min. 4.5 Ratings typ. max. 5.5 2.0 5.5 4.5–5.5 -35 VDD Output disable 4.5–5.5 0.3VDD +0.7 VDD Output disable 4.5–5.5 13.5 Output disable 4.5–5.5 0.3VDD +0.7 0.3VDD +0.7 Output P-channel Tr. OFF Output disable Output disable 4.5–5.5 unit V VDD 0.3VDD +1.0 4.5–5.5 0.75VDD 4.5–5.5 0.9VDD VDD 4.5–5.5 0.75VDD VDD VDD VDD Output disable 4.5–5.5 VSS 0.15VDD +0.4 Output disable 4.5–5.5 VSS Output disable 4.5–5.5 VSS 0.15VDD +0.4 0.1VDD +0.4 4.5–5.5 -35 0.2VDD 4.5–5.5 4.5–5.5 VSS VSS 4.5–5.5 4.5–5.5 VSS 0.294 0.25VDD 0.8VDD -1.0 0.25VDD 200 µs 4.5–5.5 0.1 10 MHz 4.5–5.5 0.2 20 Output P-channel Tr. OFF Port 87 weak signal input Output disabled Port 70 Output disabled Watchdog timer XT1,XT2,CF1, RES CF1 VDD[V] •CF2 open circuit •system clock divider set to 1/1 •external clock DUTY = 50±50% •CF2 open circuit •system clock divider set to 1/2 11/24 LC87F65C8A Parameter Symbol Pins Conditions Oscillation stabilizing time period (Note 1) FmCF(1) CF1, CF2 10MHz ceramic resonator oscillation FmCF(2) CF1, CF2 4MHz ceramic resonator oscillation Ratings VDD[V] min. typ. 4.5–5.5 10 4.5–5.5 4 max. unit MHz Refer to figure 1 Refer to figure 1 FmRC FsX’tal XT1, XT2 RC oscillation 4.5–5.5 32.768kHz crystal resonator oscillation 4.5–5.5 0.3 1.0 32.768 2.0 kHz Refer to figure 2 (Note 1) The oscillation constant is shown in table 1 and table 2. 12/24 LC87F65C8A 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Parameter Input high current Input low current Output high voltage Symbol Conditions IIH(1) Ports 0,3: N-ch open drain output •Output disabled •VIN=13.5V (including OFF state leak current of the output Tr.) 4.5–5.5 5 IIH(2) Port 0,1,3,7,8 •Output disabled •Pull-up resister OFF. •VIN=VDD (including OFF state leak current of the output Tr.) 4.5–5.5 1 IIH(3) S16 to S51 without pull-down resister (Port C,D,E,F,G) When configured as an input 4.5–5.5 port VIN=VDD 60 min. typ. max. RES VIN=VDD 4.5–5.5 1 IIH(5) XT1,XT2 When configured as an input 4.5–5.5 port VIN=VDD 1 IIH(6) CF1 VIN=VDD 4.5–5.5 IIH(7) P87/AN7/MICIN weak signal input VIN=VBIS+0.5V (VBIS : Bias voltage) 4.5–5.5 4.2 IIL(1) Port 0,1,3,7,8 •Output disabled •VIN=VSS (including OFF state leak current of the output Tr.) 4.5–5.5 -1 RES VIN=VSS 4.5–5.5 -1 IIL(3) XT1,XT2 When configured as an input 4.5–5.5 port VIN=VSS -1 IIL(4) CF1 VIN=VSS -15 IIL(5) P87/AN7/MICIN weak signal input VIN=VBIS-0.5V (VBIS : Bias voltage) VOH(1) Port 0,1,3: CMOS output option IOH=-1.0mA 4.5–5.5 VOH(2) IOH=-0.1mA 4.5–5.5 VDD-0.5 VOH(3) Port 7 IOH=-0.4mA 4.5–5.5 VOH(4) S0/T0–S15/T15 IOH=-20.0mA 4.5–5.5 VDD-1.8 IOH=-1.0mA IOH at any single pin is not over 1mA. 4.5–5.5 IOH=-5.0mA 4.5–5.5 VDD-1.8 IOH=-1.0mA IOH at any single pin is not over 1mA. 4.5–5.5 S2+ to S51 VOH(7) 4.5–5.5 -15 8.5 15 -8.5 -4.2 VDD-1 VDD-1 VDD-1 Port 02, 03 IOL=30mA 4.5–5.5 1.5 VOL(2) Port 0,1,3 IOL=10mA 4.5–5.5 1.5 IOL=1.6mA 4.5–5.5 VOH=0.9VDD 4.5–5.5 Rpu Port 0,1,3,7 µA V VDD-1 VOL(1) VOL(3) unit 15 IIL(2) VOH(6) Pull-up resistor VDD[V] IIH(4) VOH(5) Output low voltage Ratings Pins 0.4 15 40 0 KΩ Continued/ 13/24 LC87F65C8A Parameter Output offleak current Symbol Pins IOFF(1) S0/T0 to S15/T15, S16 to S51 without IOFF(2) pull-down resistor Resistance of Rinpd the low level hold Tr. High voltage Rpd pull-down resistor Hysteresis VHIS(1) voltage VHIS(2) Pin capacitance CP Input sensitivity Vsen S16 to S51 S0/T0 to S15/T15, S16 to S51 with pull-down resistor •Port 1,7 • RES Port 87 weak signal input All pins Conditions Ratings VDD[V] min. •Output P-ch Tr. OFF •VOUT=VSS •Output P-ch Tr. OFF •VOUT=VDD-40V •Output P-ch Tr. OFF 4.5–5.5 -1 4.5–5.5 -30 •Output P-ch Tr. OFF •VOUT=3V •Vp=-30V 5.0 4.5–5.5 typ. Max. µA KΩ 200 60 100 4.5–5.5 0.1VDD 4.5–5.5 0.1VDD •All other terminals connected 4.5–5.5 unit 10 200 V pF to VSS. •f=1MHz •Ta=25°C Port 87 weak signal input 4.5–6.0 0.12VDD Vpp 14/24 LC87F65C8A 4. Serial Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=0V Serial output Serial input Output clock Serial clock Input clock Parameter Symbol Pins Conditions Ratings VDD[V] min. 4.5–5.5 4/3 Cycle Time tSCK(1) Low Level pulse width tSCKL(1) 2/3 tSCKLA(1) 2/3 tSCKH(1) 2/3 High Level pulse width SCK0(P12) Refer to figure 6 tSCKHA(1) typ. 3 SCK1(P15) Refer to figure 6 4.5–5.5 tSCK(2) Low Level pulse width High Level pulse width Cycle Time tSCKL(2) 1 tSCKH(2) 1 Low Level pulse width tSCKL(3) 1/2 tSCKLA(2) 3/4 tSCKH(3) 1/2 High Level pulse width SCK0(P12) •CMOS output option •Refer to figure 6 4.5–5.5 2 4/3 tSCKHA(2) SCK1(P15) •CMOS output option •Refer to figure 6 4.5–5.5 tSCK(4) Low Level pulse width High Level pulse width tSCKL(4) 1/2 tSCKH(4) 1/2 tsDI Data hold time thDI Output delay time tdDO tSCK 2 Cycle Time Data set-up time unit tCYC Cycle Time tSCK(3) max. SI0(P10), SI1(P13), SB0(P11), SB1(P14) •Measured with respect to SI0CLK leading edge. •Refer to figure 6 4.5–5.5 SO0(P12), SO1(P15), SB0(011), SB1(P14) •When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. •Use pull-up resistor (1kΩ) when open drain output selected. •Refer to figure 6 4.5–5.5 2 tCYC tSCK µs 0.03 0.03 1/3 tCYC +0.05 15/24 LC87F65C8A 5. Pulse Input Conditions at Ta=-20°C to +70°C, VSS1=VSS2=0V Parameter Symbol High/low level tPIH(1) pulse width tPIL(1) Pins Ratings Conditions VDD[V] min. typ. max. unit tCYC INT0(P70), INT1(P71), INT2(P72) •Interrupt acceptable 4.5–5.5 •Events to timer 0 can be input. 1 tPIH(2) tPIL(2) INT3(P73) (Noise rejection ratio set to 1/1.) 4.5–5.5 •Interrupt acceptable •Events to timer 0 can be input. 2 tPIH(3) tPIL(3) INT3(P73) (Noise rejection ratio set to 1/32.) 4.5–5.5 •Interrupt acceptable •Events to timer 0 can be input. 64 tPIH(4) tPIL(4) INT3(P73) (Noise rejection ratio set to 1/128.) 4.5–5.5 •Interrupt acceptable •Events to timer 0 can be input. 256 tPIL(5) tPIL(5) MICIN(P87) •Weak signal detection counter enabled 4.5–5.5 1 tPIL(6) RES# •Reset possible 4.5–5.5 200 µs 6. AD converter Characteristics at Ta=-20°C to + 70°C, VSS1=VSS2=0V Parameter Symbol Resolution N Absolute precision ET Conversion time TCAD Pins 4.5–5.5 4.5–5.5 4.5–5.5 Conditions Ratings VDD[V] 4.5–5.5 (Note2) 4.5–5.5 AD conversion time = 32 × tCYC (ADCR2=0) (Note 3) 4.5–5.5 AD conversion time = 64 × tCYC (ADCR2=1) (Note 3) Analog input voltage range Analog port input current min. VAIN 4.5–5.5 IAINH VAIN=VDD 4.5–5.5 IAINL VAIN=VSS 4.5–5.5 typ. max. 8 unit bit 15.62 (tCYC= 0.488µs) ±1.5 97.92 (tCYC= 3.06µs) 18.82 (tCYC= 0.294µs) 97.92 (tCYC= 1.53µs) VSS VDD V 1 µA LSB µs -1 (Note 2) Absolute precision not including quantizing error (±1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register. 16/24 LC87F65C8A 7. Current Dissipation Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=0V Parameter Current dissipation during basic operation (Note 4) Symbol Pins Conditions Ratings VDD[V] min. typ. max IDDOP(1) VDD1= •FmCF=10MHz for VDD2= Ceramic resonator VDD3= oscillation VDD4 •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •Divider set to 1/1 4.5–5.5 18 35 IDDOP(2) •CF1=20MHz for external clock •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •Divider set to 1/2 4.5–5.5 19 36 IDDOP(3) •FmCF=4MHz Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock: CF oscillation •Internal RC oscillation stopped. •Divider set to 1/1 4.5–5.5 10 22 IDDOP(4) •FmCF=0Hz (No oscillation) •FsX’tal=32.768kHz for crystal oscillation •System clock: RC oscillation •Divider set to 1/2 4.5–5.5 6 15 IDDOP(5) •FmCF=0Hz (No oscillation) •FsX’tal=32.768kHz for crystal oscillation •System clock: 32.768kHz •Internal RC oscillation stopped. •Divider set to 1/2 4.5–5.5 4.5 14 unit mA Continued/ 17/24 LC87F65C8A Parameter Current dissipation HALT mode (Note 4) Symbol Pins Conditions Ratings VDD[V] min. typ. Max. IDDHALT(1) VDD1= VDD2= VDD3= VDD4 HALT mode •FmCF=10MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock : CF oscillation •Internal RC oscillation stopped. •Divider: 1/1 4.5 to 5.5 6 12 IDDHALT(2) HALT mode •CF1=20MHz for external clock •FsX’tal=32.768kHz for crystal oscillation •System clock : CF oscillation •Internal RC oscillation stopped. •Divider 1/2 4.5 to 5.5 7 13 IDDHALT(3) 4.5 to 5.5 HALT mode •FmCF=4MHz for Ceramic resonator oscillation •FsX’tal=32.768kHz for crystal oscillation •System clock : CF oscillation •Internal RC oscillation stopped. •Divider: 1/1 2.5 6 IDDHALT(4) HALT mode •FmCF=0Hz (When oscillation stops.) •FsX’tal=32.768kHz for crystal oscillation •System clock : RC oscillation •Divider: 1/2 4.5 to 5.5 600 1600 IDDHALT(5) 4.5 to 5.5 HALT mode •FmCF=0Hz (When oscillation stops.) •FsX’tal=32.768kHz for crystal oscillation •System clock : 32.768kHz •Internal RC oscillation stopped. •Divider: 1/2 60 140 unit mA µA 18/24 LC87F65C8A Parameter Symbol Pins Conditions Current dissipation HOLD mode IDDHOLD(1) VDD1 HOLD mode •CF1=VDD or open circuit (when using external clock) Current dissipation Date/time clock HOLD mode IDDHOLD(2) VDD1 Ratings VDD[V] min. typ. max. 4.5 to 5.5 0.1 25 Date/time clock HOLD 4.5 to 5.5 mode •CF1=VDD or open circuit (when using external clock) •FmX’tal=32.768kHz for crystal oscillation 50 140 unit µA (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. 8. F-ROM Write Characteristics at Ta=+10°C to +55°C, VSSI=VSS2=0V Parameter Symbol Pins On board write current IDDF(1) VDD1 Write cycle time tFW(1) Conditions Ratings VDD[V] min. typ. max. unit •128-byte write •Including erase current 4.5 to 5.5 30 65 mA •128-byte write •Including erase current •Not including time to prepare 128-byte data 4.5 to 5.5 9.8 16 mS 19/24 LC87F65C8A Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 1. Main system clock oscillation circuit characteristics using ceramic resonator (Ta=-20 to +70°C) Circuit parameters Frequency Manufacturer Oscillator C1 10MHz Murata Kyocera 4MHz Murata C2 Rd1 CSA10.0MTZ 33pF 33pF 470Ω CST10.0MTW (30pF) (30pF) 470Ω PBRC10.00BR- (10pF) (10pF) 1.0kΩ A CSA4.00MG 33pF 33pF 1.5kΩ CST4.00MGW (30pF) (30pF) 1.5kΩ Operating supply voltage range Oscillation stabilizing time Notes typ max 4.5-5.5V 4.5-5.5V 4.5-5.5V 0.07ms 0.07ms 0.10ms 0.2ms 0.2ms 0.2ms Built in C1,C2 Built in C1,C2 4.5-5.5V 4.5-5.5V 0.06ms 0.06ms 0.1ms 0.1ms Built in C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator (Ta=-20 to +70°C) Circuit Parameters Operating supply Oscillation stabilizing time Frequency Manufacturer Oscillator Notes C3 32.768kHz Seiko EPSON C-002Rx 12pF C4 Rf Rd2 15pF 10MΩ 680kΩ voltage range typ max 4.5 - 5.5V 0.8s 2.0s *The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 XT1 CF2 XT2 Rf Rd1 Rd2 C1 C2 CF C4 C3 X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing measurement point 20/24 LC87F65C8A VDD Power Supply VDD limit 0V Reset time RES Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode Unfixed Reset Instruction execution mode Reset time and oscillation stable time HOLD release Without HOLD Release HOLD release signal VALID Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stablization time 21/24 LC87F65C8A VDD RRES (Note) Set CRES, RRES values such that reset time exceeds 200µs. RES CRES Figure 5 Reset circuit SIOCLK DATAIN DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0) tSCK tSCKL tSCKH SIOCLK tsDI thDI DATAIN tdDO DATAOUT Data RAM transmission period (only SIO0) tSCKLA tSCKHA SIOCLK tsDI thDI DATAIN tdDO DATAOUT Figure 6 Serial input / output test condition 22/24 LC87F65C8A tPIL Figure 7 tPIH Pulse input timing condition 23/24 LC87F65C8A memo : PS 24/24