MAXIM MAX2316

19-1507; Rev 0a; 8/99
L
MANUA
ION KIT HEET
T
A
U
L
EVA
TA S
WS DA
FOLLO
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Applications
Single/Dual/Triple-Mode CDMA Handsets
Globalstar Dual-Mode Handsets
Wireless Data Links
Tetra Direct-Conversion Receivers
Features
♦ Complete IF Subsystem Includes VCO and
Synthesizer
♦ Supports Dual-Band, Triple-Mode Operation
♦ VGA with >110dB Gain Control
♦ Quadrature Demodulator
♦ High Output Level (2.7V)
♦ Programmable Charge-Pump Current
♦ Supports Any IF Frequency Between 40MHz and
300MHz
♦ 3-Wire Programmable Interface
♦ Low Supply Voltage (+2.7V)
Ordering Information
PART
MAX2310EEI
MAX2312EEI
MAX2314EEI
MAX2316EEI
TEMP. RANGE
PIN-PACKAGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 QSOP
28 QSOP
28 QSOP
28 QSOP
Pin Configurations appear at end of data sheet.
Block Diagram appears at end of data sheet.
Wireless Local Loop (WLL)
Selector Guide
PART
MODE
DESCRIPTION
INPUT RANGE
MAX2310
AMPS,
Cellular CDMA,
PCS CDMA
Dual Band, Triple Mode
40MHz to 300MHz
MAX2312
PCS CDMA
Single Band, Single Mode
67MHz to 300MHz
MAX2314
AMPS,
Cellular CDMA
Single Band, Dual Mode
40MHz to 150MHz
MAX2316
Cellular CDMA
Single Band, Single Mode or
Single Band, Dual Mode with
External Discriminator
40MHz to 150MHz
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX2310/MAX2312/MAX2314/MAX2316
General Description
The MAX2310/MAX2312/MAX2314/MAX2316 are IF
receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable gain
amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a dynamic range of
over 110dB, and high input IP3 (-33dBm at 35dB gain,
1.7dBm at -35dB).
Unlike similar devices, the MAX2310 family of receivers
includes dual oscillators and synthesizers to form a
self-contained IF subsystem. The synthesizer’s reference and RF dividers are fully programmable through a
3-wire serial bus, enabling dual-band system architectures using any common reference and IF frequency.
The differential baseband outputs have enough bandwidth to suit both N-CDMA and W-CDMA systems, and
offer saturated output levels of 2.7Vp-p at a low +2.75V
supply voltage. Including the low-noise voltage-controlled oscillator (VCO) and synthesizer, the MAX2310
draws only 26mA from a +2.75V supply in CDMA (differential IF) mode.
The MAX2310/MAX2312/MAX2314/MAX2316 are available in 28-pin QSOP packages.
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V, +6.0V
SHDN to GND.............................................-0.3V to (VCC + 0.3V)
STBY, BUFEN, MODE, EN, DATA,
CLK, DIVSEL ...........................................-0.3V to (VCC + 0.3V)
VGC to GND...............-0.3V, the lesser of +4.2V or (VCC + 0.3V)
AC Signals TankH ±, TankL ±,
REF, FM ±, CDMA ± .................................................1.0V peak
Digital Input Current SHDN, MODE, DIVSEL,
BUFEN, DATA, CLK, EN, STBY .....................................±10mA
Continuous Power Dissipation (TA = +70°C)
28-pin QSOP (derate 10mW/°C above TA = +70°C) ....800mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10kΩ, TA = -40°C to +85°C,
registers set to default power-up settings. Typical values are at VCC = +2.75V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
CDMA mode
FM IQ mode
Supply Current (Note 1)
ICC
ICC
FM I mode
STANDBY (VCO_H)
STANDBY (VCO_L)
Shutdown Current
ICC
Register Shutdown Current
ICC
MIN
TA = +25°C
TYP
25.9
TA = -40°C to +85°C
25.4
TA = -40°C to +85°C
37.5
36.7
40.6
TA = +25°C
24.7
TA = -40°C to +85°C
35.7
39.5
TA = +25°C
12.3
TA = -40°C to +85°C
18.8
TA = +25°C
11.5
TA = -40°C to +85°C
18.4
20.3
Addition for LO out (BUFEN = low)
3.5
SHDN = low
1.5
10
µA
3
5.8
mA
2.0
V
0.5
IIH
Logic Low Input Current
IIL
mA
20.7
Logic Low
Logic High Input Current
UNITS
41.5
TA = +25°C
Logic High
2
VGC Control Input Current
0.5V < VVGC < 2.3V
VGC Control Input Current
During Shutdown
SHDN = low
Lock Indicator High (locked)
50kΩ load
Lock Indicator Low (unlocked)
50kΩ load
DC Offset Voltage
I+ to I- and Q+ to Q-, PLL locked
Common-Mode Output Voltage
VCC = 2.75V
2
MAX
-5
2
µA
5
µA
1
µA
2.0
-20
V
µA
V
±1.5
VCC - 1.4
_______________________________________________________________________________________
0.5
V
+20
mV
V
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for
CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.)
PARAMETER
Input Frequency
SYMBOL
CONDITIONS
fIN
(Note 2)
Reference Frequency
fREF
(Note 2)
Frequency Reference Signal
Level
VREF
MIN
TYP
40
MAX
UNITS
300
MHz
39
MHz
0.2
Vp-p
SIGNAL PATH, CDMA MODE
Input Third-Order Intercept
IIP3
Input 1dB Compression
P1dB
Input 0.25dB Desensitization
Gain = -35dB (Note 3)
1.7
Gain = +35dB (Note 4)
-33.2
Gain = -35dB
-9
-6.4
Gain = +35dB
-44
-38.3
(Note 5)
Minimum Voltage Gain
AV
VGC = 0.5V (Note 6)
Maximum Voltage Gain
AV
VGC = 2.3V (Note 6)
DSB Noise Figure
NF
Gain = -35dB
-14.8
Gain = +35dB
-49
-54.8
56
dBm
dBm
dBm
-49
61.3
Gain = -35dB
62.9
Gain = +35dB
6.36
dB
dB
dB
SIGNAL PATH, FM_IQ MODE
Input Third-Order Intercept
IIP3
(Note 7)
Input 1dB Compression
P1dB
(Notes 6, 8)
Minimum Voltage Gain
AV
VGC = 0.5V (Note 6)
Maximum Voltage Gain
AV
VGC = 2.3V (Note 6)
Gain = -35dB
-6.0
Gain = +35dB
-31
Gain = -35dB
-20
-16.2
Gain = +35dB
-44
-38.4
-50.2
58.5
dBm
dBm
-47.4
dB
63.4
dB
±2.5
dB
4.2
MHz
SIGNAL PATH, CDMA and FM_IQ MODE
Maximum Gain Variation
Over Temperature
Normalized to +25°C
Baseband 0.5dB Bandwidth
Quadrature Suppression
TA = TMIN to TMAX
+30
LO to Baseband Leakage
Saturated Output Level
VSAT
Differential
+35
dB
1
mVp-p
2.7
Vp-p
PHASE-LOCKED LOOP
fVCO_L
VCO Tune Range
fVCO_H
LOOUT Output Power
PLO
(Note 2)
RL = 50Ω, BUFEN = low
80
300
135
600
-13.7
MHz
dBm
_______________________________________________________________________________________
3
MAX2310/MAX2312/MAX2314/MAX2316
AC ELECTRICAL CHARACTERISTICS
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for
CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
VCO Minimum Divide Ratio
M1, M2
VCO Maximum Divide Ratio
M1, M2
REF Minimum Divide Ratio
R1, R2
REF Maximum Divide Ratio
R1, R2
CONDITIONS
MIN
TYP
256
2
2047
(Note 6)
Maximum Phase Detector
Comparison Frequency
(Note 6)
20
1500
kHz
kHz
Base Band Spurious due to PLL
LOOUT at 210MHz,
VCO_H Enabled (Note 9)
UNITS
16383
Minimum Phase Detector
Comparison Frequency
LOOUT at 85MHz,
VCO_L Enabled (Note 9)
MAX
-50
1kHz offset
-72
12.5kHz offset
-100
30kHz offset
-110
120kHz offset
-119
900kHz offset
-125
1kHz offset
-64
12.5kHz offset
-91
30kHz offset
-105
120kHz offset
-115
900kHz offset
-125
dBc
dBc/Hz
dBc/Hz
TURBO LOCK
Charge-Pump Source/Sink
Current
Charge-Pump Source/Sink
Matching
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
4
Acquisition, CPX = XX, TC = 1
1480
2100
2650
Locked, CPX = 00
105
150
190
Locked, CPX = 01
150
210
265
Locked, CPX = 10
210
300
380
Locked, CPX = 11
300
425
530
0.2
10
Locked, all values of CPX,
0.5V < VCP < VCC - 0.5V
µA
%
FM_IQ and FM_I modes are not available on MAX2312 and MAX2316.
Recommended operating frequency range.
f1 = 210.88MHz, f2 = 210.89MHz, Pf1 = Pf2 = -15dBm.
f1 = 210.88MHz, f2 = 210.89MHz, Pf1 = Pf2 = -50dBm.
Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at
1.25MHz below the LO frequency is applied at the specified level.
Guaranteed by design and characterization.
f1 = 85.88MHz, f2 = 85.98MHz, Pf1 = Pf2 = -15dBm.
f1 = 85.88MHz, f2 = 85.98MHz, Pf1 = Pf2 = -50dBm.
Measured at LOOUT with BD = 0 (÷2 selected).
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
RECEIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TA = +25°C
25.00
TA = -40°C
22.50
3.0
3.5
4.0
4.5
5.0
TA = +25°C
0.006
-20
0.004
TA = +25°C
0
TA = -40°C
-40
TA = +85°C
-60
TA = -40°C
-80
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
5.5
1.0
1.5
2.0
2.5
VGC (V)
GAIN vs. INPUT FREQUENCY
GAIN vs. BASEBAND FREQUENCY
THIRD-ORDER INPUT
INTERCEPT vs. GAIN
59.5
40
35
30
59.0
58.0
56.5
300
400
-50
-60
56.0
500
0
2
4
6
NOISE FIGURE vs. GAIN
6.8
30
6.4
10
6.2
0
20
40
60
NOISE FIGURE vs. TEMPERATURE
VCO VOLTAGE vs. TIME
80
MAX2310 toc09
MAX2310 toc08
6.6
20
-20
SHDN
VCO
VOLTAGE
VOLTS (1V/div)
40
NF (dB)
7.0
-40
GAIN (dB)
7.2
50
-60
10 12 14 16 18 20
7.4
MAX2310 toc07
60
8
FREQUENCY (MHz)
FREQUENCY (MHz)
70
TA = +25°C
-30
-40
20
200
TA = +85°C
-20
57.5
57.0
100
-10
58.5
25
15
TA = -40°C
0
IIP3 (dBm)
RELATIVE GAIN (dB)
45
10
MAX2310 toc05
MAX2310 toc04
60.0
3.0
MAX2310 toc06
SUPPLY VOLTAGE (V)
VGC = 2.5V
0
20
SUPPLY VOLTAGE (V)
55
50
NAX2310 toc03
MAX2310 toc02
40
TA = +85°C
0.008
5.5
60
NF (dB)
60
0
2.5
GAIN (dB)
0.010
0.002
20.00
GAIN vs. VGC
80
GAIN (dB)
TA = +85°C
30.00
27.50
0.012
SHUTDOWN CURRENT (mA)
32.50
SUPPLY CURRENT (mA)
0.014
MAX2310 toc01
35.00
RECEIVE SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
LOCK
LOCK TIME
1.83ms
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70
GAIN (dB)
MAX2310/MAX2312/MAX2314/MAX2316
Typical Operating Characteristics
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for
CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.)
6.0
-40
-20
0
20
40
60
80
100
TIME (500µs/div)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for
CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.)
TANKL PORT
1/S11 vs. FREQUENCY
MAX2310 toc11
TANKH PORT
1/S11 vs. FREQUENCY
MAX2310 toc12
FM PORT
S11 vs. FREQUENCY
MAX2310 toc10
4
4
3
3
2
1
1
2
1
2
3
4
1:
2:
3:
4:
641 - j428 10MHz
27 - j162 85MHz
4 - j73 210MHz
1.8 - j39 600MHz
1:
2:
3:
4:
1:
2:
3:
4:
-3.06ms + j349µs, 100MHz
-3.01ms + j853µs, 160MHz
-3.11ms + j1.45ms, 240MHz
-3.04ms + j1.85ms, 300MHz
1.98ms + j437µs, 100MHz
2.18ms + j853µs, 160MHz
2.11ms +j 2.53ms, 420MHz
2.17ms +j 3.71ms, 600MHz
CDMA PORT
S11 vs. FREQUENCY
MAX2310 toc14
LOOUT PORT
S22 vs. FREQUENCY
MAX2310 toc13
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
1
2
1: 108.63Ω (Re)
10.266Ω (1m)
40MHz
2: 134.99Ω (Re)
13.71Ω (1m)
150MHz
3: 158.83Ω (Re)
39.58Ω (1m)
300MHz
3
4
1: 10MHz, 375Ω - j56Ω
2: 85MHz, 285Ω - j200Ω
3: 210MHz, 73Ω - j169Ω
4: 600MHz, 2.1Ω - j34Ω
Pin Description
PIN
6
NAME
MAX2310
MAX2312
MAX2314
MAX2316
1
1
1, 8
1
BYP
2
2
2
2
CP_OUT
3
3
3
3
GND
4, 5
—
4, 5
5, 6
TANKL+,
TANKL-
—
4
—
4
DIVSEL
FUNCTION
Bypass Node. Must be capacitively decoupled (bypassed)
to analog ground.
Charge-Pump Output
Analog Ground Reference
Differential Tank Input for Low-Frequency Oscillator
High selects M1/R1; low selects M2/R2.
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
PIN
NAME
MAX2310
MAX2312
MAX2314
MAX2316
6, 7
5, 6
—
—
TANKH+,
TANKH-
FUNCTION
Differential Tank Input for High-Frequency Oscillator
—
7
—
7
BUFEN
—
—
6, 7
—
N.C.
8
—
—
—
MODE
Mode Select. High selects CDMA mode; low selects FM
mode.
—
8
—
8
LOOUT
Internal VCO Output. Depending on setting of BD bit, LOOUT
is either the VCO frequency (twice the IF frequency) or onehalf the VCO frequency (equal to the IF frequency).
9
9
9
9
VCC
+2.7V to +5.5V Supply for Digital Circuits
10
10
10
10
GND
Digital Ground
11
11
11
11
REF
Reference Frequency Input
12
12
12
12
SHDN
Shutdown Input—active low. Low powers down entire device,
including registers and serial interface.
13, 14
13, 14
13, 14
13, 14
IOUT+,
IOUT-
Differential In-Phase Baseband Output, or FM signal output
FM_I mode is selected.
15
15
15
15
LOCK
Lock Output—open-collector pin. Logic high indicates phaselocked condition.
16, 17
16, 17
16, 17
16, 17
QOUT-,
QOUT+
18
18
18
18
CLK
19
19
19
19
EN
20
20
20
20
DATA
2.7V to 5.5V Supply for Analog Circuits
VGA Gain Control Input. Control voltage range is 0.5V to 2.3V.
LO Buffer Amplifier—active low
No Connection. Must be left open-circuit.
Differential Quadrature-Phase Baseband Output. Disabled if
FM_I mode is selected.
Clock input of the 3-wire serial bus
Enable Input. When low, input shift register is enabled.
Data input of the 3-wire serial bus.
21
21
21
21
VCC
22
22
22
22
VGC
23, 24
23, 24
23, 24
23, 24
CDMA-,
CDMA+
25
—
25
—
FM+
Differential Positive Input. Active in FM mode.
—
25
—
25
N.C.
No Connection.
26
—
26
—
FM-
Differential Negative Input for FM signal. Bypass to GND for
single-ended operation.
—
26
—
26
STBY
Standby Input—active low. Low powers down VGA and demodulator while keeping VCO, PLL, and serial bus on.
27, 28
27, 28
27, 28
27, 28
BYP
Bypass Node. Must be capacitively decoupled (bypassed) to
analog VCC.
Differential CDMA Input. Active in CDMA mode.
_______________________________________________________________________________________
7
MAX2310/MAX2312/MAX2314/MAX2316
Pin Description (continued)
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
0.01µF
VCC
10k
0.01µF
3.3nF
0.033µF
0.1µF
BYP
BYP
BYP
CPOUT
GND
18pF
10k
0.01µF
FMFM
FM+
TANKL+
CDMA+
5pF
10k
18pF
10k
12pF
68nH
MAX2310
CDMA
680Ω
TANKLCDMATANKH+
DAC
VGC
47pF
1.5pF
18nH
VCC
12pF
10k
TANKHVCC
MODE
VCC
VCC
47pF
DATA
3-WIRE
EN
GND
CLK
REF
SHDN
IOUT+
I
QOUT+
10k
10k
IOUT-
Q
QOUTLOCK
47k
VCC
Figure 1. MAX2310 Typical Operating Circuit
_______________Detailed Description
MAX2310
The MAX2310 is intended for dual-band (PCS and cellular) and dual-mode code division multiple access
(CDMA) and FM applications (Figure 1). The device
includes an IF variable-gain amplifier, quadrature
demodulator, dual VCOs, and dual-frequency synthesizers (Figure 7). Dual VCOs are provided for applications using different IF frequencies for each mode or
band of operation. The analog FM output signal can be
8
configured for conversion to the I channel, or it may be
converted in quadrature to both the I and Q channels.
The MAX2310’s operation modes are described in
Table 1. These modes are set by programming the control register and setting logic levels on control pins. If
MODE is left floating, the internal register controls the
operation. If driven high or low, mode will override certain register bits, as shown in Table 1.
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
CP POL
TEST_EN
TURBOCHARGE
DIVSEL
VCO_BYP
VCO_SEL
BUF_DIV
BUFEN
FM_TYPE
IN_SEL
STBY
SHDN
L
S
B
TEST_MODE
M
CONTROLS REGISTER
B
MODE
M
S
B
SHDN
PINS
SHUTDOWN
Shutdown pin completely
powers down the chip
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SHUTDOWN
0 in shutdown register bit leaves
serial port active
H
X
X
X
X
X
X
X
X
X
X
X
X
X
0
STANDBY
0 in standby register bit turns off
VGA and modulator only
H
X
X
X
0
X
X
0
1
CDMA
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to high
H
H
0
X
X
X
X
X
X
1
1
CDMA
Floating mode pin returns control
to register
H
F
0
1
1
X
X
X
1
1
1
FM_IQ
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low
H
L
0
X
X
X
X
0
X
1
1
FM_IQ
Floating mode pin returns control
to register
H
F
0
X
X
0
0
1
1
FM_I
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low
H
L
0
X
X
1
X
1
1
FM_I
Floating pins return control to
register
H
L
F
0
X
X
1
0
1
1
OPERATIONAL
MODE
ACTION
RESULT
X
X
Note: H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.
MAX2312/MAX2316
The MAX2312/MAX2316 quadrature demodulators are
simplified versions of the MAX2310 that can be used in
single-mode CDMA or dual mode using an external FM
discriminator (Figures 2a and 2b). The MAX2312 VCO
is optimized for the 67MHz to 300MHz IF frequency
range, while the MAX2316 VCO is optimized for the
40MHz to 150MHz IF frequency range.
Both devices include a buffered output for the VCO.
The buffered VCO output can be used to support systems implementing traditional limiting IF stages for FM
demodulation in dual-mode phones as well as for the
transmit LO in TDD systems. This buffered output can
be configured for the VCO frequency (twice the IF frequency) or one-half the VCO frequency (IF frequency).
The BUFEN pin enables this feature. A standby mode,
in which only the VCO and synthesizer are operational,
can be selected through the serial interface or the
STBY pin. The MAX2312/MAX2316s’ operational modes
are described in Table 2. These modes are set by programming the control register and/or setting logic levels on control pins. If the control pins (STBY, BUFEN,
DIVSEL) are left floating, the internal register controls
the operational mode. If driven high or low, the control
pins will override certain register bits, as shown in
Table 2.
_______________________________________________________________________________________
9
MAX2310/MAX2312/MAX2314/MAX2316
Table 1. MAX2310 Control Register States
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
10k
0.01µF
3300pF
0.033µF
0.01µF
BYP
BYP
CPOUT
BYP
VCC
0.01µF
GND
DIVSEL
12pF
10k
TANKH+
CDMA+
18nH
1.5pF
CDMA
680Ω
MAX2312
12pF
10k
VCC
STBY
TANKHBUFEN
CDMADAC
VGC
47pF
LOOUT
VCC
VCC
VCC
47pF
GND
REF
SHDN
IOUT+
I
DATA
VCC
EN
3-WIRE
CLK
QOUT+
10k
10k
IOUT-
Q
QOUTLOCK
47k
VCC
Figure 2a. MAX2312 Typical Operating Circuit
10
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2310/MAX2312/MAX2314/MAX2316
47pF
0.033µF
0.01µF
10k
0.01µF
BYP
BYP
CP_OUT
BYP
VCC
3300pF
0.01µF
GND
DIVSEL
17pF
10k
TANKL+
CDMA
680Ω
MAX2316
DISCRIMINATOR
TANKL-
CDMA-
BUFEN
VGC
DAC
47pF
LOOUT
455kHz
VCC
GND
REF
SHDN
IOUT+
I
DATA
VCC
3-WIRE
EN
CLK
QOUT+
10k
10k
IOUT-
FM
VCC
VCC
47pF
LIMITER
CDMA+
68nH
5pF
18pF
10k
VCC
STBY
Q
QOUTLOCK
47k
VCC
Figure 2b. MAX2316 Typical Operating Circuit
______________________________________________________________________________________
11
Table 2. MAX2312/MAX2316 Control Register States
M
S
B
BUFEN
STBY
TEST_MODE
CP_POL
TES_TEN
TURBOCHARGE
DIVSEL
VCO_BYP
VCO_SEL
BUF_DIV
BUFEN
FM_TYPE
IN_SEL
STBY
SHDN
SHUTDOWN
Shutdown pin completely powers down
the chip
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SHUTDOWN
0 in shutdown register
bit leaves serial bus
active
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
STANDBY
0 in standby pin turns
off VGA and modulator
only
H
STANDBY
0 in standby register bit
turns off VGA and modulator only
H
H/
L
DIVIDER
SELECT
DIV_SEL pin overrides
DIV_SEL register bit
H
H/
L
H
0
X
X
1
DIVIDER
SELECT
If DIV_SEL pin is floated, then register bit
selects divider
H
F
H
0
1/
0
X
1
LO BUFFER
ENABLE
BUFEN pin controls the
LO buffer and overrides
the bit
H/
L
H
0
X
X
1
LO BUFFER
ENABLE
If pin is floated, then
BUFEN register bit
controls buffer
H
F
0
X
1/
0
1
OPERATIONAL
MODE
ACTION
RESULT
L
H
0
X
X
1
0
X
0
1
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter.
12
L
S
B
CONTROL
REGISTER
MSB
DIVSEL
PINS
SHDN
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2310/MAX2312/MAX2314/MAX2316
47pF
10k
0.01µF
0.01µF
BYP
BYP
VCC
3300pF
0.033µF
0.01µF
MAX2314
CP_OUT
0.01µF
GND
18pF
10k
VCC
BYP
FM-
TANKL+
FM+
5pF
68nH
FM
CDMA+
18pF
10k
TANKL-
CDMA
680Ω
1000pF
BYP
CDMAVGC
VCC
VCC
VCC
GND
DATA
REF
EN
DAC
47pF
47pF
SHDN
I_OUT+
VCC
3-WIRE
CLK
Q_OUT+
10k
10k
I_OUT-
Q
Q_OUTLOCK
47k
VCC
Figure 3. MAX2314 Typical Operating Circuit
MAX2314
The MAX2314 supports CDMA cellular-band, dualmode operation. As with the MAX2310, the FM mode
can be configured for conversion to the I port or quadrature conversion to both the I and Q ports (Figure 3).
The MAX2314’s operational modes are described in
Table 3. These modes are set by programming the
control register and setting logic levels on control pins.
__________Applications Information
Variable-Gain Amplifier and Demodulator
The MAX2310 family provides a Variable-Gain Amplifier
(VGA) with exceptional gain range. The MAX2310/
MAX2314 support multimode applications with dual differential inputs, selectable with the IN_SEL (IS) control
bit. On the MAX2310 this function can be controlled
with the MODE pin, which overrides the IS control bit.
The VGA’s gain is controlled over a 110dB range with
______________________________________________________________________________________
13
Table 3. MAX2314 Control Register States
M
CONTROLS REGISTER
B
OPERATIONAL
MODE
ACTION
RESULT
TEST_EN
TURBOCHARGE
DIVSEL
VCO_BYP
VCO_SEL
BUF_DIV
BUFEN
FM_TYPE
IN_SEL
STBY
SHDN
L
S
B
CP_POL
M
S
B
TEST_MODE
P
I
N
SHDN
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
SHUTDOWN
Shutdown pin completely shuts down
chip
L
X
X
X
X
X
X
X
X
X
X
X
X
X
SHUTDOWN
0 in shutdown register bit leaves serial port active
H
X
X
X
X
X
X
X
X
X
X
X
X
L
0 in standby pin turns off VGA and
modulator only
H
0
0
X
X
0
1
CDMA
CDMA operation
H
0
0
X
X
X
1
1
1
FM_IQ
FM IQ quadrature operation
H
0
0
X
X
0
0
1
1
FM I operation
H
0
0
X
X
1
0
1
1
STANDBY
FM_I
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter
the VGC pin. The output of the VGA drives the RF ports
of a quadrature demodulator. The MAX2310/MAX2314
provide two types of FM demodulation, controlled by
the FM_TYPE (FT) control bit. When FM_TYPE is “1,”
the signal is passed through both the I and Q signal
paths for subsequent lowpass filtering and A/D conversion at baseband. If FM_TYPE is “0,” the FM signal is
passed through the I mixer only.
Voltage-Controlled Oscillator,
Buffers, and Quadrature Generation
The LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an onchip differential oscillator, and an off-chip high-Q resonant network. Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2310 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
14
control bit. They oscillate at twice the desired LO frequency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
bit.
The MAX2312/MAX2316 buffer the output of the VCO
and provide this signal at the LOOUT pin. This signal is
enabled by the BUFEN (BE) control bit or by the
BUFEN control pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.
Quadrature downconversion is realized by providing inphase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.
The appropriate latch outputs provide I and Q signals
at the desired LO frequency.
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Multimode applications are supported by two independent programmable registers each for the M counter
(M1, M2), the R counter (R1, R2), and the charge-pump
output current magnitude (CP1, CP2). The DIVSEL (DS)
bit selects which set of registers is used. It can be overridden by the MAX2310’s MODE pin or the MAX2312/
MAX2316’s DIVSEL pin. Programming these registers is
discussed in the 3-Wire Interface and Registers section.
800µA
D1
TANK-
TANK+
RL
RB
RE
3-Wire Interface and Registers
The MAX2310 family incorporates a 3-wire interface for
synthesizer programming and device configuration
(Figure 5). The 3-wire interface consists of a clock,
data, and ENABLE. It controls the VCO dividers (M1
and M2), reference frequency dividers (R1 and R2),
and a 13-bit control register. The control register is
used to set up the operational modes (Table 4). The
input shift is 17 data bits long and requires a total of 18
clock bits (Figure 6). A single clock pulse is required
before enable drops low to initialize the data bus.
Whenever the M or R divide register value is programmed and downloaded, the control register must
also be subsequently updated. This prevents turbolock
from going active when not desired.
The SHDN control bit is notable because it differs from
the SHDN pin. When the SHDN control bit is low, the
registers and serial interface are left active, retaining
the values stored in the latches, while the rest of the
device is shut off. In contrast, the SHDN pin, when low,
shuts down everything, including the registers and serial interface. See the functional diagram in Figure 7.
Registers
R1
CF
When the part initially powers up or changes state, the
synthesizer acquisition time can be reduced by using
the Turbo feature, enabled by the TURBOCHARGE
(TC) control bit. Turbo functionality provides a larger
charge-pump current during acquisition mode. Once
the VCO frequency is acquired, the charge-pump output current magnitude automatically returns to the preprogrammed state to maintain loop stability and
minimize spurs in the VCO output signal.
The lock detect output indicates when the PLL is
locked with a logic high.
RB
RL
CF
Figure 8 shows the programming logic. The 17-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Before the shift register is able to accept
data, it must be initialized by driving it with at least one
full clock cycle at the CLK input with EN high (see
Figure 6). Pulling enable low will allow data to be
clocked into the shift register; pulling enable high loads
the register addressed by A0, A1, and A2, respectively
(Figure 8). Table 5 lists the power-on default values of
all registers. Table 6 lists the charge-pump current,
depending on CP0 and CP1.
RE
Figure 4. Voltage-Controlled Oscillators
______________________________________________________________________________________
15
MAX2310/MAX2312/MAX2314/MAX2316
Synthesizer
The VCO’s output frequency is controlled by an internal
phase-locked-loop (PLL) dual-modulus synthesizer.
The loop filter is off-chip to simplify loop design for
emerging applications. The tunable resonant network is
also off-chip for maximum Q and for system design
flexibility. The VCO output frequency is divided down to
the desired comparison frequency with the M counter.
The M counter consists of a 4-bit A swallow counter
and a 10-bit P counter. A reference signal is provided
from an external source and is divided down to the
comparison frequency with the R counter. The two
divided signals are compared with a three-state digital
phase-frequency detector. The phase-detector output
drives a charge pump as well as lock-detect logic and
turbocharge control logic. The charge pump output
(CP_OUT) pin is processed by the loop filter and drives
the tunable resonant network, altering the VCO frequency and closing the loop.
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
VCO1
14-BIT M1
COUNTER
(00)
DATA
CPI
CLK
EN
START BIT
M
U
X
(010)
16-BIT
DATA/ADDRESS
REGISTER
2-BIT
CP1
11-BIT R1
COUNTER
2-BIT
CP2
(11X)
CPOUT
FREF
(011)
11-BIT R2
COUNTER
13-BIT CONTROL
REGISTER
CP2
(01)
VCO2
14-BIT M2
COUNTER
Figure 5. 3-Wire Control Block Diagram
LSB
MSB
*SB
DATA
*START BIT MUST BE LOGIC HIGH.
*
CLOCK
*RISE AND FALL REQUIRED PRIOR TO EN GOING LOW.
ENABLE
Figure 6. 3-Wire Interface Timing Diagram
16
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
VGC
IOUT+
CDMA+
IOUT-
CDMAEN
CLK
DATA
LOGIC
SB
1
SHIFT REGISTER
(MAX2310/14)
÷2
FM+
QOUT+
FM-
2
2
CP1
R1 REGISTER
CP2
R2 REGISTER
010
11
011
FT
14
11
DIVSEL
(MAX2312/16)
01
M2 REGISTER
QOUT-
14
00
M1 REGISTER
MODE
(MAX2310)
IS
VS
TM POL TE
DS
TC
VB
VS
BD BE
FT
IS
SB
SD 110
DS
VCO_L
CONTROL
2
2
11
14
11
14
TANKL+
2
TANKL-
14
11
R COUNTER
VB
M COUNTER
REF
POL
Ø
DET
TANKH+
LOCK DET
TANKH-
TURBO
CONTROL
2
CHARGE
PUMP
LOCK
LO_OUT
÷2
BIAS
SHDN
VCO_H
TC
BUFEN
CP_OUT
STBY
(MAX2312/16)
BD
SB
SD
BE
(MAX2312/16)
Figure 7. Functional Diagram
______________________________________________________________________________________
17
MAX2310/MAX2312/MAX2314/MAX2316
MAX2310
MAX2312
MAX2314
MAX2316
MAX2310/MAX2312/MAX2314/MAX2316
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 4. Control Register, Default State: 0B57h, Address: 110b
BIT ID
BIT NAME
POWERUP
STATE
BIT
LOCATION
0 = LSB
TM
TEST_MODE
0
12
Must be 0 for normal operation.
POL
CP_POL
1
11
Logic “1” causes the charge-pump output CP_OUT to source current when fREF/R > fVCO/M. This state is used when the VCO tune
polarity is such that increasing voltage produces increasing frequency. Logic “0” causes CP_OUT to source current when fVCO/M
> fREF/R. This state is used when increasing tune voltage causes
the VCO frequency to decrease.
TE
TEST_ENABLE
0
10
Must be 0 for normal operation.
TC
TURBO_CHARGE
1
9
Logic “1” activates turbocharge mode, which provides rapid frequency acquisition in the PLL.
DS
DIV_SEL
1
8
Logic “1” selects M1/R1 divide ratios. Logic “0” selects M2/R2.
VB
VCO_BYP
0
7
Logic “1” bypasses the VCO inputs for external VCO operation.
VS
VCO_SEL
1
6
Logic “1” selects VCO_H. Logic “0” selects VCO_L.
BD
BUF_DIV
0
5
Logic “1” selects divide-by-2 on LOOUT port. Logic “0” bypasses
divider.
BE
BUFEN
1
4
Logic “1” disables LOOUT. Logic “0” enables LOOUT.
FT
FM_TYPE
0
3
Active in FM mode. Logic “0” selects quadrature demodulator for
FM mode. Logic “1” selects downconversion to I port.
IS
IN_SEL
1
2
Logic “0” selects FM input port. Logic “1” selects CDMA input.
SB
STBY
1
1
Logic “0” enables standby mode, which shuts down the VGA and
demodulator stages, leaving the VCO locked and the registers
active.
SD
SHDN
1
0
Logic “0” enables register-based shutdown. This mode shuts down
everything except the M and R latches and the serial bus.
Table 6. Charge-Pump Control Bits
Table 5. Register Defaults
REGISTER
18
FUNCTION
CP1
CP0
CHARGE-PUMP CURRENT
AFTER ACQUISITION
(µA)
DEFAULT
M1
10519DEC
M2
4269DEC
0
0
150
R1
492DEC
0
1
210
R2
492DEC
1
0
300
CTRL
OB57HEX
1
1
425
CP0
11 BIN
CP1
11 BIN
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2310/MAX2312/MAX2314/MAX2316
ADDRESS
DECODED
START BIT
SHIFT REGISTER
1
A2/M0
A1
A0
A2/M0
A1
A0
M1 REGISTER
M113
M1/0
0
0
M2 REGISTER
M213
M2/0
0
1
CP1 AND R1 REGISTERS
CP1/1 CP1/0 R1/10
R1/0
0
1
0
CP2 AND R2 REGISTERS
CP2/1 CP2/0 R2/10
R2/0
0
1
1
SD
1
1
0
CTRL REGISTER
/1
TM
POL
TE
TC
DS
VB
VS
BD
BE
FT
IS
SB
DATA
Figure 8. Programming Logic
______________________________________________________________________________________
19
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2310/MAX2312/MAX2314/MAX2316
Pin Configurations
TOP VIEW
BYP 1
28 BYP
BYP 1
28 BYP
CP_OUT 2
27 BYP
CP_OUT 2
27 BYP
GND 3
26 FM-
GND 3
26 FM-
TANKL+ 4
25 FM+
TANKL+ 4
25 FM+
TANKL- 5
24 CDMA+
TANKL- 5
MAX2310
23 CDMA-
N.C. 6
TANKH- 7
22 VGC
N.C. 7
22 VGC
MODE 8
21 VCC
BYP 8
21 VCC
TANKH+ 6
23 CDMA-
VCC 9
20 DATA
VCC 9
20 DATA
GND 10
19 EN
GND 10
19 EN
REF 11
18 CLK
REF 11
18 CLK
SHDN 12
17 QOUT+
SHDN 12
17 QOUT+
IOUT+ 13
16 QOUT-
IOUT+ 13
16 QOUT-
IOUT- 14
15 LOCK
IOUT- 14
15 LOCK
QSOP
QSOP
BYP 1
28 BYP
BYP 1
28 BYP
CPOUT 2
27 BYP
CP_OUT 2
27 BYP
GND 3
26 STBY
DIVSEL 4
TANKH+ 5
TANKH- 6
MAX2312
DIVSEL 4
24 CDMA+
TANKL+ 5
23 CDMA-
26 STBY
GND 3
25 N.C.
TANKL- 6
25 N.C.
24 CDMA+
MAX2316
23 CDMA-
BUFEN 7
22 VGC
BUFEN 7
22 VGC
LOOUT 8
21 VCC
LOOUT 8
21 VCC
VCC 9
20 DATA
VCC 9
20 DATA
GND 10
19 EN
GND 10
19 EN
REF 11
18 CLK
REF 11
18 CLK
SHDN 12
17 QOUT+
SHDN 12
17 QOUT+
IOUT+ 13
16 QOUT-
IOUT+ 13
16 QOUT-
IOUT- 14
15 LOCK
IOUT- 14
15 LOCK
QSOP
20
24 CDMA+
MAX2314
QSOP
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
TRANSISTOR COUNT: 6422
Block Diagram
DAC
VCC
QOUT+ QOUT- LOCK
AVCC
BYP
BYP
FM-
FM+
CDMA+
CDMA-
VGA
DATA
EN
VCC
CLK
0
90 /2
MAX2310
/M
CHARGE
PUMP
PHASE
DETECTOR
/R
BYP
AGND
TANKL+
TANKH+
TANKH-
REF
MODE
DVCC
SHDN IOUT+
IOUT-
CP_OUT
TANKL-
______________________________________________________________________________________
21
MAX2310/MAX2312/MAX2314/MAX2316
Chip Information
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
QSOP.EPS
MAX2310/MAX2312/MAX2314/MAX2316
Package Information
22
______________________________________________________________________________________