1.2V 8BIT 80MSPS DAC
dac1325x
FEATURES
GENERAL DESCRIPTION
This is CMOS 8-bit D/A Converter
for general applications. Its typical conversion rate
is 80MHz and Supply voltage is 1.2V
•
•
•
•
•
TYPICAL APPLICATIONS
80MHz Operation
+1.2V power supply
8bit Voltage parallel Input
0 ~ 0.4V Output Swing
Power Down mode(High active)
• Graphic display
• General purpose high-speed
FUNCTIONAL BLOCK DIAGRAM
AVDD12A AVSS12A AVDD12D AVSS12D AVBB12A
Decoder
D[7:0]
1st
Latch
Buffer
CK1B PD1
CK1
CK1B
CLK
Clock
Generator
PD
CCOMP
Amp
_
VREFOUT
IRSET
Ver 1.1(May. 2002)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
IOB
SIN
PDOUT
+
PD1
PDOUT
IO
Current
Cell
Array
2nd
Latch
CK1
AVBB12D
Slot
Cell
CM
Block
CCOMP
SIN
CCOMP
SIN
dac1325x
1.2V 8BIT 80MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O TYPE
I/O PAD
I/O TYPE ABBR.
PIN DESCRIPTION
D[7:0]
DI
picc_abb
Digital Input Data (8bit , 1.2V)
D[7] : MSB , D[0] : LSB
CLK
DI
picc_abb
Clock (1.2V)
PD
DI
picc_abb
Power Down (High Active)
IO, IOB
AO
poa_abb
Analog Output of DAC
IRSET
AI
pia_abb
External Resistor Connection
VREFOUT
AI
pia_abb
Reference Voltage Input / Output
CCOMP
AO
poa_abb
External Capacitor Connection
SIN
AO
poa_abb
External Capacitor Connection
AVDD12A
AP
vdd12t_abb
Analog Power (+1.2V)
AVSS12A
AG
vsst_abb
Analog Ground (0.0V)
AVBB12A
AG
vbb_abb
Analog Sub Bias (0.0V)
AVDD12D
DP
vdd12t_abb
Digital Power (+1.2V)
AVSS12D
DG
vsst_abb
Digital Ground (0.0V)
AVBB12D
DG
vbb_abb
Digital Sub Bias (0.0V)
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
•
•
•
•
•
•
AP
DP
AG
DG
AB
DB
:
:
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
Analog Bidirection
Digital Bidirection
CORE CONFIGURATION
AVDD12A
AVSS12A
AVDD12D
AVSS12D
AVBB12A
AVBB12D
D[7:0]
IO
dac1325x
CLK
PD
IOB
IRSET
SEC ASIC
VREFOUT
CCOMP
2 / 13
SIN
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
FUNCTIONAL DESCRIPTION
This is 8bit 80MSPS digital to analog data converter
and uses segment architecture for 4bits of MSB sides
, binary-weighted architecture for 4bits of LSB side. it
contains of First latch block, decoder block Second
latch block, AMP block, switch buffer block, PD
block for power down, CM(current mirror)block and
analog switch block. This core uses reference current
to decide the 1LSB current size by dividing the
reference current by 16times. So the reference current
must be constant and the switch's physical real size
can be constant by using OPA block with high DC
gain. The most significant block of this core is analog
switch block and it must maintain the uniformity at
each switch, so layout designer must care of the
matching characteristics on analog switch and CM
block. And more than 80%
of supply current is
dissipated at analog switch block and AMP block.
And it uses samsung(SEC) standard cell as all digital
cell of latch ,decoder and buffer. And to adjust full
current output, you must decide the "Rset" resistor
value(connected to IREF pin) and "Vbias" voltage
value(connected to VREFOUT pin). Its voltage output
can be obtained by connecting RO1(connected to
IO,IOB pin) .
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3 / 13
Linearity Error : Linearity error is defined as the
maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn
from zero to full scale.
Monotonicity : A D/A converter is monotonic if
the output either increases or remains constants as
the digital input increases.
Offset Error : The deviation of the output current
from the ideal of zero is called offset error. For IO ,
0mV output expected when the inputs are all 0s.
Gain Error : The difference between the actual
andideal output span. The actual span is determined
by the output when all inputs are set to 1s minus the
output when all inputs are set to 0s.
Output Compliance Range : The range of allowable
voltage at the output of a current-output DAC.
Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown
resulting in nonlinear performance.
Settling Time : The time required for the output to
reach and remain within a specified error band about
its final value, measured from the start of the output
transition
Glitch Impulse : Asymmetrical switching times in a
DAC give rise to undesired output transients that are
quantified by a glitch impulse. It is specified as the
net area of the glitch in pV-s
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
SYMBOL
VALUES
UNIT
Supply Voltage
AVDD12A
AVDD12D
1.65
V
Storage Temperature Range
Tstg
-45 to 125
ºC
NOTES
1. It is strongly recommended that to avoid power latch-up all the supply
Pins(AVDD12A,AVSS12A) be driven from the same source.
2. Absolute Maximum Rating values applied individually while all other
parameters are within specified operating conditions. Function operation
under any of these conditions is not implied.
3. Applied voltage must be current limited to specified range.
4. Absolute Maximum Ratings are value beyond which the device may be
damaged permanently. Normal operation is not guaranteed.
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Operating Supply Voltage
AVDD12A
AVDD12D
1.08
1.2
1.32
V
Digital input Voltage HIGH
LOW
Vih
Vil
0.7*AVDD12D
-
-
0.3*AVDD12D
V
Operating Temperature Range
Topr
-40
-
85
ºC
SEC ASIC
4 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
DC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD12A=AVDD12D=1.2V, AVSS12A=AVSS12D=AVBB12A=AVBB12D=0V, PD=Low, Top=25° C,
R(IRSET)=0.6kΩ, load resistance=50Ω unless otherwise specified.)
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Resolution
Bit
-
-
8
Bits
Differential Linearity Error
DLE
-
-
±1
LSB
Integral Linearity Error
ILE
-
-
±1.5
LSB
Monotonicity
Guaranteed
Maximum Output Compliance
Voc
-0.1
-
+0.5
V
Internal BGR Reference Voltage
-
-
-
-
V
Full Scale Output Current
Ifs
7.6
8.6
9.6
mA
Power Supply Current
Is
8
9
10
mA
AC ELECTRICAL CHARACTERISTICS
(Converter Specifications : AVDD12A=AVDD12D=1.2V, AVSS12A=AVSS12D=AVBB12A=AVBB12D=0V,
PD=Low, Top=25°C, R(IRSET)=0.6kΩ, load resistance=50Ω , load cap.=10pF unless otherwise specified.)
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Conversion Speed
Fop
-
80
-
MHz
Analog Output Delay
Td
-
3
7
ns
Analog Output Rise Time
Tr
-
1.5
2.5
ns
Analog Output Fall Time
Tf
-
1.5
2.5
ns
Analog Output Settling Time
Ts
-
100
150
ns
Glitch Impulse
GI
-
±50
±100
pVsec
Setup Time
Ts
2
-
-
nsec
Hold Time
Th
2
-
-
nsec
THD(Total Harmonic Distortion)
THD
-62
-
-38
dB
SND( Fout=10MHz , Fck=80MHz)
SND
-56
-
-38
dB
NOTES
1. The above parameters are guaranteed over the full temperature range.
2. Clock and data feed through is a function of the amount of overshoot and undershoot on the
digital inputs. Settling time does not include clock and data feed through. Glitch impulse include
clock and data feed through.
3. Setup and Hold Time are simulation values, not a test result
SEC ASIC
5 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
TIMING DIAGRAM
Ts
Digital Input
(D[7:0])
Th
D(n-1)
D(n)
D(n+1)
D(n+2)
D(n+3)
VO(n)
VO(n+1)
VO(n+2)
CLK
1/2 Clock delay
Analog Output
(VO)
VO(n-2)
VO(n-1)
Td
Digital Input
(D [7:0])
00000000
11111111
00000000
CLK
(< ± 1LSB)
90%
Analog Output
(VO)
Td
10%
Tset
Tr
Tf
NOTES
1. Output delay measured from the 50% point of the rising edge of CLK to the full scale
transition
2. Settling time measured from the 50% point of full scale transition to the output remaining
within ±1,2LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
SEC ASIC
6 / 13
ANALOG
HOST
DSP
CORE
8
MUX
8
TEST PATH
8
RO1 , RO2
50Ω
Digital Digital
Power Ground
0.6kΩ
1.2V GND
RSET
Analog Analog
Power Ground
0.1uF CERAMIC CAPACITOR
1.2V GND
Cc
Cc
VO
10uF TANTALUM CAPACITOR
Cc
RO1
Analog
Ground
GND
VOB
Ct
Ct
IO
IOB
RO2
Analog
Ground
GND
DESCRIPTION
Ct
AVDD12D AVSS12D AVBB12D
1.2V
SIN
1.2V
Analog
Power
Cc
Analog
Power
Cc
CCOMP
dac1325x
AVDD12A AVSS12A AVBB12A
D [7:0]
CLK
PD
Ct
0.3V
IRSET VREFOUT
RSET
Ω)
(=0.6kΩ
GND
Analog
Ground
LOCATION
ANALOG
7 / 13
SEC ASIC
dac1325x
1.2V 8BIT 80MSPS DAC
CORE EVALUATION GUIDE
dac1325x
1.2V 8BIT 80MSPS DAC
The full scale current is given as the decimal value equivalent to the digital code.
1. Resolution
If you want to change the resolution, use as many appear bits as you want and connect the rest
lower bits to the ground as above diagram which is 8bit application.
2. Output Range Alteration
In order to change the output swing, use following equation.
Vout = {V(IRSET)/(RSET*16)}*(DAC_CODE)*RO
Output swing level is a function of V(IRSET), RSET, and RO.
SEC ASIC
8 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
PHANTOM CELL INFORMATION
AVDD12A
AVSS12A
AVBB12A
SIN
IRSET
CCOMP
VREFOUT
dac1325x
IO1B
IO1
Pin Usage
D[7:0]
DI
Internal / External
PD
DI
Internal / External
CLK
DI
Internal / External
IO, IOB
AO
External
IRSET
AI
External
VREFOUT
AI
Internal / External
CCOMP
AO
External
SIN
AO
External
AVDD12A
AP
External
AVSS12A
AG
External
AVBB12A
AG
External
AVDD12D
DP
External
AVSS12D
DG
External
AVBB12D
DG
External
PD
Property
CLK
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
AVBB12D
AVSS12D
AVDD12D
Pin Name
Pin Layout Guide
1. Digital Input Signal lines must have same length to
reduce propagation delay.
1. When connected to PAD, the path should be kept as short
as possible.
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
1. When the core block is connected to other blocks, it must be double guard-ring using N-well and
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
SEC ASIC
9 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
PACKAGE CONFIGURATION
L1
Cc
Ct
+
L2
AVBB12D
NC
48
2
AVSS12D
NC
47
3
AVDD12D
NC
46
4
NC
NC
45
5
NC
NC
44
6
NC
AVBB12A
43
7
NC
AVSS12A
42
8
NC
NC
41
9
NC
NC
40
D[7]
10
D[7]
AVDD12A
39
D[6]
11
D[6]
NC
38
D[5]
12
D[5]
NC
37
D[4]
13
D[4]
NC
36
D[3]
14
D[3]
IRSET
35
0.0V
(AVSS12A)
D[2]
15
D[2]
VREFOUT
34
0.3V
D[1]
16
D[1]
NC
33
D[0]
17
D[0]
SIN
32
18
NC
CCOMP
31
CLK
19
CLK
NC
30
PD
20
PD
NC
29
21
NC
IO
28
IO
22
NC
IOB
27
IOB
23
NC
NC
26
24
NC
NC
25
DAC1325X
1
(VSS)
0.0V
Cc
Ct
+
1.2V
(VDD)
RSET(=0.6kΩ
Ω)
Cc
1.2V
(AVDD12A)
(0.0V in normal operation)
RO2
RO1
0.0V
(AVSS12A)
SEC ASIC
INDEX
DESCRIPTION
L1,L2
FERRITE BEAD (0.1mh)
Ct
10uF TANTALUM CAPACITOR
Cc
0.1uF CERAMIC CAPACITOR
RO1,RO2
50 Ω
RSET
600 Ω
10 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
PACKAGE PIN DESCRIPTION
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
AVBB12D
1
DG
Digital Sub Bias (0.0V)
AVSS12D
2
DG
Digital Ground (0.0V)
AVDD12D
3
DP
Digital Power (1.2V)
D[7:0]
10~17
DI
Digital Input Data
CLK
19
DI
Clock (1.2V)
PD
20
DI
Power Down Mode (High Active)
IOB, IO
27, 28
AO
Analog Voltage Output
CCOMP
31
AO
External Capacitor Connection
SIN
32
AO
External Capacitor Connection
VREFOUT
34
AI
Reference Voltage Input / Output
IRSET
35
AI
External Resistor Connection
AVDD12A
39
AP
Analog Power (1.2V)
AVSS12A
42
AG
Analog Ground (0.0V)
AVBB12A
43
AG
Analog Sub Bias (0.0V)
NC
4,5,6,7,8,9,18
21,22,23,24,25
26,29,30,33,36
37,38,40,41,44
45,46,47,48
DO
No Connection
I/O TYPE ABBR.
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
•
•
•
•
•
•
AP
DP
AG
DG
AB
DB
:
:
:
:
:
:
Analog Power
Digital Power
Analog Ground
Digital Ground
Analog Bidirection
Digital Bidirection
SEC ASIC
11 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (AVDD12A,AVDD12D) and VSS (AVSS12A,AVSS12D) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(AVDD12D) and analog power plane(AVDD12A) are connected
through a ferrite bead, and also the digital ground plane(AVSS12D) and the analog
ground plane(AVSS12A). This ferrite bead should be located within 3inches of
the dac1325x. The analog power plane supplies power to the dac1325x of
the analog output pin and related devices.
SEC ASIC
12 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products. If you have further questions, please specify in
the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
ºC
Output Load Capacitor
pF
Output Load Resistor
Ohm
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage
TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal
Frequency
MHz
Reference Voltage
V
External Resistor for Current
Setting(RSET)
Ohm
Pipeline Delay
sec
- Do you want to Power down mode?
- Do you want to Internal Reference Voltage(BGR)?
- Which do you want to Serial Input TYPE or parallel Input TYPE?
SEC ASIC
13 / 13
ANALOG
dac1325x
1.2V 8BIT 80MSPS DAC
VERSION LIST
Version
Date
Modified Items
Ver 1.0
02.03.20
Original version published.
Ver 1.1
02.05.01
Phantom Cell Information, Package Configuration, Package Pin
Description, PC Board Layout Consideration Added.
SEC ASIC
Comments
ANALOG