19-4539; Rev 0; 5/09 Fast Sample-and-Hold Circuit Features The DS1843 is a sample-and-hold circuit useful for capturing fast signals where board space is constrained. It includes a differential, high-speed switched capacitor input sample stage, offset nulling circuitry, and an output buffer. The DS1843 is optimized for use in optical line transmission (OLT) systems for burst-mode RSSI measurement in conjunction with an external sense resistor. ♦ Fast Sample Time < 300ns ♦ Hold Time > 100µs ♦ Low Input Offset ♦ Buffered Output ♦ Small, 8-Pin µDFN (2mm x 2mm) Pb-Free Package Applications Ordering Information Gigabit Passive Optical Network (GPON) OLT Gigabit Ethernet Passive Optical Network (GEPON) OLT GPON Optical Network Unit Sample and Hold PART TEMP RANGE PIN-PACKAGE DS1843D+ -40°C to +85°C 8 μDFN DS1843D+TRL -40°C to +85°C 8 μDFN +Denotes a lead(Pb)-free/RoHS-compliant package. TRL = Tape and reel. Typical Operating Circuit SDA DS1842/ MAX4007 I2C INTERFACE SCL MAIN MEMORY EEPROM/SRAM VCC 3.3V DS1843 VINP BMD MON3P VOUTP MON3N CIN CS VOUTN RIN MON4 CS CIN VINN STROBE SEN GND TEMP SENSOR 3.3V CONTROL LOGIC DEN STROBE ANALOG MUX MON1 VCC A/D CONFIG/RESULTS, SYSTEM STATUS BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY 12-BIT ADC MOD DAC BIAS DAC SEN CONTROLLER Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1843 General Description DS1843 Fast Sample-and-Hold Circuit ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC .............................................-0.5V to +6V Voltage Range on VOUTP, VOUTN, VINP, VINN, SEN, DEN ............................-0.5V to (VCC + 0.5V)* Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature ..............................................Refer to the IPC/JEDEC J-STD-020 Specification. *Subject to not exceeding +6V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Supply Voltage SYMBOL VCC CONDITIONS (Note 1) MIN TYP MAX UNITS +5.5 V TYP MAX UNITS 5.7 9 mA 7 pF +2.97 DC ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Supply Current ICC (Note 1) Input Capacitance CIN All pins (Note 2) Sample Capacitance CS VINN and VINP (Note 2) Logic-Input Low VIL SEN and DEN inputs Logic-Input High VIH SEN and DEN inputs Input Leakage I IN VINN or VINP, SEN = 0 Input Voltage VIN VIN = VINP - VINN VOUT = V OUTP - VOUTN; 100k load on each output pin Output Voltage Output Impedance Output Capacitive Load Total Input Referenced Voltage Offset: Differential Total Input Referenced Voltage Offset: Single-Ended 2 VOUT R OUTMAX C OUT VOS-DIFF VOS-SE (Note 2) MIN 5 pF 0.3 x VCC 0.7 x VCC V V 1 μA 0 1.0 V 0 1.0 V 1.3 k 1 Capacitance for stable operation 50 pF VCC = 2.9V, 1μs sample time, VIN = 6mV Voltco (VCC = 2.9V to 5.5V) 3.6 6.1 mV 1 mV/V VCC = 2.9V, 1μs sample time, VIN = 6mV 3.4 8 mV 1 mV/V Voltco (VCC = 2.9V to 5.5V) _______________________________________________________________________________________ Fast Sample-and-Hold Circuit (VCC = +2.97V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram.) PARAMETER SYMBOL Sample Time Minimum (Note 3) tS Delay Time Minimum Output Time Hold Time MIN 300 VOUT is within 35% 260 tDEL (Note 4) t OUT Delay from SEN falling edge until valid output at VOUT to 1% accuracy tHOLD Output Step Recovery Time (Note 6) CONDITIONS VOUT is within 1% tREC TYP MAX ns 10 (Note 5) UNITS ns t OUT 1V step, DEN = high 2 μs 100 μs 2 3V step, DEN = high or low 3.5 μs Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: Guaranteed by design. Note 3: VOUT at the end of the 10μs hold time is within specified % of VIN during the sample window; a 2.5kΩ resistor connected in series to both VINP and VINN (VINP - VINN = 1V). External capacitance to ground for both VINP and VINN is approximately 10pF. Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin must be low for a short period of time, tDEL, before the input changes. Note 5: VOUT at the end of the hold time is within 1% of VIN during the sample window (VINP - VINN = 1V). Note 6: Voltage step applied across VOUTP to VOUTN through a 5pF capacitor connected to each pin. This models the load presented by an ADC while it is sampling the DS1843’s output. See the Output Buffer section. Settled within 1% of initial voltage. Timing Diagram VINP - VINN tS tDEL SEN tOUT tHOLD VOLTAGE INVALID VOUTP - VOUTN tREC tADC:ST tADC:CT EXTERNAL ADC DATA DATA VALID tADC:ST = EXTERNAL ADC SAMPLING TIME. tADC:CT = EXTERNAL ADC CONVERSION TIME. DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT. NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS. _______________________________________________________________________________________ 3 DS1843 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ICC vs. TEMPERATURE ICC (mA) ICC (mA) VCC = 5V 5.9 5.7 5.4 5.3 VCC = 3.3V 5.5 5.3 3.5 4.0 5.9 5.7 5.5 3.0 VCC = 5V 6.1 VCC = 3.3V DEN = VCC 2.5 DEN = GND 6.3 6.1 5.6 5.5 DEN = VCC 6.3 DEN = GND 5.7 ICC vs. TEMPERATURE 6.5 DS1843 toc02 DS1843 toc01 5.8 4.5 5.0 5.5 5.3 -40 -15 10 35 60 85 -40 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) OUTPUT HOLD TIME vs. TEMPERATURE OUTPUT HOLD TIME vs. TEMPERATURE DIFFERENTIAL OUTPUT DURING SAMPLING (VINP = 6mV) 100 DEN = VCC 10 1 DS1843 toc06 1000 OUTPUT HOLD TIME (SECONDS) DS1843 toc04 1000 100mV/div VOUTP 1.5V/div 100 VOUTN VSEN DEN = GND 10 VOUTP - VOUTN 5mV/div 1 -40 -15 10 35 60 85 -40 -15 10 35 85 60 TEMPERATURE (°C) TEMPERATURE (°C) SINGLE-ENDED OUTPUT DURING SAMPLING (VINP = 6mV) DIFFERENTIAL OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 6mV) DS1843 toc07 500ns/div SINGLE-ENDED OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 6mV) DS1843 toc09 DS1843 toc08 VSEN 100mV/div VOUTP VSEN VCC = 3.3V 1.5V/div 100mV/div VOUTP ZOOMED 500ns/div VOUTN VSEN 2.0V/div VCC = 3.3V 1V/div VCC = 3.0V VOUTP ZOOM VOUTP - VOUTN 2mV/div VCC = 3.0V 5mV/div 100mV/div 20ns/div 4 -15 VCC (V) DS1843 toc05 ICC (mA) 6.5 DS1843 toc03 ICC vs. VCC 5.9 OUTPUT HOLD TIME (SECONDS) DS1843 Fast Sample-and-Hold Circuit 100μs/div VOUTP 100μs/div _______________________________________________________________________________________ Fast Sample-and-Hold Circuit DIFFERENTIAL OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 1V) SINGLE-ENDED OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 1V) DS1843 toc10 DS1843 toc11 VSEN DS1843 toc12 VSEN 2V/div VCC = 3.3V VOUTP (200mV/div) VOUTN (200mV/div) 2V/div VCC = 3.3V VOUTP VCC = 3.0V DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 6mV) VOUTN VSEN (1V/div) 1V/div 200mV/div VOUTP - VOUTN VOUTP - VOUTN VCC = 3V 200mV/div VOUTP 10mV/div 1V/div 100μs/div 100μs/div 50μs/div SINGLE-ENDED STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V) SINGLE-ENDED OUTPUT, STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V, ZOOMED IN) DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V) DS1843 toc13 DS1843 toc14 DS1843 toc15 VOUTP (200mV/div) VSEN (1V/div) VOUTP (200mV/div) OUTPUT STEP (200mV/div) VSEN (1V/div) VOUTN (200mV/div) 500mV/div VOUTP - VOUTN VOUTP STEP (200mV/div) VOUTP 200mV/div 500mV/div 50μs/div 50μs/div 50ns/div DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V, ZOOMED IN) DS1843 toc16 200mV/div VOUTP VOUTP - VOUTN (200mV/div) VOUTN (200mV/div) 50ns/div _______________________________________________________________________________________ 5 DS1843 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Fast Sample-and-Hold Circuit DS1843 Pin Description PIN NAME 1 VCC FUNCTION 2 VINP Positive Voltage Input. Input to sample circuit. 3 VINN Negative Voltage Input. Input to sample circuit. 4 DEN Differential Output Enable. Connect to VCC for differential output or GND for single-ended output. 5 GND Power-Supply Input Ground Terminal 6 VOUTN Sampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or connect to GND for single-ended output mode. 7 VOUTP Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor. 8 SEN Sample Enable. Enables input sampling. This input is pulsed. Block Diagram DS1843 VCC VINP VOUTN CIN CIN CS VOUTP CS DEN VINN SEN CONTROL LOGIC GND Detailed Description The DS1843 consists of a fully differential sampling capacitor, switches, and a differential output buffer. It is designed to operate in fiber optic burst-mode systems; however, it can be used in other applications requiring a fast sample-and-hold circuit. The output can be configured for single-ended operations. Input Sampling Capacitor The input voltage is sampled using a 5pF capacitor on the positive input and another on the negative input. The capacitors are connected to the input when SEN is high. In addition to the sampling capacitors, the inputs 6 also have parasitic capacitance (CIN). These capacitors must fully charge before SEN is switched to low in order to ensure accurate sampling. An RC time constant is created by the resistance of the voltage source connected to the DS1843’s input and the capacitances on this node. See the Applications Information section for details. Output Buffer After sampling is complete, the sampling capacitor is switched to the output buffer. This buffer requires a small amount of time to settle, tOUT. When an ADC is used to measure the DS1843’s output, a step occurs at the ADC’s input caused by the ADC’s internal sampling capacitor. The DS1843’s recovery time, tREC, is dependent on the size of the ADC’s sampling capacitor and the voltage applied across the ADC. To maximize accuracy, the ADC’s sampling speed (ADC clock frequency) should be reduced until the ADC’s conversion window (tADC:ST, as shown in the Timing Diagram) is larger than the DS1843’s recovery time. Refer to the ADC’s documentation for tADC:ST. Sampling Time and Output Error As the sampling time (tS) is decreased, the output error increases. The output error is largely dependent on the settling time of the sampling capacitor and, to a lesser degree, the output buffer’s gain error and offset voltage. Settling time can be reduced by driving the DS1843 with a lower impedance. In a typical fiber optic application, a current is applied across a 5kΩ resistor. By using a stronger current source, the resistance and the settling time can be reduced (see the Applications Information section for details). _______________________________________________________________________________________ Fast Sample-and-Hold Circuit INPUT MODEL RSW VINP CPAR DS1843 DS1843 CURRENT MIRROR OUTPUT CIN CS RIN VINN CIN CS RSW Figure 1. Input Impedances for Settling Time Calculations Diagram Applications Information Power-Supply Decoupling To achieve the best results when using the DS1843, decouple the power-supply pin, VCC, with a 0.01μF or 0.1μF capacitor. Use a high-quality X7R or equivalent ceramic surface-mount capacitor. DS1843 Estimated Settling Time The settling time is dependent on the gain ratio of the current mirror used at the input of the DS1843. For example, the MAX4007 includes a 10:1 ratio current mirror. This requires a 5kΩ resistor to create a 1V fullscale output with 2mA current input to the MAX4007. This resistor can be decreased to 2.5kΩ by using the DS1842, which has a 5:1 ratio current mirror. Variable Definitions: RIN: Input resistor. The current mirror creates a voltage across this resistor. RSW: Resistance of series switch that connects internal circuitry to input pins after tIST time. CIN: 7pF parasitic (ESD) capacitor. CPAR: External parasitic capacitance. A current mirror's output and typical trace capacitance are less than 10pF. CS: 5pF sample capacitor. tIST: Internal settling time based on tS from the AC electrical specification. The minimum tS includes one time constant. tIST removes this time constant. tRC: RC settling time of the input. Figure 1 shows the simplified diagram of input impedances for settling time calculations. Sample time is divided into two parts: 1) tIST: Internal settling time (max 250ns). During this time, voltage VIN (VINP - VINN) rises with a time constant of: RIN x (CIN + CPAR) 2) tRC: During this period two things happen: a. Input VIN keeps increasing from its value at tIST to its final value with a new time constant of: ( ) 2 2⎫ ⎧ ⎨ RIN × ( C IN + C PAR ) + ( R SW × C S ) ⎬ ⎩ ⎭ b. RSW and CS track this VIN (input) with a time constant of RSW x CS, which is 12.5ns (worst case). Example: Approximate accuracy calculations can be done for an input voltage based on the above impedance values. These calculations can be divided into three parts. 1) Accuracy of input at tIST (250ns): − t1 ⎡ RIN × ( C IN + C PAR ) ⎤ ⎦ Accuracy = 1 − e ⎣ where t1 = tIST = 250ns. At tIST the internal circuit tags input impedance. This causes charge redistribution to occur, which causes a dip in the input voltage. The worst-case value of the input voltage at tIST is: VIN @ t IST − t IST ⎡ ⎡ ⎤ ⎢ CS ⎡ RIN × ( C IN + C PAR ) ⎤ ⎦ = ⎢1 − ⎥ × ⎢1 − e ⎣ ( CIN + C PAR + C S ) ⎥⎦ ⎢ ⎢⎣ ⎢⎣ ⎤ ⎥ ⎥ × VIN ⎥ ⎥⎦ _______________________________________________________________________________________ 7 Pin Configuration 2) Accuracy of internal circuitry between tS - tIST: Accuracy = 1 − e −t 2 (R SW × C S ) TOP VIEW where t2 = (tS - tIST) and (RSW x CS) ~ = 12ns. + DS1843 Fast Sample-and-Hold Circuit 3) Total accuracy of input at sampling time, tS: −t 2 ⎡ Accuracy = ⎢1 − 1 − VIN @ t IST × e newRC ⎢ ⎣ ( where newRC = ) ( −t 2 ⎤ ⎤ ⎡ ⎥ × ⎢1 − e ( R SW × C S ) ⎥ ⎥ ⎥ ⎢ ⎥ ⎦ ⎢⎣ ⎦ VCC 1 VINP 2 8 SEN 7 VOUTP DS1843 ) 2 2⎫ ⎧ ⎨ RIN × ( C IN + C PAR ) + ( R SW × C S ) ⎬ ⎭ ⎩ VINN 3 6 VOUTN DEN 4 5 GND μDFN (2mm × 2mm) Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 μDFN L822+1 21-0164 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.