DEM-ADS7843E/45E ® EVALUATION FIXTURE FEATURES DESCRIPTION ● STAND-ALONE CAPABILITY The DEM-ADS7843E/45E evaluation fixture is designed for quick evaluation of Burr-Brown’s ADS7843E (4-wire) and ADS7845E (5-wire) touchpanel controllers. The board has features that allow the user to evaluate all the functions of the analog-todigital converter. The options offered to the user include a flexible clock generator circuit, an analog breadboard area, a digital breadboard area, and an easily-configurable voltage reference. The DEMADS7843E/45E has been designed to accommodate stand-alone operation, allowing the user to easily connect directly to 4-wire (ADS7843E) or 5-wire (ADS7845E) touch-screen panels and to an external processor. This evaluation fixture has a quick-release socket for easy evaluation of mulitiple converters or a solder footprint to allow the user to solder the DUT directly to the board. ● FLEXIBLE CLOCK PROGRAMMING ● USER-CONFIGURABLE A/D CONVERTER OPERATION ● ANALOG BREADBOARD AREA ● DIGITAL BREADBOARD AREA ● FLEXIBLE REFERENCE VOLTAGE PROGRAMMING APPLICATIONS ● DATA ACQUISTION ● PERSONAL DIGITAL ASSISTANTS ● 4- OR 5-WIRE RESISTIVE TOUCH SCREEN ● PORTABLE INSTRUMENTS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation LI-522A 1 Printed in U.S.A.March, 1999 DEM-ADS7843E/45E INSTALLATION is the position X1, which is a solder location for the DUT. If this option is chosen, the user must solder the DUT directly to the board. This position is only useful for 2 or 3 solder cycles. The DEM-ADS7843E/45E evaluation fixture is designed for stand-alone evaluation or evaluation using the clocking network on the board. Stand-alone evaluations imply that the A/D converter is powered by J4 (power supply connector) and the user is put to the task to provide analog and digital input excitation. This is achieved by removing all five jumper tops of JP4 and using J1 and J2 for direct connections to the device under test (DUT). CAUTION: DO NOT connect the a device into the DUT1 socket and have another device soldered to the board in position X1 at the same time. The additional equipment required to do a complete evaluation of the performance of the ADS7843E or ADS7845E comprises of: In contrast, the DEM-ADS7843E/45E/45E board has the appropriate digital interface circuitry to drive the DUT data clock, chip select, and serial data in which is coordinated with the BUSY and PENIRQ to provide serial and parallel output data. +5VDC power supply Voltage or current signal source 4-Wire (ADS7843E) or 5-Wire (ADS7845E) Resistive Touch Screen This kit includes the following items: To install the DEM-ADS7843E/45E evaluation fixture, connect the appropriate power supply to J4. When power is applied to the DEM-ADS7843E/45E, the red LED on the board should light. ADS7843E Evaluation Fixture—A2518 DEM-ADS7843E/45E Documentation (LI-522) ADS7843E (5 samples) ADS7845E (5 samples) The DEM-ADS7843E evaluation fixture has two positions on the board for the A/D converter to be installed in. The first position is the socket, DUT1 on the board. This springloaded socket allows the user to quickly swap in or out the device that is being evaluated. The other option on the board J1 Analog Input Interface. Each connector is labeled. J2 Digital I/O Interface. Each connector is labeled. J3 Parallel Output Port. J4 Power Supply Connector. This connector powers the DUT and digital network. Refer to the ADS7843 or ADS7845 product data sheet for power supply restrictions. All digital chips on the DEM-ADS7843E/45E board are capable of operating with supply voltage from 2.7V to 5.25V. P1 External DCLK Connector. USER CONFIGURATIONS The DEM-ADS7843E/45E evaluation fixture provides the right combination of jumper options and support circuitry to allow for a variety of evaluation configurations. Throughout this data sheet, numerous references are made to the ADS7843 and ADS7845 A/D converters. For more information concerning these devices, refer to the ADS7843 or ADS7845 data sheet. The circuit is laid out with a four-layer board. The two outside layers are for circuit traces and the inner layers are the ground and power planes. The analog and digital planes of the circuit is separated through the middle of the board all the way to the power supply connector, where they are joined. The circuit diagram and layout diagrams for the DEM-ADS7843E/45E is shown in Figure 1 and Figures 4 through 7. TABLE I. Connectors (Jx and P1) Assignments. JUMPER NUMBER JP1 FACTORY SETTING B JP2, JP11, JP10 JP2 = Not Installed JP11 = Not Installed JP10 = Not Installed JP3 D, F, G JP4 A, B, C, D, E DESCRIPTION Voltage reference. This setting connects A/D converter reference to +VCC. Inverted or non-inverted option for PENIRQ of the ADS7843 or ADS7845 when driving this pin through pin 2. This setting sets this pin HIGH and connects this pin to J2. Hardwire digital jumpers for DIN serial code. This setting configures the A/D converter for S = HIGH, A2-A0 = 001, MODE = LOW, SGL/DIF = HIGH, PD1-PD0 = 11. This jumper connects the clocking network to the DUT. JP5, JP6 JP5 = A JP6 = B Clock speed options. This configuration sets the board using Y1/10 as the DCLK frequency. JP7, JP8 JP7 = B JP8 = A Optional 16- or 24-bit operation. This configuration sets the board for 16 DCLK per conversion cycle. JP9 B Used to personalize the board for the ADS7843 or ADS7845. Position B = ADS7843 or ADS7845. TABLE II. Jumper (JPx) Assignments. ® DEM-ADS7843E/45E 2 DUT CONNECTIONS The digital I/O pins of the DUT may be driven or monitored with the J2 connector. The assignment of these pins are summarized in Table V. The DEM-ADS7843E/45E DUT Board has a socket for the DUT which is positioned in the DUT1 position. Additionally, it has a solder footprint in the event that the user chooses to solder the DUT directly to the board. This footprint is poisitioned in X1, just below the DUT1 socket. If the solder footprint is used, care should be taken to preserve the solder pads for repeated soldering. Bad X1 solder pads do not interfere with the operation or connections of the DUT1 socket. J2 PIN NUMBER (From Left to Right) The DEM-ADS7843E/45E evaluation fixture is designed to evaluate both the ADS7843 and ADS7845 A/D converters. JP9 must be in position B to evaluate either the ADS7843 or ADS7845. B The power supply from J4 is configured to pin 9 (VREF) of the DUT. C 2.5V is configured to pin 9 (VREF) of the DUT. DCLK 3 BUSY 4 DIN 5 PENIRQ 6 DOUT The DUT can be evaluated in a stand-alone configuration by removing all of the jumper tops of JP4. JP4 connects pins 12, 13, 14, 15, and 16 of the DUT to the digital interface circuitry of the board. If the array of jumper tops are not removed, the user may find significant conflicts on the digital I/O lines of the DUT. The details of this interface circuitry is discussed in detail in the “Digital Interface” section of this data sheet. DIGITAL INTERFACE CIRCUITRY The DUT can be evaluated using the digital clocking circuitry on the board by installing all of the jumper tops of JP4 and removing any signal present on the J2 connector. This digital circuit uses the clock signal from P1 (External Clock) or Y1 to create the DUT clock (DCLK), CS, and the DIN code to the device while providing a serial or parallel output signal from the DOUT pin of the DUT. RESULTING CONFIGURATION 1.2V is configured to pin 9 (VREF) of the DUT. CS 2 STAND-ALONE OPERATION The voltage reference to the DUT is programmed in the JP1. The JP1 options are given in Table III. A 1 TABLE V. J2 Connector Contacts versus DUT Pins. (NOTE: If you have a DEM-ADS7843E/45E, Revision A, the silkscreen is in error. The above description is correct.) Space for an R/C input filter has been provided to allow user customization for the particular application. Shorting bars have been installed in R3, R5, R7, R9, R10, and R12 positions on the board. These are positioned betwen the input of the DUT and the pin connector, P1. Shorting bars were used to allow for immediate evaluation of a four-wire touch screen. In this situation, the touch screen would provide the source resistance. If resistors are desired in positions R3, R5, R7, R9, R10, and R12, the user can solder in the desired values. Additionally, positions for capacitors at the input of the DUT are provided with C3, C4, C5, C6, C9 and C10. Once again, the user must install appropriate values for the application under evaluation. POSITION ADS7843 PIN DESCRIPTION TABLE III. VREF is Programmed Using JP1 Position Options. Clock Control The master clock to the board is set with the JP6 jumper. Position A of the JP6 jumper configures the External Clock (P1) coax connector into the circuit. It is recommended that this signal be a logic square wave. The signal from this connector will be used directly for the DCLK signal to the The combination of JP2 allows jumper programmable settings of the PENIRQ of the ADS7843 or ADS7845 pin of the DUT. Additionally, this pin can be accessed through J2 and a combination of JP10 and JP11. Refer to Table IV for jumper position details. Refer to the ADS7845 data sheet for additional options. JP2 POSITION JP10 POSITION JP11 POSITION Not Installed Not Installed Not Installed RESULTING CONFIGURATION Pin 11 of the DUT is HIGH. Not Installed Installed Not Installed Pin 11 of the DUT is connected to position 5 of J2. If there is no connection to position 5 of J2, pin 11 of the DUT will default HIGH. Not Installed Not Installed Installed Pin 11 of the DUT is inverted and connected to position 5 of J2. If there is no connection to position 5 of J2, pin 11 of the DUT will default HIGH. Installed Not Installed Not Installed Pin 11 of the DUT is LOW. Installed Installed Not Installed Pin 11 of the DUT is connected to position 5 of J2. If there is no connection to position 5 of J2, pin 11 of the DUT will default LOW. Installed Not Installed Installed Pin 11 of the DUT is inverted and connected to position 5 of J2. If there is no connection to position 5 of J2, pin 11 of the DUT will default LOW. TABLE IV. PENIRQ (ADS7843 or ADS7845) Jumper Settings. 3 ® DEM-ADS7843E/45E DIN Programming DUT. Refer to the ADS7843 or ADS7845 data sheet for the proper restrictions on this clock. Alternatively, a clock oscillator that is installed in Y1 can be used as the master clock. The signal from this device is either divided by 10 or divided by 20 per JP5. The settings from JP5 are listed in Table VI. JUMPER SETTING The DIN input (DUT, pin 14) receives an 8-bit serial input data stream which programs the ADS7843 or ADS7845 X or Y input channel, mode and power-down options. This serial stream can be programmed with JP3. JP3 is essentailly an 8bit parallel configuration which is processed by a parallel-toserial converter (U8) and then transmitted to the DUT at the appropriate time. Even when a position on JP3 is jumper top configured, digital gates can over drive their settings. Consequently, these lines are also connected to the digital breadboard area, which gives the user more flexibility in terms of programming this serial command byte. RESULTING CONFIGURATION A Y1 Frequency divided by 10. In conjunction with JP6 = B, this frequency becomes DCLK for the DUT. B Y1 frequency divided by 20. In conjunction with JP6 = B, this frequency becomes DCLK for the DUT. Parallel Output The combination of U13 and U14 converts the digital output of the DUT into a parallel word. This parallel word appears on the connector J3. A DVALID trigger is also provided on J3. Refer to Table VIII for the J3 connector configuration. TABLE VI. Jumper Settings for Using Y1 as Master Clock. Clocks per Conversion Control Once DCLK is set (per clock control instructions) the conversion cycle of the DUT can be configured to either take 16 or 24 clock cycles. The jumper configuration for these two modes of operation are shown in Table VII. Additionally, the timing diagram of these two modes of operation are shown in Figures 2 and 3. JP7 JP8 RESULTING CONFIGURATION A B 24 DCLK cycles per conversion B A 16 DCLK cycles per conversion TABLE VII. The Digital Support Circuitry Can be Operated in a 16 Clocks per Conversion or a 24 Clocks per Conversion with the Jumper Settings Described in the Table. Refer to Figures 2 and 3 for specific timing. J3 PIN DESCRIPTION 1 DVALID 11 LSB 13 LSB + 1 15 LSB + 2 17 LSB + 3 19 LSB + 4 21 LSB + 5 23 LSB + 6 25 LSB + 7 27 LSB + 8 29 LSB + 9 31 LSB + 10 33 MSB 3, 5, 7, 9 Digital LOW 35 through 50 Open All Even Pins GND TABLE VIII. J3 Configuration. ® DEM-ADS7843E/45E 4 PART LOCATION NUMBER PER KIT PART NUMBER VENDOR DESCRIPTION 1 A-2518 Rev B X1 (not installed) 1 Accepts ADS7843E and ADS7845E Burr-Brown ADS7843E Bare Board 12-bit A/D converter solder land area, parts not installed U1 1 REF1004C-1.2 Burr-Brown 1.235V Reference, SOIC U2 1 REF1004C-2.5 Burr-Brown 2.5V Reference, SOIC DUT 5 ADS7843E Burr-Brown 12-bit Touch Screen A/D Converter (4-wire panel) DUT 5 ADS7845E Burr-Brown 12-bit Touch Screen A/D Converter (5-wire panel) DUT (socket) 1 OTS-16(24)-0.635-01 Enplas (TESCO) Dual, 4-bit, binary counter 16-lead SSOP socket U3, U5, U7 3 74HC393D TI(1) U4 1 74HC08D TI(1) Quadruple two-input positive AND gates U6 1 74HC04D TI(1) Hex Inverters U8 1 74HC166D TI(1) 8-bit parallel-load shift register 8-bit shift registers with output registers Decade counter, dual 4-bit U13, U14 2 SN74HC594D TI(1) U15 1 MC74HC390D TI(1) Y1 1 CTX129-ND DigiKey Y1 (socket) 1 1107741 Aries D1 Hewlett Packard(1) 32MHz clock oscillator, (CTS) 14-pin oscillator socket, DIP 1 HLMP-3201 R13 1 CRCW12062001F Dale 2kΩ, 1%, 0.125W, metal-film resistor R14 1 CRCW12061001F Dale 1kΩ, 1%, 0.125W, metal-film resistor 22.1kΩ, 1%, 0.125W, metal-film resistor R3, R5, R7, R9, R10, R12 Red LED Optional. Provided with shorts. Resistors not included. R15, R16 2 CRCW120622R1F Dale R1, R11 2 CRCW12061002F Dale 10kΩ, 1%, 0.125W, metal-film resistor R8, R18 2 CECW12061003F Dale 100kΩ, 1%, 0.125W, metal-film resistor R2, R4, R6 3 CRCW12061000F Dale 100Ω, 1%, 0.125W, metal-film resistor R17 1 CRCW12066810F Dale C1 1 T491B225K016AS Kemet C12, C14 through C25 13 C1206C104K5RAC Kemet 0.1µF surface-mount capacitor, X7R C3 through C6, C9, C10 681Ω, 1%, 0.125W, metal-film resistor 2.2µF capacitor, 16V Optional. Capacitor not included. C11, C13 2 T491C106K016AS Kemet 10µF polarized capacitors, 16V, 10% C2 1 C1206C103K5RAC Kemet 0.01µF, 50V, 10%, chip-ceramic, X7R C8 1 C320C104K5R5CA Kemet 0.1µF, 50V, 10%, ceramic JP1 1 TSW-103-07-T-D Samtec 2x3 JP2 1 TSW-101-07-T-D Samtec 2x1 JP3 1 TSW-108-07-T-D Samtec 2x8 JP4 1 TSW-105-07-T-D Samtec 2x5 JP5 through JP9 5 TSW-103-07-T-S Samtec 1x3 JP1, JP2, JP3 tops 3 SNT-100-BK-T Samtec Jumper Tops J1, J2, J4 pins 7 31024102 RIACON 2-pin terminal block pins, 3.5mm centers J1, J2, J4 tops 7 31165102 RIACON 2-pin terminal block tops, 3.5mm centers J3 1 IDH-50LP-S3-TG Robinson Nugent P1 1 47788 Pamona RN2 1 CSC10A-01-104F Dale RN1 1 CSC10A-01-103F Dale Rubber Feet 6 SJ5523-O-ND 3M 2 x 25, straight-through header w/shroud, 0.1" center spacing BNC right-angle, PC mount connector 10-pin SIP resistor network (100kΩ, 9R, 1C) 10-pin SIP resistor network (10kΩ, 9R, 1C) Bumpons NOTE: (1) Or equivalent. TABLE IX. Parts List for the DEM-ADS7843E/45E. ® 5 DEM-ADS7843E/45E Analog Workspace Bypass Capacitors +5V C14 0.10µF 50V 10% C15 0.10µF 50V 10% C16 0.10µF 50V 10% C20 0.10µF 50V 10% C21 0.10µF 50V 10% C22 0.10µF 50V 10% C23 0.10µF 50V 10% C24 0.10µF 50V 10% C25 0.10µF 50V 10% JP4 1 3 5 7 9 Dout Din Dclk CS Busy/Sync X+ Y+ X– Y– IN3 IN4 +5V 1 2 R3 0Ω X+ R5 0Ω Y+ C3 R7 0Ω J1A 1 2 GND R10 0Ω 1 2 R12 0Ω J2 0.125W 1% R6 100Ω Dclk 16 X+ 2 X+ CS 15 Y+ 3 Y+ Din 14 X– 4 X– Busy 13 Y– 5 6 C6 IN3 IN4 C9 R4 100Ω 2 1 0.125W 1% J2A Y– GND 2 1 0.125W 1% VCC 1 X– R9 0Ω C2 0.01µF 50V 10% DUT1 OTS-16(24)-0.635-02 C4 C5 J1B R2 100Ω C1 2.2µF 16V 10% 3 C10 2 Y– GND ADS7843E ADS7845E J1 +5V Dout 12 Penirq 11 IN3 7 IN3 VCC 10 IN4 8 IN4 VREF 9 +5V 1 JP9 +5V +5V R8 100kΩ 0.125W 1% R18 100kΩ 0.125W 1% JP10 2 1 J2B +5V C8 0.1µF 50V 10% DUT socket may be used or part may be soldered directly to PCB JP11 10 11 U6 74HC040 JP2 R11 10.0kΩ 0.125W 1% JP1 GND 1 2 3 4 5 6 +5V R17 681Ω 0.125W J4 1% 16V 10% 1 C12 0.10µF 50V 10% C11 10µF 16V 10% C13 10µF 2 R13 1.0kΩ 0.125W 1% R14 1.0kΩ 0.125W 1% R15 22.1Ω 0.125W 1% R16 22.1Ω 0.125W 1% U2 U1 1 2 LED HLMP-3201 RED 3 4 User Supply Input 8 NC1 CATHODE 2 6 NC2 CATHODE 1 7 NC3 NC5 5 ANODE NC4 REF1004-1.2 FIGURE 1a. ADS7843E and ADS7845E Evaluation Demo Board Analog Circuit Diagram. ® DEM-ADS7843E/45E +5V 6 1 2 3 4 NC1 NC2 NC3 ANODE CATHODE 2 CATHODE 1 NC5 NC4 REF1004-2.5 8 6 7 5 External Clk Input JP5 +5V 1 1 NC 2 P1 3 7 GND 2 OUT 8 3 5 6 7 QA QB QC QD 1 CKA 4 CKB Y1 U15 U15 +5V 14 CLR MC74HC390D 32MHz JP6 13 11 10 9 QA 15 CKA QB 12 CKB QC QD 14 CLR +5V 1 2 Dclk MC74HC390D 32MHz/10 = 3.2MHz/16 = 200kHz TTLOsc/10 = DUTCLK/(16-24) = Convert Dout Din Dclk CS Busy/Sync PD0 PD1 SER/DFR MODE A0 A1 A2 START U3 1 Dclk 1 CLK U3 2 CLR QA QB QC QD 3 4 5 6 1 2 3 U4 74HC08D 4 5 74HC393D 2 R1 10kΩ 0.125W 1% U5 1 2 +5V CL SH/LD CKINH CK SER A Din 13 B QH C D Din 13 E F G U8 H 9 15 6 7 1 2 3 4 5 10 11 12 14 9 U6 74HC04D U4 2 2 74HC08D 3 U5 3 4 5 6 QA QB QC QD 13 12 CLR 74HC393D CLK QA QB QC QD 11 10 9 8 CLR 74HC393D 1 +5V 4 U7 8 2 3 1 Dclk RN2 100kΩ U6 74HC04D 1 9 10 CLK U6 74HC04D 74HC166D Busy/Sync JP8 1 74HC08D 8 3 2 11 74HC08D JP7 1 U4 74HC393D 6 U4 CLR 12 13 3 4 5 6 QA QB QC QD CLK Digital Workspace 3 CLK 2 3 4 5 6 7 8 9 PD0 PD1 SER/DFR MODE A0 A1 A2 START 1 3 5 7 9 11 13 15 JP3 2 4 6 8 10 12 14 16 10 9 8 7 6 5 4 3 2 U7 QA QB QC QD 3 4 5 6 13 12 CLR 74HC393D CLK QA 11 QB 10 QC 9 QD 8 5 RN1 10kΩ 6 1 U6 74HC04D J3 U13 CLR 74HC393D +5V Dclk 14 12 10 11 13 SER RCK SRCLR SRCK RCLR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q17 DVALID (Low) (Low) (Low) (Low) LSB 15 1 2 3 4 5 6 7 9 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 18 SN74HC594D U14 POWER AND GROUND CHART REF. DES. DEVICE POWER PIN U1 U2 U3, U5, U7 U4 U6 U8 U13, U14 U15 REF1004-1.2 REF1004-2.5 74HC393N 74HC08N 74HC04N 74HC166N 74HC594N 74HC390N N/A N/A 16 14 14 16 16 16 GROUND PIN BYPASS CAP REF. DES. 4 4 8 7 7 8 8 8 N/A N/A C14, C15, C16 C20 C21 C22 C23, C24 C25 +5V 14 12 10 11 13 SER RCK SRCLR SRCK RCLR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q17 15 1 2 3 4 5 6 7 9 MSB SN74HC594D Spares 13 12 U6 74HC04D 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 FIGURE 1b. ADS7843E and ADS7845E Evaluation Demo Board Digital Circuit Diagram. ® 7 DEM-ADS7843E/45E CS 1 4 8 12 16 20 24 28 32 DCLK DCLK/16 Par-Ser SH/LD DIN S A2 A1 A0 MODE (START) SER/ DFR PD1 PD0 S A2 A1 A0 MODE (START) SER/ DFR PD1 PD0 BUSY (Sync) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (MSB) (MSB) (16 Clks) DVALID FIGURE 2. ADS7843E and ADS7845E Conversion Timing Diagram, 16 Clocks per Conversion. 1 4 8 12 16 20 24 28 32 DCLK DCLK/16 CS Par-Ser SH/LD DIN S A2 A1 A0 MODE (START) SER/ DFR PD1 PD0 S A2 A1 A0 MODE (START) SER/ DFR PD1 PD0 BUSY (Sync) DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (MSB) (MSB) (16 Clks) DVALID FIGURE 3. ADS7843E and ADS7845E Conversion Timing Diagram, 24 Clocks per Conversion. ® DEM-ADS7843E/45E 8 FIGURE 4. Component Side of the DEM-ADS7843E/45E Demonstration Board. FIGURE 5. Ground Plane of the DEM-ADS7843E/45E Demonstration Board. ® 9 DEM-ADS7843E/45E FIGURE 6. Power Plane of the DEM-ADS7843E/45E Demonstration Board. FIGURE 7. Solder Side of the DEM-ADS7843E/45E Demonstration Board. ® DEM-ADS7843E/45E 10 FIGURE 8. Component Side Silkscreen of the DEM-ADS7843E/45E Demonstration Board. FIGURE 9. Component Side Soldermask of the DEM-ADS7843E/45E Demonstration Board. ® 11 DEM-ADS7843E/45E FIGURE 10. Bottom Side Soldermask of the DEM-ADS7843E/45E Demonstration Board. ® DEM-ADS7843E/45E 12