DEM-ADS7815U EVALUATION FIXTURE ® FEATURES APPLICATIONS ● COMPUTER INTERFACE ● TRANSDUCER INTERFACE ● STAND-ALONE CAPABILITY ● MULTIPLEXED DAS ● BREADBOARD AREAS ● INPUT RANGE EASILY CONFIGURED FOR APPLICATION DESCRIPTION a gain of +2V/V to the converter. The voltage reference to the chip is generated by Burr-Brown’s REF1004-2.5 (U6) and buffered with the operational amplifier, U2. Additionally, the on board oscillator chip is used to generate a clock frequency of 25kHz to the DUT. Finally, the edge-triggered, D-type flip-flop array, U7 and U8 are enabled by tying OE to GND. The DEM-ADS7815U evaluation fixture is designed for quick evaluation of Burr-Brown’s ADS7814 and ADS7815 in the 28-pin SOIC package. Breadboard areas are provided with optional bipolar power supply connections to assist in the evaluation of various driver amplifiers or multiplexed input circuits. Additionally, the demonstration fixture has flexibility in its clocking circuit to allow for various fixed conversion rates. To further enhance the clocking network, an external off board clock can be connected through the BNC connector, P3. The DEM-ADS7815U has been designed to accommodate stand-alone operation, as well as interfacing to Burr-Brown’s DEM-CIB (Universal PC interface board). With this jumper configuration the digital portion of the circuit sets the DUT in a continuous conversion mode with the parallel digital output available on the connector P1, pins 1 through 31. DEM-ADS7815U BOARD DESCRIPTION All of the jumper functions for the DEM-ADS7815U are shown in Table I. These jumpers affect the circuit’s analog front-end, reference circuit, clocking circuit, and the digital interface to the connector, P1. GETTING STARTED For quick, first time evaluations, it is recommended that the board be powered with ±5V supplies to P4. P4 provides power to all the components on DEMADS7815U. The breadboard power connector, P5, provides power to the breadboard busses, +VS and –VS. For first time evaluations, P5 should not be used. The ground connection of both power connectors are tied together with the single ground plane. J1, J2, J5 J6 The factory set position of the jumpers are shown below. Used to configure reference voltage input. See Table III. J7 Enable/Disable for the DUT parallel digital output to P1. Position B manually enables the edge-triggered D-type flip-flops. Position A manually configures the output of the flip-flops into high impedance. When the DEM-CIB computer interface board is used, J7 should not be installed. J1 J2 J3 J4 = C, F = Installed = Installed =A JUMPER NAME J3, J4 J5 = Not Installed J6 = A J7 = B JUMPER FUNCTION Used to configure the input analog source to the driver amplifier (U1). See Table II. Used to configure the clock generation circuit. See Table IV. TABLE I. Description of Jumpers on DEM-ADS7815U Demonstration Fixture. With this jumper configuration the analog input signal path is configured to use P2 for the signal source with International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation LI-499 1 DEM-ADS7815U Printed in U.S.A. July, 1997 ANALOG INPUT CONFIGURATIONS User Designed Voltage Reference—The breadboard section includes a REF bus to allow for the integration of user designed voltage reference. When this option is used, it is recommended that J6 does not have a jumper installed. Analog Source Options: J1, J2, J5, and P2—The input of the A/D converter (DUT) can be driven by the high speed voltage feedback amplifier, OPA642 (U1) or by breadboard circuitry. The functions of the jumpers are summarized in Table II. ANALOG INPUT FUNCTION J1 J2 J5 C, F Installed Open C Installed Open Non-inverting input from P2 (G = 1 + R2/R1) with offset adjust enabled. C, F Installed Installed Inverting input from P2 (G = – R2/R1). B, D Installed Open Inverting input from P2 (G = – R2/R1) with offset adjust enabled. B, D Installed Installed Non-inverting input from breadboard IN bus through U1 (G = 1 + R2/R1). A, C, F Installed Open Non-inverting input from breadboard IN bus through U1 (G = +1). A, C Installed Open Non-inverting input from breadboard IN bus through U1 (G = 1 + R2/R1) with offset adjust enabled. A, C, F Installed Installed Inverting input from breadboard IN bus through U1 (G = 1 + R2/R1). A, B, D Installed Open Inverting input from breadboard IN bus through U1 (G = 1 + R2/R1) with offset adjust enabled. A, B, D Installed Installed Input from breadboard AIN bus, to input of DUT. D Open Open Non-inverting input from P2 (G = 1 + R2/R1). Buffered input from P2 (G = +1). CLOCK NETWORK AND DIGITAL INTERFACE Clock Network: J3, J4 and P3—The clock network includes U3 (10MHz oscillator) and U4 and U10 (clock divide network). The 10MHz signal from U3 is divided by 40 and finally buffered by U5. J3 provides power to U3, U4, and U10. To utilize the on board clock, J4 must have a jumper top in position A (see Table IV). If an external clock is used, the BNC connector P3 can be used along with a reconfiguration of J4. CLOCK OPTION No Jumper Connected Additionally, the user of the DEM-ADS7815U can use the board in a stand-alone mode, using P1 as the interface connection to a user designed interface. P1 PIN NUMBER Adjustable Voltage Reference—An adjustable reference is provided with the inclusion of the potentiometer, R6, and the jumper J6. The primary function of this portion of the circuit is to provide gain adjustment capability. The correct jumper configuration for this option is summarized in Table III. All Even Pins Odd Pins 1 - 31 Applies the on board reference (U6 and U2) to the reference pin of the DUT. Also allows for gain adjustment by using the potentiometer, R6, 2.5V nominal. Ground U7 and U8 external buffer output of the parallel digital output from the DUT. Enable/Disable for the DUT parallel digital output to P1. When P1-35 is LOW the edge-triggered D-type flip-flops are enabled. When P2-35 is HIGH, the flip-flops are placed into a high impedance mode. When the DEM-CIB Computer Interface Board is used, J7 should not be installed. 39 CS (Chip Select), connected to UX9 (DUT) pin 13 43 BUSY, connected to UX9 (DUT) pin 26 TABLE V. External Digital Interface Connector, P1 Pin Description. This configuration is used if the user is taking advantage of the breadboard area to design a custom reference circuit. TABLE III. Function of the Voltage Reference Jumper, J6. ® DEM-ADS7815U PIN DESCRIPTION 35 DESCRIPTION Applies the on board reference (U6 and U2) to the reference pin of the DUT, 2.5V nominal. No Jumper Installed On Board Clock The P1 connector is designed to interface to Burr-Brown’s Computer Interface Board, DEM-CIB. The DEM-CIB and accompanying Windows compatible program allows the performance of the ADS7814 and ADS7815 to be evaluated directly from a PC. Precision Voltage Reference—The ADS7814 and ADS7815 require an external voltage reference for proper operation. The DEM-ADS7815U board supplies that reference through U6, a 2.5V reference and U2, an operational amplifier that is used as a low impedance buffer to the reference pin of the DUT. If the on board reference is used in the evaluation, position A of J6 shorted with a jumper top, as shown in Table III. A, B No Jumper External Digital Interface—All critical digital lines are connected to the 25 x 2 pin connector, P1 (see Table V). The quad 2-input NAND Gate, U5 is used to insure that the proper timing of R/C, BUSY and CS are applied to the converter. For more details concerning the timing of the ADS7814 and ADS7815, refer to their respective product data sheets. EXTERNAL VOLTAGE REFERENCE OPTIONS A J3 Connected TABLE IV. Jumper Configuration of Clock Options on the DEM-ADS7815U Demonstration Fixture. TABLE II. The Jumper Settings for (J1, J2, and J5) are Used to Interface the DUT with the Analog Portion of the Demonstration Fixture, ie., the Amplifiers and the Breadboard Areas. J6 CONFIGURATION J4 External Clock (P3) 2 PART IDENTIFIER QUANTITY PART NUMBER DUT 1 ADS7815U DUT (socket) 1 SOP-28B-SMT-TT DUT (removal tool) 1 SOP-28B-REMTOOL U3 1 CTX114-ND(1) U3 (socket) 1 1107741 U1, U2 2 OPA642U(3) DESCRIPTION 16-Bit, High Speed, SAR, A/D Converter SMT SOP Socket, 28-Pin, 0.375 Row Spacing, Body and Frame, Robinson Nugent Frame Removal Tool for the DUT socket, Robinson Nugent Clock Oscillator, 10MHz, Digi-Key (CTS) 14-Pin Oscillator Socket, Aries High Speed, Single, Voltage Feedback, Operational Amplifier, Burr-Brown U4 1 74AC11074D(1) Dual, D-Type Flip-Flop, SOIC, TI U5 1 SN74HC00D(1) NAND Gate, Quad, 2 Input, SOIC, TI U6 1 REF1004C-2.5(2) U7, U8 2 74HC574D(1) Latch, Octal D-Type, 3-State Output, TI U10 1 74HC390D(1) Counter, Decade, Dual, 4-Bit, TI C1 - C4, C6, C10, C12, C17, C18, C20 - C23 13 C1206C104K5RAC(1) C5 1 CK05BX104K(1) Capacitor, 0.1µF, 10%, Ceramic X7R C7 1 CD5FC101503(1) Capacitor, Dipped Mica, 100pF, CDE C8, C9, C13 - C16 6 T491C225K025AS(1) Capacitor, 2.2µF, 25V, 10%, Tantalum Chip-Molded C11, C19 2 T491C106K025AS(1) Capacitor, 10µF, 20V, 10%, Tantalum Chip-Molded C24 1 T491C105K020AS(1) Capacitor, 1µF, 25V, 10%, Tantalum Chip-Molded J1 1 TSW-106-07-T-D(1) Jumper, 2 x 6, Terminal Strip, SAMTEC J2, J3, J5 3 TSW-101-07-T-D(1) Jumper, 1 x 2, Terminal Strip, SAMTEC J4, J6, J7 3 TSW-102-07-T-D(1) Jumper, 2 x 2, Terminal Strip, SAMTEC P1 1 IDH-50LP-SR3-TG(1) P2, P3 2 KC-79-274-M06(1) P4, P5 2 ED300/3 R1 1 RN55C75R0F(1) R2, R15 2 CRCW120675R0F(1) Resistor, 75Ω, 0.125W, 1%, Chip-Thick-Film R3, R9 2 CRCW120610R0F(1) Resistor, 710Ω, 0.125W, 1%, Chip-Thick-Film R4, R7, R8 3 CRCW12064992F(1) Resistor, 49.9kΩ, 0.125W, 1%, Chip-Thick-Film R5, R6 2 ST5W104CT-ND(1) R10 1 RN55C49R9F(1) R11, R12 2 4816P-1-101-ND(1) R13, R14 2 CRCW12061000F(1) Resistor, 100Ω, 0.125W, 1%, Chip-Thick-Film R16, R17, R19 3 CRCW12061002F(1) Resistor, 10kΩ, 0.125W, 1%, Chip-Thick-Film R18 1 CRCW12061621F(1) Jumper Tops 9 SNT-100-BK-T-H Rubber Feet 5 SJ5523-O-ND 1 A2207 2.5V Reference, Burr-Brown Capacitor, 0.01µF, 50V, 10%, chip-ceramic X7R Right Angle, Header 25 x 2 Robinson Nugent Connector BNC, PCB Mount, KING Terminal Block, 3 Pin, ON-SHORE Technology Resistor, 75Ω, 0.125W, 1%, Metal-Film Resistor, 100kΩ, 1/4W, 14 turn Potentiometer Resistor, 49.9Ω, 0.125W, 1%, Metal Film Resistor Network, 100Ω, Digi-Key (Bourns) Resistor, 1.62kΩ, 0.125W, 1%, Chip-Thick-Film Jumper Tops, Samtec Bumpons, 3M Bare Board Number NOTES: (1) Vender substitutions allowed providing specifications in description portion of table are met. (2) REF1004-2.5C from Burr-Brown is allowed as substitution. (3) OPA642UB from Burr-Brown is allowed as substitution. TABLE VI. Parts List for the DEM-ADS7815U. ® 3 DEM-ADS7815U FIGURE 1. Circuit Diagram of the DEM-ADS7815U Demonstration Fixture. ® DEM-ADS7815U 4 + C8 C17 + C9 U6 REF1004-2.5 8 6 7 5 C18 1 NC1 CATHODE2 2 NC2 CATHODE1 3 NC5 NC3 4 NC4 ANODE R8 49.9kΩ R18 1.62kΩ +5V R6 100kΩ +5V –5V R4 49.9kΩ INPUT Ext Analog In BB1 +5V R5 100kΩ P2 + 8 5 XU9 D15 AGND2 CAP Ref 6 –VS R7C CS BUSY +VS +VS C4 0.10µF AGND1 VIN –5V 4 U2 OPA642UB 7 C3 0.10µF R15 750Ω 23 24 25 26 27 28 3 2 8 22 D14 D0 ADS7815U 21 D13 U9 D1 9 20 D12 DUT D2 10 19 D11 D3 11 18 D10 D4 12 17 D9 D5 13 16 D8 D6 14 15 DGND D7 7 6 5 4 3 2 1 C24 1µF 3 2 R1 750Ω R7 49.9kΩ +5V Offset Adjust J5 J1 A B C D E F 8 5 –5V 4 C10 J6 A B + C11 +15V Gain Adjust R9 100Ω C2 0.10µF 6 C1 0.10µF U2 OPA642UB 7 +5V R2 750Ω R3 100Ω J2 J13 C12 Ref AIN C7 100pF +5V 14 13 12 11 10 9 4 5 6 7 8 9 8 3 10 7 15 11 6 2 12 5 16 13 4 1 14 3 16 2 U5 1 13 U5 12 8 9 15 R12 100Ω CK D CLR 12 U4 PR CK D CLR 10 U4 PR 74AC11074D 7 14 13 74AC11074D 1 2 1 R11 100Ω R13 3 SN74HC00D 5 6 11 U5 4 7 8 10MHz U3 CTX114-ND C + 19 –5V BB2 BB3 R16 10kΩ 14 C5 0.10µF VCLK 1 11 9 8 7 6 5 4 3 2 1 11 9 8 7 6 5 4 3 2 5 6 3 2 R14 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE CLK D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 U8 74HC574D OE CLK D7 D6 D5 D4 D3 D2 D1 D0 U7 74HC574D 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 13 QA 11 QB 10 QC 9 QD BUSY P1-39 P1-35 P1-17 P1-19 P1-21 P1-23 P1-25 P1-27 P1-29 D15 D14 D13 D12 D11 D10 D9 P1-1 P1-3 P1-5 P1-7 P1-8 P1-11 P1-13 Parallel Bus Out D8 P1-15 D7 D6 D5 D4 D3 D2 D1 U10 C20 U5 C21 +5V 9 8 10 U5 R17 10kΩ P1-33 Parallel Bus Out D0 P1-31 CONVERT OUT ENABLE U4 C6 VCLK 3 QA 5 QB 6 QC 7 QD 74HC390D 1 CKA 4 CKB U10 2 CLR 74HC390D 15 CKA 12 CKB U10 14 CLR R19 +5V 10kΩ J7 A B Q Q Q Q J4 U8 C23 BB12 BB11 BB10 BB9 BB15 BB8 BB14 BB7 P3 R10 49.9Ω Ext Clk In B U7 C22 A BB17 BB16 BB6 BB13 BB4 BB5 –VS +VS –5V +5V + + + + C16 2.2µF C15 2.2µF C14 2.2µF C13 2.2µF P5 P5 P5 P4 P4 P4 P1-2 P1-4 P1-6 P1-8 P1-10 P1-12 P1-14 P1-16 P1-18 P1-20 P1-22 P1-24 P1-26 P1-28 P1-30 P1-32 P1-34 P1-36 P1-38 P1-40 P1-42 P1-44 P1-46 P1-48 P1-50 FIGURE 2. Silkscreen of the DEM-ADS7815U Demonstration Fixture. FIGURE 3. Component Side of the DEM-ADS7815U Demonstration Fixture. ® 5 DEM-ADS7815U FIGURE 4. Top Soldermask of the DEM-ADS7815U Demonstration Fixture. FIGURE 5. Ground Plane of the DEM-ADS7815U Demonstration Fixture. ® DEM-ADS7815U 6